; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\drvgpio.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvgpio.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvgpio.crf ..\bsp\Driver\DrvGPIO.c]
                          THUMB

                          AREA ||i.DrvGPIO_Close||, CODE, READONLY, ALIGN=2

                  DrvGPIO_Close PROC
;;;146    /*---------------------------------------------------------------------------------------------------------*/
;;;147    int32_t DrvGPIO_Close(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a07              LDR      r2,|L1.32|
;;;148    {
;;;149    	GPIO_TypeDef *base;
;;;150    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;151    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;152    
;;;153    	base->PMD &= ~(0x3<<(i32Bit*2));
000006  6802              LDR      r2,[r0,#0]
000008  004b              LSLS     r3,r1,#1
00000a  2103              MOVS     r1,#3
00000c  4099              LSLS     r1,r1,r3
00000e  438a              BICS     r2,r2,r1
000010  6002              STR      r2,[r0,#0]
;;;154    
;;;155    	/* disable GPIO debounce clock */
;;;156    	GPIODBNCE->CON_BITS.DBCLKEN = 0;
000012  4904              LDR      r1,|L1.36|
000014  6808              LDR      r0,[r1,#0]
000016  2220              MOVS     r2,#0x20
000018  4390              BICS     r0,r0,r2
00001a  6008              STR      r0,[r1,#0]
;;;157    
;;;158    	/* disable GPIO clock */
;;;159    	//CLK->AHBCLK_BITS.GPIO_EN = 0;
;;;160    
;;;161    	return E_SUCCESS;
00001c  2000              MOVS     r0,#0
;;;162    }
00001e  4770              BX       lr
;;;163    
                          ENDP

                  |L1.32|
                          DCD      0x50004000
                  |L1.36|
                          DCD      0x50004180

                          AREA ||i.DrvGPIO_ClrBit||, CODE, READONLY, ALIGN=2

                  DrvGPIO_ClrBit PROC
;;;222    /*---------------------------------------------------------------------------------------------------------*/
;;;223    int32_t DrvGPIO_ClrBit(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a04              LDR      r2,|L2.20|
;;;224    {
;;;225    	GPIO_TypeDef *base;
;;;226    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;227    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;228    
;;;229    	base->DOUT &= ~(1 << i32Bit);
000006  6882              LDR      r2,[r0,#8]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  439a              BICS     r2,r2,r3
00000e  6082              STR      r2,[r0,#8]
;;;230    
;;;231    	return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;232    }
000012  4770              BX       lr
;;;233    
                          ENDP

                  |L2.20|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_ClrBitMask||, CODE, READONLY, ALIGN=2

                  DrvGPIO_ClrBitMask PROC
;;;387    /*---------------------------------------------------------------------------------------------------------*/
;;;388    int32_t DrvGPIO_ClrBitMask(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a04              LDR      r2,|L3.20|
;;;389    {
;;;390    	GPIO_TypeDef *base;
;;;391    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;392    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;393    
;;;394    	base->DMASK &= ~(1<<i32Bit);
000006  68c2              LDR      r2,[r0,#0xc]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  439a              BICS     r2,r2,r3
00000e  60c2              STR      r2,[r0,#0xc]
;;;395    
;;;396    	return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;397    }
000012  4770              BX       lr
;;;398    
                          ENDP

                  |L3.20|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_ClrPortMask||, CODE, READONLY, ALIGN=2

                  DrvGPIO_ClrPortMask PROC
;;;458    /*---------------------------------------------------------------------------------------------------------*/
;;;459    int32_t DrvGPIO_ClrPortMask(E_DRVGPIO_PORT port, int32_t i32MaskData)
000000  4a03              LDR      r2,|L4.16|
;;;460    {
;;;461    	GPIO_TypeDef *base;
;;;462    	assert_param(CHECK_GPIO_PORT(port));
;;;463    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;464    	base->DMASK &= ~i32MaskData;
000006  68c2              LDR      r2,[r0,#0xc]
000008  438a              BICS     r2,r2,r1
00000a  60c2              STR      r2,[r0,#0xc]
;;;465    
;;;466    	return E_SUCCESS;
00000c  2000              MOVS     r0,#0
;;;467    }
00000e  4770              BX       lr
;;;468    
                          ENDP

                  |L4.16|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_DisableDebounce||, CODE, READONLY, ALIGN=2

                  DrvGPIO_DisableDebounce PROC
;;;555    /*---------------------------------------------------------------------------------------------------------*/
;;;556    int32_t DrvGPIO_DisableDebounce(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a04              LDR      r2,|L5.20|
;;;557    {
;;;558    	GPIO_TypeDef *base;
;;;559    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;560    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;561    
;;;562    	base->DBEN &= ~(1<<i32Bit);
000006  6942              LDR      r2,[r0,#0x14]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  439a              BICS     r2,r2,r3
00000e  6142              STR      r2,[r0,#0x14]
;;;563    
;;;564    	return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;565    }
000012  4770              BX       lr
;;;566    
                          ENDP

                  |L5.20|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_DisableEINT0||, CODE, READONLY, ALIGN=2

                  DrvGPIO_DisableEINT0 PROC
;;;907    /*---------------------------------------------------------------------------------------------------------*/
;;;908    void DrvGPIO_DisableEINT0(void)
000000  b510              PUSH     {r4,lr}
;;;909    {
;;;910    	gGPIO_EXT0_Base->IER &= (~((1UL << gGPIO_EXT0_Pin) | (1UL << (gGPIO_EXT0_Pin + 16))));
000002  4c14              LDR      r4,|L6.84|
000004  2101              MOVS     r1,#1
000006  6a20              LDR      r0,[r4,#0x20]  ; gGPIO_EXT0_Pin
000008  460a              MOV      r2,r1
00000a  4082              LSLS     r2,r2,r0
00000c  3010              ADDS     r0,r0,#0x10
00000e  4081              LSLS     r1,r1,r0
000010  69a0              LDR      r0,[r4,#0x18]  ; gGPIO_EXT0_Base
000012  430a              ORRS     r2,r2,r1
000014  69c1              LDR      r1,[r0,#0x1c]
000016  4391              BICS     r1,r1,r2
000018  61c1              STR      r1,[r0,#0x1c]
;;;911    	NVIC_DisableIRQ(EINT0_IRQn);
00001a  2002              MOVS     r0,#2
00001c  f7fffffe          BL       NVIC_DisableIRQ
;;;912    
;;;913    	GCR->PB_H_MFP_BITS.PB8 = 0;
000020  2005              MOVS     r0,#5
000022  0700              LSLS     r0,r0,#28
000024  6bc1              LDR      r1,[r0,#0x3c]
000026  08c9              LSRS     r1,r1,#3
000028  00c9              LSLS     r1,r1,#3
00002a  63c1              STR      r1,[r0,#0x3c]
;;;914    	GCR->PB_H_MFP_BITS.PB9 = 0;
00002c  6bc1              LDR      r1,[r0,#0x3c]
00002e  2270              MOVS     r2,#0x70
000030  4391              BICS     r1,r1,r2
000032  63c1              STR      r1,[r0,#0x3c]
;;;915    	GCR->PB_H_MFP_BITS.PB14 = 0;
000034  6bc1              LDR      r1,[r0,#0x3c]
000036  0512              LSLS     r2,r2,#20
000038  4391              BICS     r1,r1,r2
00003a  63c1              STR      r1,[r0,#0x3c]
;;;916    	GCR->PC_H_MFP_BITS.PC12 = 0;
00003c  4806              LDR      r0,|L6.88|
00003e  6841              LDR      r1,[r0,#4]
000040  1212              ASRS     r2,r2,#8
000042  4391              BICS     r1,r1,r2
000044  6041              STR      r1,[r0,#4]
;;;917    	GCR->PF_L_MFP_BITS.PF0 = 0;
000046  6981              LDR      r1,[r0,#0x18]
000048  08c9              LSRS     r1,r1,#3
00004a  00c9              LSLS     r1,r1,#3
00004c  6181              STR      r1,[r0,#0x18]
;;;918    	gIsEXT0_Config = 0;
00004e  2000              MOVS     r0,#0
000050  6020              STR      r0,[r4,#0]  ; gIsEXT0_Config
;;;919    }
000052  bd10              POP      {r4,pc}
;;;920    
                          ENDP

                  |L6.84|
                          DCD      ||.data||
                  |L6.88|
                          DCD      0x50000040

                          AREA ||i.DrvGPIO_DisableEINT1||, CODE, READONLY, ALIGN=2

                  DrvGPIO_DisableEINT1 PROC
;;;1081   /*---------------------------------------------------------------------------------------------------------*/
;;;1082   void DrvGPIO_DisableEINT1(void)
000000  b510              PUSH     {r4,lr}
;;;1083   {
;;;1084   	gGPIO_EXT1_Base->IER &= (~((1UL << gGPIO_EXT1_Pin) | (1UL << (gGPIO_EXT1_Pin + 16))));
000002  4c11              LDR      r4,|L7.72|
000004  2101              MOVS     r1,#1
000006  6a60              LDR      r0,[r4,#0x24]  ; gGPIO_EXT1_Pin
000008  460a              MOV      r2,r1
00000a  4082              LSLS     r2,r2,r0
00000c  3010              ADDS     r0,r0,#0x10
00000e  4081              LSLS     r1,r1,r0
000010  69e0              LDR      r0,[r4,#0x1c]  ; gGPIO_EXT1_Base
000012  430a              ORRS     r2,r2,r1
000014  69c1              LDR      r1,[r0,#0x1c]
000016  4391              BICS     r1,r1,r2
000018  61c1              STR      r1,[r0,#0x1c]
;;;1085   	NVIC_DisableIRQ(EINT1_IRQn);
00001a  2003              MOVS     r0,#3
00001c  f7fffffe          BL       NVIC_DisableIRQ
;;;1086   
;;;1087   	GCR->PB_H_MFP_BITS.PB15 = 0;
000020  2005              MOVS     r0,#5
000022  0700              LSLS     r0,r0,#28
000024  6bc1              LDR      r1,[r0,#0x3c]
000026  2207              MOVS     r2,#7
000028  0712              LSLS     r2,r2,#28
00002a  4391              BICS     r1,r1,r2
00002c  63c1              STR      r1,[r0,#0x3c]
;;;1088   	GCR->PC_H_MFP_BITS.PC13 = 0;
00002e  4807              LDR      r0,|L7.76|
000030  6841              LDR      r1,[r0,#4]
000032  1212              ASRS     r2,r2,#8
000034  4391              BICS     r1,r1,r2
000036  6041              STR      r1,[r0,#4]
;;;1089   	GCR->PF_L_MFP_BITS.PF1 = 0;
000038  6981              LDR      r1,[r0,#0x18]
00003a  2270              MOVS     r2,#0x70
00003c  4391              BICS     r1,r1,r2
00003e  6181              STR      r1,[r0,#0x18]
;;;1090   	gIsEXT1_Config = 0;
000040  2000              MOVS     r0,#0
000042  6060              STR      r0,[r4,#4]  ; gIsEXT1_Config
;;;1091   }
000044  bd10              POP      {r4,pc}
;;;1092   
                          ENDP

000046  0000              DCW      0x0000
                  |L7.72|
                          DCD      ||.data||
                  |L7.76|
                          DCD      0x50000040

                          AREA ||i.DrvGPIO_DisableInt||, CODE, READONLY, ALIGN=2

                  DrvGPIO_DisableInt PROC
;;;695    /*---------------------------------------------------------------------------------------------------------*/
;;;696    int32_t DrvGPIO_DisableInt(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  b510              PUSH     {r4,lr}
;;;697    {
000002  4604              MOV      r4,r0
;;;698    	GPIO_TypeDef *base;
;;;699    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;700    	base = (GPIO_TypeDef *)get_port_base(port);
000004  4a0f              LDR      r2,|L8.68|
000006  0180              LSLS     r0,r0,#6
000008  1880              ADDS     r0,r0,r2
;;;701    
;;;702    	base->IER &= ~((1<<i32Bit) | (1 << (i32Bit+16)));
00000a  2201              MOVS     r2,#1
00000c  4613              MOV      r3,r2
00000e  408b              LSLS     r3,r3,r1
000010  3110              ADDS     r1,r1,#0x10
000012  408a              LSLS     r2,r2,r1
000014  69c1              LDR      r1,[r0,#0x1c]
000016  4313              ORRS     r3,r3,r2
000018  4399              BICS     r1,r1,r3
00001a  61c1              STR      r1,[r0,#0x1c]
;;;703    
;;;704    	/* Disable the relative interrupt of M0 */
;;;705    	if ((port == E_GPA) || (port == E_GPB) || (port == E_GPC))
00001c  2c00              CMP      r4,#0
00001e  d003              BEQ      |L8.40|
000020  2c01              CMP      r4,#1
000022  d001              BEQ      |L8.40|
000024  2c02              CMP      r4,#2
000026  d102              BNE      |L8.46|
                  |L8.40|
;;;706    	{
;;;707    		NVIC_DisableIRQ(GPABC_IRQn);
000028  2004              MOVS     r0,#4
00002a  f7fffffe          BL       NVIC_DisableIRQ
                  |L8.46|
;;;708    	}
;;;709    
;;;710    	if ((port == E_GPD) || (port == E_GPE) || (port == E_GPF))
00002e  2c03              CMP      r4,#3
000030  d003              BEQ      |L8.58|
000032  2c04              CMP      r4,#4
000034  d001              BEQ      |L8.58|
000036  2c05              CMP      r4,#5
000038  d102              BNE      |L8.64|
                  |L8.58|
;;;711    	{
;;;712    		NVIC_DisableIRQ(GPDEF_IRQn);
00003a  2005              MOVS     r0,#5
00003c  f7fffffe          BL       NVIC_DisableIRQ
                  |L8.64|
;;;713    	}
;;;714    
;;;715    	return E_SUCCESS;
000040  2000              MOVS     r0,#0
;;;716    }
000042  bd10              POP      {r4,pc}
;;;717    
                          ENDP

                  |L8.68|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_DisablePullup||, CODE, READONLY, ALIGN=2

                  DrvGPIO_DisablePullup PROC
;;;505    /*---------------------------------------------------------------------------------------------------------*/
;;;506    int32_t DrvGPIO_DisablePullup(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a04              LDR      r2,|L9.20|
;;;507    {
;;;508    	GPIO_TypeDef *base;
;;;509    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;510    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;511    
;;;512    	base->PUEN &= ~(1<<i32Bit);
000006  6a42              LDR      r2,[r0,#0x24]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  439a              BICS     r2,r2,r3
00000e  6242              STR      r2,[r0,#0x24]
;;;513    
;;;514    	return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;515    }
000012  4770              BX       lr
;;;516    
                          ENDP

                  |L9.20|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_EnableDebounce||, CODE, READONLY, ALIGN=2

                  DrvGPIO_EnableDebounce PROC
;;;529    /*---------------------------------------------------------------------------------------------------------*/
;;;530    int32_t DrvGPIO_EnableDebounce(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a07              LDR      r2,|L10.32|
;;;531    {
;;;532    	GPIO_TypeDef *base;
;;;533    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;534    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;535    
;;;536    	base->DBEN |= (1<<i32Bit);
000006  6942              LDR      r2,[r0,#0x14]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  431a              ORRS     r2,r2,r3
00000e  6142              STR      r2,[r0,#0x14]
;;;537    
;;;538    	GPIODBNCE->CON_BITS.DBCLKEN = 1;
000010  4804              LDR      r0,|L10.36|
000012  6801              LDR      r1,[r0,#0]
000014  2220              MOVS     r2,#0x20
000016  4311              ORRS     r1,r1,r2
000018  6001              STR      r1,[r0,#0]
;;;539    
;;;540    	return E_SUCCESS;
00001a  2000              MOVS     r0,#0
;;;541    }
00001c  4770              BX       lr
;;;542    
                          ENDP

00001e  0000              DCW      0x0000
                  |L10.32|
                          DCD      0x50004000
                  |L10.36|
                          DCD      0x50004180

                          AREA ||i.DrvGPIO_EnableEINT0||, CODE, READONLY, ALIGN=2

                  DrvGPIO_EnableEINT0 PROC
;;;758    /*---------------------------------------------------------------------------------------------------------*/
;;;759    void DrvGPIO_EnableEINT0(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode, GPIO_EINT0_CALLBACK pfEINT0Callback)
000000  b570              PUSH     {r4-r6,lr}
;;;760    {
;;;761    	assert_param(CHECK_GPIO_INTTYPE(TriggerType, Mode));
;;;762    
;;;763    	_pfEINT0Callback = pfEINT0Callback;
000002  4b1a              LDR      r3,|L11.108|
;;;764    
;;;765    	gPreGPIO_EXT0 = E_EXT0_GPB14;
000004  611a              STR      r2,[r3,#0x10]  ; _pfEINT0Callback
000006  2202              MOVS     r2,#2
;;;766    	GCR->PB_H_MFP_BITS.PB14 = 0x1;
000008  629a              STR      r2,[r3,#0x28]  ; gPreGPIO_EXT0
00000a  2205              MOVS     r2,#5
00000c  0712              LSLS     r2,r2,#28
00000e  6bd4              LDR      r4,[r2,#0x3c]
000010  2507              MOVS     r5,#7
000012  062d              LSLS     r5,r5,#24
000014  43ac              BICS     r4,r4,r5
000016  2501              MOVS     r5,#1
000018  062d              LSLS     r5,r5,#24
00001a  1964              ADDS     r4,r4,r5
00001c  63d4              STR      r4,[r2,#0x3c]
;;;767    	gGPIO_EXT0_Base = GPIOB;
00001e  4a14              LDR      r2,|L11.112|
;;;768    	gGPIO_EXT0_Pin = 14;
000020  240e              MOVS     r4,#0xe
;;;769    
;;;770    	if(TriggerType == E_IO_RISING)
;;;771    	{
;;;772    		gGPIO_EXT0_Base->IER |= (1 << (gGPIO_EXT0_Pin + 16));
;;;773    	}
;;;774    	else if(TriggerType == E_IO_FALLING)
;;;775    	{
;;;776    		gGPIO_EXT0_Base->IER |= (1 << gGPIO_EXT0_Pin);
000022  621c              STR      r4,[r3,#0x20]  ; gGPIO_EXT0_Pin
000024  0615              LSLS     r5,r2,#24             ;772
000026  142c              ASRS     r4,r5,#16
000028  2601              MOVS     r6,#1                 ;772
00002a  619a              STR      r2,[r3,#0x18]  ; gGPIO_EXT0_Base
00002c  2800              CMP      r0,#0                 ;770
00002e  d004              BEQ      |L11.58|
000030  2801              CMP      r0,#1                 ;774
000032  d004              BEQ      |L11.62|
;;;777    	}
;;;778    	else if(TriggerType == E_IO_BOTH_EDGE)
000034  2802              CMP      r0,#2
000036  d005              BEQ      |L11.68|
000038  e008              B        |L11.76|
                  |L11.58|
00003a  69d0              LDR      r0,[r2,#0x1c]         ;772
00003c  e004              B        |L11.72|
                  |L11.62|
00003e  69d0              LDR      r0,[r2,#0x1c]         ;776
000040  4320              ORRS     r0,r0,r4              ;776
000042  e002              B        |L11.74|
                  |L11.68|
;;;779    	{
;;;780    		gGPIO_EXT0_Base->IER |= ((1 << gGPIO_EXT0_Pin) | (1 << (gGPIO_EXT0_Pin + 16)));
000044  480b              LDR      r0,|L11.116|
000046  69d5              LDR      r5,[r2,#0x1c]
                  |L11.72|
000048  4328              ORRS     r0,r0,r5              ;772
                  |L11.74|
00004a  61d0              STR      r0,[r2,#0x1c]
                  |L11.76|
;;;781    	}
;;;782    
;;;783    	/* Configure to be level trigger or edge trigger */
;;;784    	if (Mode == E_MODE_EDGE)
00004c  2900              CMP      r1,#0
00004e  d002              BEQ      |L11.86|
;;;785    		gGPIO_EXT0_Base->IMD &= ~(1<<gGPIO_EXT0_Pin);
;;;786    	else if(Mode == E_MODE_LEVEL)
000050  2901              CMP      r1,#1
000052  d003              BEQ      |L11.92|
000054  e005              B        |L11.98|
                  |L11.86|
000056  6990              LDR      r0,[r2,#0x18]         ;785
000058  43a0              BICS     r0,r0,r4              ;785
00005a  e001              B        |L11.96|
                  |L11.92|
;;;787    		gGPIO_EXT0_Base->IMD |= (1<<gGPIO_EXT0_Pin);
00005c  6990              LDR      r0,[r2,#0x18]
00005e  4320              ORRS     r0,r0,r4
                  |L11.96|
000060  6190              STR      r0,[r2,#0x18]
                  |L11.98|
;;;788    
;;;789    	gIsEXT0_Config = 1;
;;;790    	NVIC_EnableIRQ(EINT0_IRQn);
000062  2002              MOVS     r0,#2
000064  601e              STR      r6,[r3,#0]  ; gIsEXT0_Config
000066  f7fffffe          BL       NVIC_EnableIRQ
;;;791    }
00006a  bd70              POP      {r4-r6,pc}
;;;792    
                          ENDP

                  |L11.108|
                          DCD      ||.data||
                  |L11.112|
                          DCD      0x50004040
                  |L11.116|
                          DCD      0x40004000

                          AREA ||i.DrvGPIO_EnableEINT0_Ex||, CODE, READONLY, ALIGN=2

                  DrvGPIO_EnableEINT0_Ex PROC
;;;818    /*---------------------------------------------------------------------------------------------------------*/
;;;819    void DrvGPIO_EnableEINT0_Ex(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode,
000000  b5ff              PUSH     {r0-r7,lr}
;;;820    							GPIO_EINT0_CALLBACK pfEINT0Callback, E_DRVGPIO_EINT0 Ext0)
;;;821    {
000002  4604              MOV      r4,r0
;;;822    	assert_param(CHECK_GPIO_INTTYPE(TriggerType, Mode));
;;;823    
;;;824    	if (gIsEXT0_Config)
000004  4850              LDR      r0,|L12.328|
;;;825    	{
;;;826    		if (Ext0 < gPreGPIO_EXT0)   /* new INT priority higher */
;;;827    		{
;;;828    			printf("EXT0 interrupt is higher than before !\n");
;;;829    			GCR->PB_H_MFP_BITS.PB8 = 0;
000006  2505              MOVS     r5,#5
000008  6800              LDR      r0,[r0,#0]            ;824  ; gIsEXT0_Config
00000a  072d              LSLS     r5,r5,#28
;;;830    			GCR->PB_H_MFP_BITS.PB9 = 0;
;;;831    			GCR->PB_H_MFP_BITS.PB14 = 0;
;;;832    			GCR->PC_H_MFP_BITS.PC12 = 0;
00000c  4e4f              LDR      r6,|L12.332|
00000e  b081              SUB      sp,sp,#4              ;821
000010  461f              MOV      r7,r3                 ;821
000012  2800              CMP      r0,#0                 ;824
000014  d01b              BEQ      |L12.78|
000016  484c              LDR      r0,|L12.328|
000018  6a80              LDR      r0,[r0,#0x28]         ;826  ; gPreGPIO_EXT0
00001a  4287              CMP      r7,r0                 ;826
00001c  d223              BCS      |L12.102|
00001e  a04c              ADR      r0,|L12.336|
000020  f7fffffe          BL       __2printf
000024  6be8              LDR      r0,[r5,#0x3c]         ;829
000026  08c0              LSRS     r0,r0,#3              ;829
000028  00c0              LSLS     r0,r0,#3              ;829
00002a  63e8              STR      r0,[r5,#0x3c]         ;829
00002c  6be9              LDR      r1,[r5,#0x3c]         ;830
00002e  2070              MOVS     r0,#0x70              ;830
000030  4381              BICS     r1,r1,r0              ;830
000032  63e9              STR      r1,[r5,#0x3c]         ;830
000034  6be9              LDR      r1,[r5,#0x3c]         ;831
000036  0500              LSLS     r0,r0,#20             ;831
000038  4381              BICS     r1,r1,r0              ;831
00003a  63e9              STR      r1,[r5,#0x3c]         ;831
00003c  6870              LDR      r0,[r6,#4]
00003e  2107              MOVS     r1,#7
000040  0409              LSLS     r1,r1,#16
000042  4388              BICS     r0,r0,r1
000044  6070              STR      r0,[r6,#4]
;;;833    			GCR->PF_L_MFP_BITS.PF0 = 0;
000046  69b0              LDR      r0,[r6,#0x18]
000048  08c0              LSRS     r0,r0,#3
00004a  00c0              LSLS     r0,r0,#3
00004c  61b0              STR      r0,[r6,#0x18]
                  |L12.78|
;;;834    		}
;;;835    		else
;;;836    		{
;;;837    			printf("already set the EXT0 interrupt !!\n");
;;;838    			return;
;;;839    		}
;;;840    	}
;;;841       _pfEINT0Callback = pfEINT0Callback;
00004e  483e              LDR      r0,|L12.328|
000050  9903              LDR      r1,[sp,#0xc]
;;;842    
;;;843    	gPreGPIO_EXT0 = Ext0;
;;;844    	switch (Ext0)
;;;845    	{
;;;846    		case E_EXT0_GPB8:
;;;847    			GCR->PB_H_MFP_BITS.PB8 = 0x3;
;;;848    			gGPIO_EXT0_Base = GPIOB;
000052  6287              STR      r7,[r0,#0x28]  ; gPreGPIO_EXT0
000054  6101              STR      r1,[r0,#0x10]  ; _pfEINT0Callback
000056  4948              LDR      r1,|L12.376|
000058  003b              MOVS     r3,r7                 ;844
00005a  f7fffffe          BL       __ARM_common_switch8
00005e  0509              DCB      0x05,0x09
000060  11212c39          DCB      0x11,0x21,0x2c,0x39
000064  0700              DCB      0x07,0x00
                  |L12.102|
000066  a045              ADR      r0,|L12.380|
000068  f7fffffe          BL       __2printf
                  |L12.108|
;;;849    			gGPIO_EXT0_Pin = 8;
;;;850    			break;
;;;851    		case E_EXT0_GPB9:
;;;852    			GCR->PB_H_MFP_BITS.PB9 = 0x5;
;;;853    			gGPIO_EXT0_Base = GPIOB;
;;;854    			gGPIO_EXT0_Pin = 9;
;;;855    			break;
;;;856    		case E_EXT0_GPB14:
;;;857    			GCR->PB_H_MFP_BITS.PB14 = 0x1;
;;;858    			gGPIO_EXT0_Base = GPIOB;
;;;859    			gGPIO_EXT0_Pin = 14;
;;;860    			break;
;;;861    		case E_EXT0_GPC12:
;;;862    			GCR->PC_H_MFP_BITS.PC12 = 0x5;
;;;863    			gGPIO_EXT0_Base = GPIOC;
;;;864    			gGPIO_EXT0_Pin = 12;
;;;865    			break;
;;;866    		case E_EXT0_GPF0:
;;;867    			GCR->PF_L_MFP_BITS.PF0 = 0x5;
;;;868    			gGPIO_EXT0_Base = GPIOF;
;;;869    			gGPIO_EXT0_Pin = 0;
;;;870    			break;
;;;871    		default:
;;;872    			return;
;;;873    	}
;;;874    
;;;875    	if(TriggerType == E_IO_RISING)
;;;876    	{
;;;877    		gGPIO_EXT0_Base->IER |= (1 << (gGPIO_EXT0_Pin + 16));
;;;878    	}
;;;879    	else if(TriggerType == E_IO_FALLING)
;;;880    	{
;;;881    		gGPIO_EXT0_Base->IER |= (1 << gGPIO_EXT0_Pin);
;;;882    	}
;;;883    	else if(TriggerType == E_IO_BOTH_EDGE)
;;;884    	{
;;;885    		gGPIO_EXT0_Base->IER |= ((1 << gGPIO_EXT0_Pin) | (1 << (gGPIO_EXT0_Pin + 16)));
;;;886    	}
;;;887    
;;;888    	/* Configure to be level trigger or edge trigger */
;;;889    	if (Mode == E_MODE_EDGE)
;;;890    		gGPIO_EXT0_Base->IMD &= ~(1<<gGPIO_EXT0_Pin);
;;;891    	else if(Mode == E_MODE_LEVEL)
;;;892    		gGPIO_EXT0_Base->IMD |= (1<<gGPIO_EXT0_Pin);
;;;893    
;;;894    	gIsEXT0_Config = 1;
;;;895    	NVIC_EnableIRQ(EINT0_IRQn);
;;;896    }
00006c  b005              ADD      sp,sp,#0x14
00006e  bdf0              POP      {r4-r7,pc}
000070  6bea              LDR      r2,[r5,#0x3c]         ;847
000072  08d2              LSRS     r2,r2,#3              ;847
000074  00d2              LSLS     r2,r2,#3              ;847
000076  1cd2              ADDS     r2,r2,#3              ;847
000078  63ea              STR      r2,[r5,#0x3c]         ;847
00007a  6181              STR      r1,[r0,#0x18]         ;849  ; gGPIO_EXT0_Base
00007c  2108              MOVS     r1,#8                 ;849
00007e  e006              B        |L12.142|
000080  6bea              LDR      r2,[r5,#0x3c]         ;852
000082  2370              MOVS     r3,#0x70              ;852
000084  439a              BICS     r2,r2,r3              ;852
000086  3250              ADDS     r2,r2,#0x50           ;852
000088  63ea              STR      r2,[r5,#0x3c]         ;852
00008a  6181              STR      r1,[r0,#0x18]         ;854  ; gGPIO_EXT0_Base
00008c  2109              MOVS     r1,#9                 ;854
                  |L12.142|
00008e  6201              STR      r1,[r0,#0x20]         ;821  ; gGPIO_EXT0_Pin
000090  2101              MOVS     r1,#1                 ;821
000092  2c00              CMP      r4,#0                 ;875
000094  d025              BEQ      |L12.226|
000096  2c01              CMP      r4,#1                 ;879
000098  d02b              BEQ      |L12.242|
00009a  2c02              CMP      r4,#2                 ;883
00009c  d02f              BEQ      |L12.254|
00009e  e039              B        |L12.276|
0000a0  6bea              LDR      r2,[r5,#0x3c]         ;857
0000a2  2307              MOVS     r3,#7                 ;857
0000a4  061b              LSLS     r3,r3,#24             ;857
0000a6  439a              BICS     r2,r2,r3              ;857
0000a8  2301              MOVS     r3,#1                 ;857
0000aa  061b              LSLS     r3,r3,#24             ;857
0000ac  18d2              ADDS     r2,r2,r3              ;857
0000ae  63ea              STR      r2,[r5,#0x3c]         ;857
0000b0  6181              STR      r1,[r0,#0x18]         ;859  ; gGPIO_EXT0_Base
0000b2  210e              MOVS     r1,#0xe               ;859
0000b4  e7eb              B        |L12.142|
0000b6  6872              LDR      r2,[r6,#4]            ;862
0000b8  2107              MOVS     r1,#7                 ;862
0000ba  0409              LSLS     r1,r1,#16             ;862
0000bc  438a              BICS     r2,r2,r1              ;862
0000be  2105              MOVS     r1,#5                 ;862
0000c0  0409              LSLS     r1,r1,#16             ;862
0000c2  1851              ADDS     r1,r2,r1              ;862
0000c4  6071              STR      r1,[r6,#4]            ;862
0000c6  492c              LDR      r1,|L12.376|
0000c8  3140              ADDS     r1,r1,#0x40           ;863
0000ca  6181              STR      r1,[r0,#0x18]         ;864  ; gGPIO_EXT0_Base
0000cc  210c              MOVS     r1,#0xc               ;864
0000ce  e7de              B        |L12.142|
0000d0  69b1              LDR      r1,[r6,#0x18]         ;867
0000d2  08c9              LSRS     r1,r1,#3              ;867
0000d4  00c9              LSLS     r1,r1,#3              ;867
0000d6  1d49              ADDS     r1,r1,#5              ;867
0000d8  61b1              STR      r1,[r6,#0x18]         ;867
0000da  4931              LDR      r1,|L12.416|
0000dc  6181              STR      r1,[r0,#0x18]         ;869  ; gGPIO_EXT0_Base
0000de  2100              MOVS     r1,#0                 ;869
0000e0  e7d5              B        |L12.142|
                  |L12.226|
0000e2  6982              LDR      r2,[r0,#0x18]         ;877  ; gGPIO_EXT0_Base
0000e4  69d3              LDR      r3,[r2,#0x1c]         ;877
0000e6  6a04              LDR      r4,[r0,#0x20]         ;877  ; gGPIO_EXT0_Pin
0000e8  460d              MOV      r5,r1                 ;877
0000ea  3410              ADDS     r4,r4,#0x10           ;877
0000ec  40a5              LSLS     r5,r5,r4              ;877
0000ee  432b              ORRS     r3,r3,r5              ;877
0000f0  e00f              B        |L12.274|
                  |L12.242|
0000f2  6982              LDR      r2,[r0,#0x18]         ;881  ; gGPIO_EXT0_Base
0000f4  69d3              LDR      r3,[r2,#0x1c]         ;881
0000f6  6a05              LDR      r5,[r0,#0x20]         ;881  ; gGPIO_EXT0_Pin
0000f8  460c              MOV      r4,r1                 ;881
0000fa  40ac              LSLS     r4,r4,r5              ;881
0000fc  e008              B        |L12.272|
                  |L12.254|
0000fe  6a02              LDR      r2,[r0,#0x20]         ;885  ; gGPIO_EXT0_Pin
000100  460b              MOV      r3,r1                 ;885
000102  4093              LSLS     r3,r3,r2              ;885
000104  3210              ADDS     r2,r2,#0x10           ;885
000106  460c              MOV      r4,r1                 ;885
000108  4094              LSLS     r4,r4,r2              ;885
00010a  6982              LDR      r2,[r0,#0x18]         ;885  ; gGPIO_EXT0_Base
00010c  4323              ORRS     r3,r3,r4              ;885
00010e  69d4              LDR      r4,[r2,#0x1c]         ;885
                  |L12.272|
000110  4323              ORRS     r3,r3,r4              ;885
                  |L12.274|
000112  61d3              STR      r3,[r2,#0x1c]         ;885
                  |L12.276|
000114  9a02              LDR      r2,[sp,#8]            ;889
000116  2a00              CMP      r2,#0                 ;889
000118  d002              BEQ      |L12.288|
00011a  2a01              CMP      r2,#1                 ;891
00011c  d007              BEQ      |L12.302|
00011e  e00d              B        |L12.316|
                  |L12.288|
000120  6982              LDR      r2,[r0,#0x18]         ;890  ; gGPIO_EXT0_Base
000122  6993              LDR      r3,[r2,#0x18]         ;890
000124  6a05              LDR      r5,[r0,#0x20]         ;890  ; gGPIO_EXT0_Pin
000126  460c              MOV      r4,r1                 ;890
000128  40ac              LSLS     r4,r4,r5              ;890
00012a  43a3              BICS     r3,r3,r4              ;890
00012c  e005              B        |L12.314|
                  |L12.302|
00012e  6982              LDR      r2,[r0,#0x18]         ;892  ; gGPIO_EXT0_Base
000130  6993              LDR      r3,[r2,#0x18]         ;892
000132  6a05              LDR      r5,[r0,#0x20]         ;892  ; gGPIO_EXT0_Pin
000134  460c              MOV      r4,r1                 ;892
000136  40ac              LSLS     r4,r4,r5              ;892
000138  4323              ORRS     r3,r3,r4              ;892
                  |L12.314|
00013a  6193              STR      r3,[r2,#0x18]         ;892
                  |L12.316|
00013c  6001              STR      r1,[r0,#0]            ;895  ; gIsEXT0_Config
00013e  2002              MOVS     r0,#2                 ;895
000140  f7fffffe          BL       NVIC_EnableIRQ
000144  e792              B        |L12.108|
;;;897    
                          ENDP

000146  0000              DCW      0x0000
                  |L12.328|
                          DCD      ||.data||
                  |L12.332|
                          DCD      0x50000040
                  |L12.336|
000150  45585430          DCB      "EXT0 interrupt is higher than before !\n",0
000154  20696e74
000158  65727275
00015c  70742069
000160  73206869
000164  67686572
000168  20746861
00016c  6e206265
000170  666f7265
000174  20210a00
                  |L12.376|
                          DCD      0x50004040
                  |L12.380|
00017c  616c7265          DCB      "already set the EXT0 interrupt !!\n",0
000180  61647920
000184  73657420
000188  74686520
00018c  45585430
000190  20696e74
000194  65727275
000198  70742021
00019c  210a00  
00019f  00                DCB      0
                  |L12.416|
                          DCD      0x50004140

                          AREA ||i.DrvGPIO_EnableEINT1||, CODE, READONLY, ALIGN=2

                  DrvGPIO_EnableEINT1 PROC
;;;944    /*---------------------------------------------------------------------------------------------------------*/
;;;945    void DrvGPIO_EnableEINT1(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode, GPIO_EINT1_CALLBACK pfEINT1Callback)
000000  b570              PUSH     {r4-r6,lr}
;;;946    {
;;;947    	assert_param(CHECK_GPIO_INTTYPE(TriggerType, Mode));
;;;948    
;;;949    	_pfEINT1Callback = pfEINT1Callback;
000002  4b1a              LDR      r3,|L13.108|
;;;950    
;;;951    	gPreGPIO_EXT1 = E_EXT1_GPB15;
000004  615a              STR      r2,[r3,#0x14]  ; _pfEINT1Callback
000006  2200              MOVS     r2,#0
;;;952    	GCR->PB_H_MFP_BITS.PB15 = 0x1;
000008  62da              STR      r2,[r3,#0x2c]  ; gPreGPIO_EXT1
00000a  2205              MOVS     r2,#5
00000c  0712              LSLS     r2,r2,#28
00000e  6bd4              LDR      r4,[r2,#0x3c]
000010  2507              MOVS     r5,#7
000012  072d              LSLS     r5,r5,#28
000014  43ac              BICS     r4,r4,r5
000016  2501              MOVS     r5,#1
000018  072d              LSLS     r5,r5,#28
00001a  1964              ADDS     r4,r4,r5
00001c  63d4              STR      r4,[r2,#0x3c]
;;;953    	gGPIO_EXT1_Base = GPIOB;
00001e  4a14              LDR      r2,|L13.112|
;;;954    	gGPIO_EXT1_Pin = 15;
000020  240f              MOVS     r4,#0xf
;;;955    
;;;956    	if (TriggerType == E_IO_RISING)
;;;957    	{
;;;958    		gGPIO_EXT1_Base->IER |= (1 << (gGPIO_EXT1_Pin + 16));
;;;959    	}
;;;960    	else if (TriggerType == E_IO_FALLING)
;;;961    	{
;;;962    		gGPIO_EXT1_Base->IER |= (1 << gGPIO_EXT1_Pin);
000022  625c              STR      r4,[r3,#0x24]  ; gGPIO_EXT1_Pin
000024  0655              LSLS     r5,r2,#25             ;958
000026  0c2c              LSRS     r4,r5,#16
000028  2601              MOVS     r6,#1                 ;958
00002a  61da              STR      r2,[r3,#0x1c]  ; gGPIO_EXT1_Base
00002c  2800              CMP      r0,#0                 ;956
00002e  d004              BEQ      |L13.58|
000030  2801              CMP      r0,#1                 ;960
000032  d004              BEQ      |L13.62|
;;;963    	}
;;;964    	else if (TriggerType == E_IO_BOTH_EDGE)
000034  2802              CMP      r0,#2
000036  d005              BEQ      |L13.68|
000038  e008              B        |L13.76|
                  |L13.58|
00003a  69d0              LDR      r0,[r2,#0x1c]         ;958
00003c  e004              B        |L13.72|
                  |L13.62|
00003e  69d0              LDR      r0,[r2,#0x1c]         ;962
000040  4320              ORRS     r0,r0,r4              ;962
000042  e002              B        |L13.74|
                  |L13.68|
;;;965    	{
;;;966    		gGPIO_EXT1_Base->IER |= ((1 << gGPIO_EXT1_Pin) | (1 << (gGPIO_EXT1_Pin + 16)));
000044  480b              LDR      r0,|L13.116|
000046  69d5              LDR      r5,[r2,#0x1c]
                  |L13.72|
000048  4328              ORRS     r0,r0,r5              ;958
                  |L13.74|
00004a  61d0              STR      r0,[r2,#0x1c]
                  |L13.76|
;;;967    	}
;;;968    
;;;969    	 /* Configure to be level trigger or edge trigger */
;;;970    	if (Mode == E_MODE_EDGE)
00004c  2900              CMP      r1,#0
00004e  d002              BEQ      |L13.86|
;;;971    		gGPIO_EXT1_Base->IMD &= ~(1 << gGPIO_EXT1_Pin);
;;;972    	else if(Mode == E_MODE_LEVEL)
000050  2901              CMP      r1,#1
000052  d003              BEQ      |L13.92|
000054  e005              B        |L13.98|
                  |L13.86|
000056  6990              LDR      r0,[r2,#0x18]         ;971
000058  43a0              BICS     r0,r0,r4              ;971
00005a  e001              B        |L13.96|
                  |L13.92|
;;;973    		gGPIO_EXT1_Base->IMD |= (1 << gGPIO_EXT1_Pin);
00005c  6990              LDR      r0,[r2,#0x18]
00005e  4320              ORRS     r0,r0,r4
                  |L13.96|
000060  6190              STR      r0,[r2,#0x18]
                  |L13.98|
;;;974    
;;;975    	gIsEXT1_Config = 1;
;;;976    	NVIC_EnableIRQ(EINT1_IRQn);
000062  2003              MOVS     r0,#3
000064  605e              STR      r6,[r3,#4]  ; gIsEXT1_Config
000066  f7fffffe          BL       NVIC_EnableIRQ
;;;977    }
00006a  bd70              POP      {r4-r6,pc}
;;;978    
                          ENDP

                  |L13.108|
                          DCD      ||.data||
                  |L13.112|
                          DCD      0x50004040
                  |L13.116|
                          DCD      0x80008000

                          AREA ||i.DrvGPIO_EnableEINT1_Ex||, CODE, READONLY, ALIGN=2

                  DrvGPIO_EnableEINT1_Ex PROC
;;;1004   /*---------------------------------------------------------------------------------------------------------*/
;;;1005   void DrvGPIO_EnableEINT1_Ex(E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode,
000000  b5ff              PUSH     {r0-r7,lr}
;;;1006   							GPIO_EINT1_CALLBACK pfEINT1Callback, E_DRVGPIO_EINT1 Ext1)
;;;1007   {
;;;1008   	assert_param(CHECK_GPIO_INTTYPE(TriggerType, Mode));
;;;1009   
;;;1010   	if (gIsEXT1_Config)
000002  4c44              LDR      r4,|L14.276|
000004  4606              MOV      r6,r0                 ;1007
000006  6860              LDR      r0,[r4,#4]  ; gIsEXT1_Config
;;;1011   	{
;;;1012   		if (Ext1 < gPreGPIO_EXT1)   /* new INT priority higher */
;;;1013   		{
;;;1014   			printf("EXT1 interrupt is higher than before !\n");
;;;1015   			GCR->PB_H_MFP_BITS.PB15 = 0;
;;;1016   			GCR->PC_H_MFP_BITS.PC13 = 0;
000008  4f43              LDR      r7,|L14.280|
00000a  b081              SUB      sp,sp,#4              ;1007
00000c  461d              MOV      r5,r3                 ;1007
00000e  2800              CMP      r0,#0                 ;1010
000010  d014              BEQ      |L14.60|
000012  6ae0              LDR      r0,[r4,#0x2c]         ;1012  ; gPreGPIO_EXT1
000014  4285              CMP      r5,r0                 ;1012
000016  d22a              BCS      |L14.110|
000018  a040              ADR      r0,|L14.284|
00001a  f7fffffe          BL       __2printf
00001e  2005              MOVS     r0,#5                 ;1015
000020  0700              LSLS     r0,r0,#28             ;1015
000022  6bc1              LDR      r1,[r0,#0x3c]         ;1015
000024  2207              MOVS     r2,#7                 ;1015
000026  0712              LSLS     r2,r2,#28             ;1015
000028  4391              BICS     r1,r1,r2              ;1015
00002a  63c1              STR      r1,[r0,#0x3c]         ;1015
00002c  6878              LDR      r0,[r7,#4]
00002e  1211              ASRS     r1,r2,#8
000030  4388              BICS     r0,r0,r1
000032  6078              STR      r0,[r7,#4]
;;;1017   			GCR->PF_L_MFP_BITS.PF1 = 0;
000034  69b9              LDR      r1,[r7,#0x18]
000036  2070              MOVS     r0,#0x70
000038  4381              BICS     r1,r1,r0
00003a  61b9              STR      r1,[r7,#0x18]
                  |L14.60|
;;;1018   		}
;;;1019   		else
;;;1020   		{
;;;1021   			printf("already set the EXT0 interrupt !!\n");
;;;1022   			return;
;;;1023   		}
;;;1024   	}
;;;1025   	_pfEINT1Callback = pfEINT1Callback;
00003c  9803              LDR      r0,[sp,#0xc]
00003e  62e5              STR      r5,[r4,#0x2c]         ;1007  ; gPreGPIO_EXT1
000040  6160              STR      r0,[r4,#0x14]         ;1007  ; _pfEINT1Callback
000042  2001              MOVS     r0,#1                 ;1007
;;;1026   
;;;1027   	gPreGPIO_EXT1 = Ext1;
;;;1028   	switch (Ext1)
000044  2d00              CMP      r5,#0
000046  d017              BEQ      |L14.120|
000048  2d01              CMP      r5,#1
00004a  d023              BEQ      |L14.148|
00004c  2d02              CMP      r5,#2
00004e  d111              BNE      |L14.116|
;;;1029   	{
;;;1030   		case E_EXT1_GPB15:
;;;1031   			GCR->PB_H_MFP_BITS.PB15 = 0x1;
;;;1032   			gGPIO_EXT1_Base = GPIOB;
;;;1033   			gGPIO_EXT1_Pin = 15;
;;;1034   			break;
;;;1035   		case E_EXT1_GPC13:
;;;1036   			GCR->PC_H_MFP_BITS.PC13 = 0x5;
;;;1037   			gGPIO_EXT1_Base = GPIOC;
;;;1038   			gGPIO_EXT1_Pin = 13;
;;;1039   			break;
;;;1040   		case E_EXT0_GPF1:
;;;1041   			GCR->PF_L_MFP_BITS.PF1 = 0x5;
000050  69b9              LDR      r1,[r7,#0x18]
000052  2270              MOVS     r2,#0x70
000054  4391              BICS     r1,r1,r2
000056  3150              ADDS     r1,r1,#0x50
000058  61b9              STR      r1,[r7,#0x18]
;;;1042   			gGPIO_EXT1_Base = GPIOF;
00005a  493a              LDR      r1,|L14.324|
;;;1043   			gGPIO_EXT1_Pin = 1;
00005c  61e1              STR      r1,[r4,#0x1c]  ; gGPIO_EXT1_Base
00005e  6260              STR      r0,[r4,#0x24]  ; gGPIO_EXT1_Pin
                  |L14.96|
;;;1044   			break;
;;;1045   		default:
;;;1046   			return;
;;;1047   	}
;;;1048   
;;;1049   	if (TriggerType == E_IO_RISING)
000060  2e00              CMP      r6,#0
000062  d025              BEQ      |L14.176|
;;;1050   	{
;;;1051   		gGPIO_EXT1_Base->IER |= (1 << (gGPIO_EXT1_Pin + 16));
;;;1052   	}
;;;1053   	else if (TriggerType == E_IO_FALLING)
000064  2e01              CMP      r6,#1
000066  d02b              BEQ      |L14.192|
;;;1054   	{
;;;1055   		gGPIO_EXT1_Base->IER |= (1 << gGPIO_EXT1_Pin);
;;;1056   	}
;;;1057   	else if (TriggerType == E_IO_BOTH_EDGE)
000068  2e02              CMP      r6,#2
00006a  d02f              BEQ      |L14.204|
00006c  e039              B        |L14.226|
                  |L14.110|
00006e  a036              ADR      r0,|L14.328|
000070  f7fffffe          BL       __2printf
                  |L14.116|
;;;1058   	{
;;;1059   		gGPIO_EXT1_Base->IER |= ((1 << gGPIO_EXT1_Pin) | (1 << (gGPIO_EXT1_Pin + 16)));
;;;1060   	}
;;;1061   
;;;1062   	 /* Configure to be level trigger or edge trigger */
;;;1063   	if (Mode == E_MODE_EDGE)
;;;1064   		gGPIO_EXT1_Base->IMD &= ~(1 << gGPIO_EXT1_Pin);
;;;1065   	else if(Mode == E_MODE_LEVEL)
;;;1066   		gGPIO_EXT1_Base->IMD |= (1 << gGPIO_EXT1_Pin);
;;;1067   
;;;1068   	gIsEXT1_Config = 1;
;;;1069   	NVIC_EnableIRQ(EINT1_IRQn);
;;;1070   }
000074  b005              ADD      sp,sp,#0x14
000076  bdf0              POP      {r4-r7,pc}
                  |L14.120|
000078  2105              MOVS     r1,#5                 ;1031
00007a  0709              LSLS     r1,r1,#28             ;1031
00007c  6bca              LDR      r2,[r1,#0x3c]         ;1031
00007e  2307              MOVS     r3,#7                 ;1031
000080  071b              LSLS     r3,r3,#28             ;1031
000082  439a              BICS     r2,r2,r3              ;1031
000084  2301              MOVS     r3,#1                 ;1031
000086  071b              LSLS     r3,r3,#28             ;1031
000088  18d2              ADDS     r2,r2,r3              ;1031
00008a  63ca              STR      r2,[r1,#0x3c]         ;1031
00008c  4937              LDR      r1,|L14.364|
00008e  61e1              STR      r1,[r4,#0x1c]         ;1033  ; gGPIO_EXT1_Base
000090  210f              MOVS     r1,#0xf               ;1033
000092  e00b              B        |L14.172|
                  |L14.148|
000094  6879              LDR      r1,[r7,#4]            ;1036
000096  2207              MOVS     r2,#7                 ;1036
000098  0512              LSLS     r2,r2,#20             ;1036
00009a  4391              BICS     r1,r1,r2              ;1036
00009c  2205              MOVS     r2,#5                 ;1036
00009e  0512              LSLS     r2,r2,#20             ;1036
0000a0  1889              ADDS     r1,r1,r2              ;1036
0000a2  6079              STR      r1,[r7,#4]            ;1036
0000a4  4931              LDR      r1,|L14.364|
0000a6  3140              ADDS     r1,r1,#0x40           ;1037
0000a8  61e1              STR      r1,[r4,#0x1c]         ;1038  ; gGPIO_EXT1_Base
0000aa  210d              MOVS     r1,#0xd               ;1038
                  |L14.172|
0000ac  6261              STR      r1,[r4,#0x24]         ;1033  ; gGPIO_EXT1_Pin
0000ae  e7d7              B        |L14.96|
                  |L14.176|
0000b0  69e1              LDR      r1,[r4,#0x1c]         ;1051  ; gGPIO_EXT1_Base
0000b2  69ca              LDR      r2,[r1,#0x1c]         ;1051
0000b4  6a63              LDR      r3,[r4,#0x24]         ;1051  ; gGPIO_EXT1_Pin
0000b6  4605              MOV      r5,r0                 ;1051
0000b8  3310              ADDS     r3,r3,#0x10           ;1051
0000ba  409d              LSLS     r5,r5,r3              ;1051
0000bc  432a              ORRS     r2,r2,r5              ;1051
0000be  e00f              B        |L14.224|
                  |L14.192|
0000c0  69e1              LDR      r1,[r4,#0x1c]         ;1055  ; gGPIO_EXT1_Base
0000c2  69ca              LDR      r2,[r1,#0x1c]         ;1055
0000c4  6a65              LDR      r5,[r4,#0x24]         ;1055  ; gGPIO_EXT1_Pin
0000c6  4603              MOV      r3,r0                 ;1055
0000c8  40ab              LSLS     r3,r3,r5              ;1055
0000ca  e008              B        |L14.222|
                  |L14.204|
0000cc  6a61              LDR      r1,[r4,#0x24]         ;1059  ; gGPIO_EXT1_Pin
0000ce  4602              MOV      r2,r0                 ;1059
0000d0  408a              LSLS     r2,r2,r1              ;1059
0000d2  3110              ADDS     r1,r1,#0x10           ;1059
0000d4  4603              MOV      r3,r0                 ;1059
0000d6  408b              LSLS     r3,r3,r1              ;1059
0000d8  69e1              LDR      r1,[r4,#0x1c]         ;1059  ; gGPIO_EXT1_Base
0000da  431a              ORRS     r2,r2,r3              ;1059
0000dc  69cb              LDR      r3,[r1,#0x1c]         ;1059
                  |L14.222|
0000de  431a              ORRS     r2,r2,r3              ;1059
                  |L14.224|
0000e0  61ca              STR      r2,[r1,#0x1c]         ;1059
                  |L14.226|
0000e2  9902              LDR      r1,[sp,#8]            ;1063
0000e4  2900              CMP      r1,#0                 ;1063
0000e6  d002              BEQ      |L14.238|
0000e8  2901              CMP      r1,#1                 ;1065
0000ea  d007              BEQ      |L14.252|
0000ec  e00d              B        |L14.266|
                  |L14.238|
0000ee  69e1              LDR      r1,[r4,#0x1c]         ;1064  ; gGPIO_EXT1_Base
0000f0  698a              LDR      r2,[r1,#0x18]         ;1064
0000f2  6a65              LDR      r5,[r4,#0x24]         ;1064  ; gGPIO_EXT1_Pin
0000f4  4603              MOV      r3,r0                 ;1064
0000f6  40ab              LSLS     r3,r3,r5              ;1064
0000f8  439a              BICS     r2,r2,r3              ;1064
0000fa  e005              B        |L14.264|
                  |L14.252|
0000fc  69e1              LDR      r1,[r4,#0x1c]         ;1066  ; gGPIO_EXT1_Base
0000fe  698a              LDR      r2,[r1,#0x18]         ;1066
000100  6a65              LDR      r5,[r4,#0x24]         ;1066  ; gGPIO_EXT1_Pin
000102  4603              MOV      r3,r0                 ;1066
000104  40ab              LSLS     r3,r3,r5              ;1066
000106  431a              ORRS     r2,r2,r3              ;1066
                  |L14.264|
000108  618a              STR      r2,[r1,#0x18]         ;1066
                  |L14.266|
00010a  6060              STR      r0,[r4,#4]            ;1069  ; gIsEXT1_Config
00010c  2003              MOVS     r0,#3                 ;1069
00010e  f7fffffe          BL       NVIC_EnableIRQ
000112  e7af              B        |L14.116|
;;;1071   
                          ENDP

                  |L14.276|
                          DCD      ||.data||
                  |L14.280|
                          DCD      0x50000040
                  |L14.284|
00011c  45585431          DCB      "EXT1 interrupt is higher than before !\n",0
000120  20696e74
000124  65727275
000128  70742069
00012c  73206869
000130  67686572
000134  20746861
000138  6e206265
00013c  666f7265
000140  20210a00
                  |L14.324|
                          DCD      0x50004140
                  |L14.328|
000148  616c7265          DCB      "already set the EXT0 interrupt !!\n",0
00014c  61647920
000150  73657420
000154  74686520
000158  45585430
00015c  20696e74
000160  65727275
000164  70742021
000168  210a00  
00016b  00                DCB      0
                  |L14.364|
                          DCD      0x50004040

                          AREA ||i.DrvGPIO_EnableInt||, CODE, READONLY, ALIGN=2

                  DrvGPIO_EnableInt PROC
;;;639    /*---------------------------------------------------------------------------------------------------------*/
;;;640    int32_t DrvGPIO_EnableInt(E_DRVGPIO_PORT port, int32_t i32Bit, E_DRVGPIO_INT_TYPE TriggerType, E_DRVGPIO_INT_MODE Mode)
000000  b5f8              PUSH     {r3-r7,lr}
;;;641    {
000002  4605              MOV      r5,r0
;;;642    	GPIO_TypeDef *base;
;;;643    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;644    	base = (GPIO_TypeDef *)get_port_base(port);
000004  4c1c              LDR      r4,|L15.120|
000006  0180              LSLS     r0,r0,#6
000008  1904              ADDS     r4,r0,r4
;;;645    
;;;646    	assert_param(CHECK_GPIO_INTTYPE(TriggerType, Mode));
;;;647    
;;;648    	/* Configure the interrupt to be rising/falling when edge trigger or high/low level when level trigger */
;;;649    	if (TriggerType == E_IO_RISING)
;;;650    		base->IER |= (1 << (i32Bit+16));
00000a  4608              MOV      r0,r1
00000c  2701              MOVS     r7,#1
00000e  3010              ADDS     r0,r0,#0x10
000010  463e              MOV      r6,r7
000012  4086              LSLS     r6,r6,r0
;;;651    	else if(TriggerType == E_IO_FALLING)
;;;652    		base->IER |= (1 << i32Bit);
;;;653    	else if(TriggerType == E_IO_BOTH_EDGE)
;;;654    		base->IER |= ((1<<i32Bit) | (1 << (i32Bit+16)));
;;;655    	else
;;;656    		return E_DRVGPIO_ARGUMENT;
000014  4819              LDR      r0,|L15.124|
000016  408f              LSLS     r7,r7,r1              ;652
000018  2a00              CMP      r2,#0                 ;649
00001a  d016              BEQ      |L15.74|
00001c  2a01              CMP      r2,#1                 ;651
00001e  d017              BEQ      |L15.80|
000020  2a02              CMP      r2,#2                 ;653
000022  d128              BNE      |L15.118|
000024  4639              MOV      r1,r7                 ;653
000026  69e2              LDR      r2,[r4,#0x1c]         ;654
000028  4331              ORRS     r1,r1,r6              ;654
00002a  4311              ORRS     r1,r1,r2              ;654
                  |L15.44|
00002c  61e1              STR      r1,[r4,#0x1c]         ;654
;;;657    
;;;658    	/* Configure to be level trigger or edge trigger */
;;;659    	if(Mode == E_MODE_EDGE)
00002e  2b00              CMP      r3,#0
000030  d011              BEQ      |L15.86|
;;;660    		base->IMD &= ~(1<<i32Bit);
;;;661    	else if(Mode ==E_MODE_LEVEL)
000032  2b01              CMP      r3,#1
000034  d11f              BNE      |L15.118|
;;;662    		base->IMD |= (1<<i32Bit);
000036  69a0              LDR      r0,[r4,#0x18]
000038  4338              ORRS     r0,r0,r7
                  |L15.58|
00003a  61a0              STR      r0,[r4,#0x18]
;;;663    	else
;;;664    		return E_DRVGPIO_ARGUMENT;
;;;665    
;;;666    	/* Enable the relative interrupt of M0 */
;;;667    	if ((port == E_GPA) || (port == E_GPB) || (port == E_GPC))
00003c  2d00              CMP      r5,#0
00003e  d00d              BEQ      |L15.92|
000040  2d01              CMP      r5,#1
000042  d00b              BEQ      |L15.92|
000044  2d02              CMP      r5,#2
000046  d009              BEQ      |L15.92|
000048  e00b              B        |L15.98|
                  |L15.74|
00004a  69e1              LDR      r1,[r4,#0x1c]         ;650
00004c  4331              ORRS     r1,r1,r6              ;650
00004e  e7ed              B        |L15.44|
                  |L15.80|
000050  69e1              LDR      r1,[r4,#0x1c]         ;652
000052  4339              ORRS     r1,r1,r7              ;652
000054  e7ea              B        |L15.44|
                  |L15.86|
000056  69a0              LDR      r0,[r4,#0x18]         ;660
000058  43b8              BICS     r0,r0,r7              ;660
00005a  e7ee              B        |L15.58|
                  |L15.92|
;;;668    	{
;;;669    		//NVIC_SetPriority(GPABC_IRQn, (1<<__NVIC_PRIO_BITS) - 2);
;;;670    		NVIC_EnableIRQ(GPABC_IRQn);
00005c  2004              MOVS     r0,#4
00005e  f7fffffe          BL       NVIC_EnableIRQ
                  |L15.98|
;;;671    	}
;;;672    
;;;673    	if ((port == E_GPD) || (port == E_GPE) || (port == E_GPF))
000062  2d03              CMP      r5,#3
000064  d003              BEQ      |L15.110|
000066  2d04              CMP      r5,#4
000068  d001              BEQ      |L15.110|
00006a  2d05              CMP      r5,#5
00006c  d102              BNE      |L15.116|
                  |L15.110|
;;;674    	{
;;;675    		//NVIC_SetPriority(GPDEF_IRQn, (1<<__NVIC_PRIO_BITS) - 2);
;;;676    		NVIC_EnableIRQ(GPDEF_IRQn);
00006e  2005              MOVS     r0,#5
000070  f7fffffe          BL       NVIC_EnableIRQ
                  |L15.116|
;;;677    	}
;;;678    
;;;679    	return E_SUCCESS;
000074  2000              MOVS     r0,#0
                  |L15.118|
;;;680    }
000076  bdf8              POP      {r3-r7,pc}
;;;681    
                          ENDP

                  |L15.120|
                          DCD      0x50004000
                  |L15.124|
                          DCD      0xffff8901

                          AREA ||i.DrvGPIO_EnablePullup||, CODE, READONLY, ALIGN=2

                  DrvGPIO_EnablePullup PROC
;;;481    /*---------------------------------------------------------------------------------------------------------*/
;;;482    int32_t DrvGPIO_EnablePullup(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a04              LDR      r2,|L16.20|
;;;483    {
;;;484    	GPIO_TypeDef *base;
;;;485    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;486    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;487    
;;;488    	base->PUEN |= (1<<i32Bit);
000006  6a42              LDR      r2,[r0,#0x24]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  431a              ORRS     r2,r2,r3
00000e  6242              STR      r2,[r0,#0x24]
;;;489    
;;;490    	return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;491    }
000012  4770              BX       lr
;;;492    
                          ENDP

                  |L16.20|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetBit||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetBit PROC
;;;200    /*---------------------------------------------------------------------------------------------------------*/
;;;201    int32_t DrvGPIO_GetBit(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a03              LDR      r2,|L17.16|
;;;202    {
;;;203    	GPIO_TypeDef *base;
;;;204    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;205    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;206    
;;;207    	return ((base->PIN>>i32Bit) & 0x1);
000006  6900              LDR      r0,[r0,#0x10]
000008  40c8              LSRS     r0,r0,r1
00000a  07c0              LSLS     r0,r0,#31
00000c  0fc0              LSRS     r0,r0,#31
;;;208    }
00000e  4770              BX       lr
;;;209    
                          ENDP

                  |L17.16|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetBitMask||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetBitMask PROC
;;;364    /*---------------------------------------------------------------------------------------------------------*/
;;;365    int32_t DrvGPIO_GetBitMask(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a03              LDR      r2,|L18.16|
;;;366    {
;;;367    	GPIO_TypeDef *base;
;;;368    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;369    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;370    
;;;371    	return ((base->DMASK>>i32Bit) & 0x1);
000006  68c0              LDR      r0,[r0,#0xc]
000008  40c8              LSRS     r0,r0,r1
00000a  07c0              LSLS     r0,r0,#31
00000c  0fc0              LSRS     r0,r0,#31
;;;372    }
00000e  4770              BX       lr
;;;373    
                          ENDP

                  |L18.16|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetDebounceSampleCycle||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetDebounceSampleCycle PROC
;;;605    /*---------------------------------------------------------------------------------------------------------*/
;;;606    int32_t DrvGPIO_GetDebounceSampleCycle(void)
000000  4802              LDR      r0,|L19.12|
;;;607    {
;;;608    	return GPIODBNCE->CON_BITS.DBCLKSEL;
000002  6800              LDR      r0,[r0,#0]
000004  0700              LSLS     r0,r0,#28
000006  0f00              LSRS     r0,r0,#28
;;;609    }
000008  4770              BX       lr
;;;610    
                          ENDP

00000a  0000              DCW      0x0000
                  |L19.12|
                          DCD      0x50004180

                          AREA ||i.DrvGPIO_GetDoutBit||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetDoutBit PROC
;;;292    /*---------------------------------------------------------------------------------------------------------*/
;;;293    int32_t DrvGPIO_GetDoutBit(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a03              LDR      r2,|L20.16|
;;;294    {
;;;295    	GPIO_TypeDef *base;
;;;296    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;297    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;298    
;;;299    	return ((base->DOUT>>i32Bit) & 0x1);
000006  6880              LDR      r0,[r0,#8]
000008  40c8              LSRS     r0,r0,r1
00000a  07c0              LSLS     r0,r0,#31
00000c  0fc0              LSRS     r0,r0,#31
;;;300    }
00000e  4770              BX       lr
;;;301    
                          ENDP

                  |L20.16|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetIntStatus||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetIntStatus PROC
;;;1105   /*---------------------------------------------------------------------------------------------------------*/
;;;1106   int32_t DrvGPIO_GetIntStatus(E_DRVGPIO_PORT port)
000000  4902              LDR      r1,|L21.12|
;;;1107   {
;;;1108   	GPIO_TypeDef *base;
;;;1109   	assert_param(CHECK_GPIO_PORT(port));
;;;1110   	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1840              ADDS     r0,r0,r1
;;;1111   
;;;1112   	return base->ISR;
000006  6a00              LDR      r0,[r0,#0x20]
;;;1113   }
000008  4770              BX       lr
;;;1114   
                          ENDP

00000a  0000              DCW      0x0000
                  |L21.12|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetPortBits||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetPortBits PROC
;;;268    /*---------------------------------------------------------------------------------------------------------*/
;;;269    int32_t DrvGPIO_GetPortBits(E_DRVGPIO_PORT port)
000000  4902              LDR      r1,|L22.12|
;;;270    {
;;;271    	GPIO_TypeDef *base;
;;;272    	assert_param(CHECK_GPIO_PORT(port));
;;;273    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1840              ADDS     r0,r0,r1
;;;274    
;;;275    	return base->PIN;
000006  6900              LDR      r0,[r0,#0x10]
;;;276    }
000008  4770              BX       lr
;;;277    
                          ENDP

00000a  0000              DCW      0x0000
                  |L22.12|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetPortDoutBits||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetPortDoutBits PROC
;;;314    /*---------------------------------------------------------------------------------------------------------*/
;;;315    int32_t DrvGPIO_GetPortDoutBits(E_DRVGPIO_PORT port)
000000  4902              LDR      r1,|L23.12|
;;;316    {
;;;317    	GPIO_TypeDef *base;
;;;318    	assert_param(CHECK_GPIO_PORT(port));
;;;319    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1840              ADDS     r0,r0,r1
;;;320    
;;;321    	return (base->DOUT);
000006  6880              LDR      r0,[r0,#8]
;;;322    }
000008  4770              BX       lr
;;;323    
                          ENDP

00000a  0000              DCW      0x0000
                  |L23.12|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetPortMask||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetPortMask PROC
;;;435    /*---------------------------------------------------------------------------------------------------------*/
;;;436    int32_t DrvGPIO_GetPortMask(E_DRVGPIO_PORT port)
000000  4902              LDR      r1,|L24.12|
;;;437    {
;;;438    	GPIO_TypeDef *base;
;;;439    	assert_param(CHECK_GPIO_PORT(port));
;;;440    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1840              ADDS     r0,r0,r1
;;;441    
;;;442    	return (base->DMASK);
000006  68c0              LDR      r0,[r0,#0xc]
;;;443    }
000008  4770              BX       lr
;;;444    
                          ENDP

00000a  0000              DCW      0x0000
                  |L24.12|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_GetVersion||, CODE, READONLY, ALIGN=2

                  DrvGPIO_GetVersion PROC
;;;2225   /*---------------------------------------------------------------------------------------------------------*/
;;;2226   int32_t DrvGPIO_GetVersion(void)
000000  4800              LDR      r0,|L25.4|
;;;2227   {
;;;2228      return DRVGPIO_VERSION_NUM;
;;;2229   }
000002  4770              BX       lr
;;;2230   
                          ENDP

                  |L25.4|
                          DCD      0x00010101

                          AREA ||i.DrvGPIO_InitDAC||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitDAC PROC
;;;2165   /*---------------------------------------------------------------------------------------------------------*/
;;;2166   int32_t DrvGPIO_InitDAC(E_DRVGPIO_DAC function)
000000  b570              PUSH     {r4-r6,lr}
;;;2167   {
;;;2168   	uint32_t offset, value, shift0, shift1, val0, val1;
;;;2169   
;;;2170   	offset = (function & 0xff000000) >> 24;
000002  0e04              LSRS     r4,r0,#24
;;;2171   	shift0 = (function & 0x00ff0000) >> 16;
000004  0c01              LSRS     r1,r0,#16
;;;2172   	shift1 = (function & 0x0000ff00) >> 8;
000006  0a02              LSRS     r2,r0,#8
;;;2173   	val0   = (function & 0xf) << shift0;
000008  0703              LSLS     r3,r0,#28
00000a  0f1b              LSRS     r3,r3,#28
00000c  408b              LSLS     r3,r3,r1
;;;2174   	val1   = ((function & 0xf0) >> 4) << shift1;
00000e  0600              LSLS     r0,r0,#24
000010  0f00              LSRS     r0,r0,#28
;;;2175   
;;;2176   	value = (inpw(GCR_BASE+offset) & ~(0xf<<shift0)) & ~(0xf<<shift1);
000012  260f              MOVS     r6,#0xf
000014  4090              LSLS     r0,r0,r2              ;2174
000016  4635              MOV      r5,r6
000018  4095              LSLS     r5,r5,r2
00001a  408e              LSLS     r6,r6,r1
;;;2177   	outpw(GCR_BASE+offset, value|val0|val1);
;;;2178   
;;;2179   	return E_SUCCESS;
;;;2180   }
00001c  4335              ORRS     r5,r5,r6
00001e  2105              MOVS     r1,#5                 ;2176
000020  43ea              MVNS     r2,r5
000022  0709              LSLS     r1,r1,#28             ;2176
000024  1861              ADDS     r1,r4,r1              ;2176
000026  680c              LDR      r4,[r1,#0]            ;2176
000028  4022              ANDS     r2,r2,r4              ;2176
00002a  431a              ORRS     r2,r2,r3              ;2177
00002c  4302              ORRS     r2,r2,r0              ;2177
00002e  600a              STR      r2,[r1,#0]            ;2177
000030  2000              MOVS     r0,#0                 ;2179
000032  bd70              POP      {r4-r6,pc}
;;;2181   
                          ENDP


                          AREA ||i.DrvGPIO_InitFunction||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitFunction PROC
;;;1141   /*---------------------------------------------------------------------------------------------------------*/
;;;1142   int32_t DrvGPIO_InitFunction(E_DRVGPIO_FUNC function)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1143   {
;;;1144   	uint32_t offset, value, shift0, shift1, val0, val1=0;
;;;1145   
;;;1146   	if ((function & 0xff000000) != 0x0f000000)
;;;1147   	{
;;;1148   		offset = (function & 0xff000000) >> 24;
;;;1149   		shift0 = (function & 0x00ff0000) >> 16;
;;;1150   		shift1 = (function & 0x0000ff00) >> 8;
;;;1151   		val0   = (function & 0xf) << shift0;
;;;1152   		if (shift1 != 0xff)
;;;1153   		{
;;;1154   			val1   = ((function & 0xf0) >> 4) << shift1;
;;;1155   			value = (inpw(GCR_BASE+offset) & ~(0xf<<shift0)) & ~(0xf<<shift1);
000002  2105              MOVS     r1,#5
000004  2300              MOVS     r3,#0                 ;1144
000006  0e02              LSRS     r2,r0,#24             ;1146
000008  0709              LSLS     r1,r1,#28
00000a  2a0f              CMP      r2,#0xf               ;1146
00000c  d01e              BEQ      |L27.76|
00000e  0401              LSLS     r1,r0,#16             ;1150
000010  0c02              LSRS     r2,r0,#16             ;1149
000012  0e09              LSRS     r1,r1,#24             ;1150
000014  0704              LSLS     r4,r0,#28             ;1151
000016  0f24              LSRS     r4,r4,#28             ;1151
000018  4094              LSLS     r4,r4,r2              ;1151
00001a  270f              MOVS     r7,#0xf
00001c  0c05              LSRS     r5,r0,#16             ;1149
00001e  463a              MOV      r2,r7                 ;1149
000020  40aa              LSLS     r2,r2,r5
000022  2605              MOVS     r6,#5
000024  0e05              LSRS     r5,r0,#24             ;1146
000026  0736              LSLS     r6,r6,#28
000028  19ad              ADDS     r5,r5,r6
00002a  29ff              CMP      r1,#0xff              ;1152
00002c  d008              BEQ      |L27.64|
00002e  0600              LSLS     r0,r0,#24             ;1154
000030  0f03              LSRS     r3,r0,#28             ;1154
000032  408b              LSLS     r3,r3,r1              ;1154
000034  408f              LSLS     r7,r7,r1
;;;1156   		}
;;;1157   		else
;;;1158   			value = inpw(GCR_BASE+offset) & ~(0xf<<shift0);
;;;1159   
;;;1160   		outpw(GCR_BASE+offset, value|val0|val1);
;;;1161   
;;;1162   		return E_SUCCESS;
;;;1163   	}
;;;1164   
;;;1165   	switch ( function )
;;;1166   	{
;;;1167   		/*---------------------------------------------------------------------------------------------------------*/
;;;1168   		/* GPIO                                                                                                    */
;;;1169   		/*---------------------------------------------------------------------------------------------------------*/
;;;1170   		case E_FUNC_GPIO:
;;;1171   		{
;;;1172   			GCR->PA_H_MFP = 0;
;;;1173   			GCR->PA_L_MFP = 0;
;;;1174   			GCR->PB_H_MFP = 0;
;;;1175   			GCR->PB_L_MFP = 0;
;;;1176   			GCR->PC_H_MFP = 0;
;;;1177   			GCR->PC_L_MFP = 0;
;;;1178   			GCR->PD_H_MFP = 0;
;;;1179   			GCR->PD_L_MFP = 0;
;;;1180   			GCR->PE_H_MFP = 0;
;;;1181   			GCR->PE_L_MFP = 0;
;;;1182   			GCR->PF_L_MFP = 0;
;;;1183   		}break;
;;;1184   
;;;1185   		/*---------------------------------------------------------------------------------------------------------*/
;;;1186   		/* I2S                                                                                                     */
;;;1187   		/*---------------------------------------------------------------------------------------------------------*/
;;;1188   		case E_FUNC_I2S:
;;;1189   		{
;;;1190   			GCR->PC_L_MFP = (GCR->PC_L_MFP & ~0xffff) | 0x2222;
;;;1191   			GCR->PA_H_MFP_BITS.PA15 = 0x2;  // I2S MCLK
;;;1192   		}break;
;;;1193   
;;;1194   
;;;1195   		/*---------------------------------------------------------------------------------------------------------*/
;;;1196   		/* SPI                                                                                                     */
;;;1197   		/*---------------------------------------------------------------------------------------------------------*/
;;;1198   		case E_FUNC_SPI0:
;;;1199   		{
;;;1200   			GCR->PC_L_MFP = (GCR->PC_L_MFP & ~0xffff) | 0x1111;
;;;1201   			GCR->PB_H_MFP_BITS.PB10 = 0x1;  // SPI0 SS1
;;;1202   		}break;
;;;1203   
;;;1204   		case E_FUNC_SPI1:
;;;1205   		{
;;;1206   			GCR->PC_H_MFP = (GCR->PC_H_MFP & ~0xffff) | 0x1111;
;;;1207   			GCR->PB_H_MFP_BITS.PB9 = 0x1;   // SPI1 SS1
;;;1208   		}break;
;;;1209   
;;;1210   		case E_FUNC_SPI2:
;;;1211   		{
;;;1212   			GCR->PD_L_MFP = (GCR->PD_L_MFP & ~0xffff) | 0x3333;
;;;1213   		}break;
;;;1214   
;;;1215   		/*---------------------------------------------------------------------------------------------------------*/
;;;1216   		/* UART                                                                                                    */
;;;1217   		/*--------------------------------------------------------------------------------------------------------*/
;;;1218   		case E_FUNC_UART0:
;;;1219   		{
;;;1220   			GCR->PB_L_MFP = (GCR->PB_L_MFP & ~0xffff) | 0x1111;
;;;1221   		}break;
;;;1222   
;;;1223   		case E_FUNC_UART1:
;;;1224   		{
;;;1225   			GCR->PB_L_MFP = (GCR->PB_L_MFP & ~0xffff0000) | 0x11110000;
;;;1226   		}break;
;;;1227   
;;;1228   		/*---------------------------------------------------------------------------------------------------------*/
;;;1229   		/* PWM                                                                                                     */
;;;1230   		/*---------------------------------------------------------------------------------------------------------*/
;;;1231   		case E_FUNC_PWM45:  // PWM1 channel 0/1
;;;1232   		{
;;;1233   			GCR->PB_H_MFP_BITS.PB11 = 0x1;
;;;1234   			GCR->PE_L_MFP_BITS.PE5 = 0x1;
;;;1235   		}break;
;;;1236   
;;;1237   		/*---------------------------------------------------------------------------------------------------------*/
;;;1238   		/* EBI                                                                                                     */
;;;1239   		/*---------------------------------------------------------------------------------------------------------*/
;;;1240   		case E_FUNC_EBI_16B:
;;;1241   		{
;;;1242   			// Enable nWRH & nWRL for support Byte-Write in 16bit Data Width Device(SARM)
;;;1243   			GCR->PB_L_MFP = (GCR->PB_L_MFP & ~0xff00) | 0x2200;
;;;1244   
;;;1245   			// Enable EBI AD High-byte, bit 15~8
;;;1246   			GCR->PA_L_MFP = (GCR->PA_L_MFP & ~0xfffff0) | 0x222220;
;;;1247   			GCR->PA_H_MFP = (GCR->PA_H_MFP & ~0xfff0000) | 0x2220000;
;;;1248   		}
;;;1249   
;;;1250   		case E_FUNC_EBI_8B:
;;;1251   		{
;;;1252   			// Enable EBI_EN and EBI_MCLK_EN
;;;1253   			GCR->PC_H_MFP_BITS.PC8 = 0x2;
;;;1254   
;;;1255   			// Enable nRD/nWR/ALE/nCS for EBI
;;;1256   			GCR->PA_H_MFP = (GCR->PA_H_MFP & ~0xff00) | 0x2200;
;;;1257   			GCR->PB_L_MFP = (GCR->PB_L_MFP & ~0xff000000) | 0x22000000;
;;;1258   
;;;1259   			// Enable EBI AD Low-byte, bit 7~0
;;;1260   			GCR->PA_L_MFP = (GCR->PA_L_MFP & ~0xff000000) | 0x22000000;
;;;1261   			GCR->PB_H_MFP = (GCR->PB_H_MFP & ~0xff0000) | 0x220000;
;;;1262   			GCR->PC_H_MFP = (GCR->PC_H_MFP & ~0xff000000) | 0x22000000;
;;;1263   			GCR->PC_L_MFP = (GCR->PC_L_MFP & ~0xff000000) | 0x22000000;
;;;1264   		}break;
;;;1265   
;;;1266   		default:
;;;1267   			return E_DRVGPIO_ARGUMENT;
;;;1268   	}
;;;1269   
;;;1270   	return E_SUCCESS;
;;;1271   }
000036  4317              ORRS     r7,r7,r2
000038  6829              LDR      r1,[r5,#0]            ;1155
00003a  43f8              MVNS     r0,r7
00003c  4008              ANDS     r0,r0,r1              ;1155
00003e  e001              B        |L27.68|
                  |L27.64|
000040  6828              LDR      r0,[r5,#0]            ;1158
000042  4390              BICS     r0,r0,r2              ;1158
                  |L27.68|
000044  4320              ORRS     r0,r0,r4              ;1160
000046  4318              ORRS     r0,r0,r3              ;1160
000048  6028              STR      r0,[r5,#0]            ;1160
00004a  e09b              B        |L27.388|
                  |L27.76|
00004c  22f1              MOVS     r2,#0xf1              ;1165
00004e  0612              LSLS     r2,r2,#24             ;1165
000050  1886              ADDS     r6,r0,r2              ;1165
000052  20ff              MOVS     r0,#0xff              ;1243
000054  2411              MOVS     r4,#0x11              ;1243
000056  4a4d              LDR      r2,|L27.396|
000058  4d4d              LDR      r5,|L27.400|
00005a  0200              LSLS     r0,r0,#8              ;1243
00005c  0264              LSLS     r4,r4,#9              ;1243
00005e  0033              MOVS     r3,r6                 ;1165
000060  f7fffffe          BL       __ARM_common_switch8
000064  0a061321          DCB      0x0a,0x06,0x13,0x21
000068  2d383f44          DCB      0x2d,0x38,0x3f,0x44
00006c  4a6a5a92          DCB      0x4a,0x6a,0x5a,0x92
000070  2000              MOVS     r0,#0                 ;1172
000072  6348              STR      r0,[r1,#0x34]         ;1172
000074  6308              STR      r0,[r1,#0x30]         ;1173
000076  63c8              STR      r0,[r1,#0x3c]         ;1174
000078  6388              STR      r0,[r1,#0x38]         ;1175
00007a  6050              STR      r0,[r2,#4]            ;1176
00007c  6010              STR      r0,[r2,#0]            ;1177
00007e  60d0              STR      r0,[r2,#0xc]          ;1178
000080  6090              STR      r0,[r2,#8]            ;1179
000082  6150              STR      r0,[r2,#0x14]         ;1180
000084  6110              STR      r0,[r2,#0x10]         ;1181
000086  6190              STR      r0,[r2,#0x18]         ;1182
000088  e07c              B        |L27.388|
00008a  6810              LDR      r0,[r2,#0]            ;1190
00008c  4b41              LDR      r3,|L27.404|
00008e  0c00              LSRS     r0,r0,#16             ;1190
000090  0400              LSLS     r0,r0,#16             ;1190
000092  18c0              ADDS     r0,r0,r3              ;1190
000094  6010              STR      r0,[r2,#0]            ;1190
000096  6b48              LDR      r0,[r1,#0x34]         ;1191
000098  2207              MOVS     r2,#7                 ;1191
00009a  0712              LSLS     r2,r2,#28             ;1191
00009c  4390              BICS     r0,r0,r2              ;1191
00009e  071a              LSLS     r2,r3,#28             ;1191
0000a0  1880              ADDS     r0,r0,r2              ;1191
0000a2  6348              STR      r0,[r1,#0x34]         ;1191
0000a4  e06e              B        |L27.388|
0000a6  6810              LDR      r0,[r2,#0]            ;1200
0000a8  0c00              LSRS     r0,r0,#16             ;1200
0000aa  0400              LSLS     r0,r0,#16             ;1200
0000ac  1940              ADDS     r0,r0,r5              ;1200
0000ae  6010              STR      r0,[r2,#0]            ;1200
0000b0  6bc8              LDR      r0,[r1,#0x3c]         ;1201
0000b2  2207              MOVS     r2,#7                 ;1201
0000b4  0212              LSLS     r2,r2,#8              ;1201
0000b6  4390              BICS     r0,r0,r2              ;1201
0000b8  30ff              ADDS     r0,r0,#0xff           ;1201
0000ba  3001              ADDS     r0,#1                 ;1201
0000bc  e008              B        |L27.208|
0000be  6850              LDR      r0,[r2,#4]            ;1206
0000c0  0c00              LSRS     r0,r0,#16             ;1206
0000c2  0400              LSLS     r0,r0,#16             ;1206
0000c4  1940              ADDS     r0,r0,r5              ;1206
0000c6  6050              STR      r0,[r2,#4]            ;1206
0000c8  6bc8              LDR      r0,[r1,#0x3c]         ;1207
0000ca  2270              MOVS     r2,#0x70              ;1207
0000cc  4390              BICS     r0,r0,r2              ;1207
0000ce  3010              ADDS     r0,r0,#0x10           ;1207
                  |L27.208|
0000d0  63c8              STR      r0,[r1,#0x3c]         ;1201
0000d2  e057              B        |L27.388|
0000d4  6890              LDR      r0,[r2,#8]            ;1212
0000d6  4930              LDR      r1,|L27.408|
0000d8  0c00              LSRS     r0,r0,#16             ;1212
0000da  0400              LSLS     r0,r0,#16             ;1212
0000dc  1840              ADDS     r0,r0,r1              ;1212
0000de  6090              STR      r0,[r2,#8]            ;1212
0000e0  e050              B        |L27.388|
0000e2  6b88              LDR      r0,[r1,#0x38]         ;1220
0000e4  0c00              LSRS     r0,r0,#16             ;1220
0000e6  0400              LSLS     r0,r0,#16             ;1220
0000e8  1940              ADDS     r0,r0,r5              ;1220
0000ea  e003              B        |L27.244|
0000ec  6b88              LDR      r0,[r1,#0x38]         ;1225
0000ee  4a2b              LDR      r2,|L27.412|
0000f0  b280              UXTH     r0,r0                 ;1225
0000f2  1880              ADDS     r0,r0,r2              ;1225
                  |L27.244|
0000f4  6388              STR      r0,[r1,#0x38]         ;1220
0000f6  e045              B        |L27.388|
0000f8  6bc8              LDR      r0,[r1,#0x3c]         ;1233
0000fa  2307              MOVS     r3,#7                 ;1233
0000fc  031b              LSLS     r3,r3,#12             ;1233
0000fe  4398              BICS     r0,r0,r3              ;1233
000100  2301              MOVS     r3,#1                 ;1233
000102  031b              LSLS     r3,r3,#12             ;1233
000104  18c0              ADDS     r0,r0,r3              ;1233
000106  63c8              STR      r0,[r1,#0x3c]         ;1233
000108  6910              LDR      r0,[r2,#0x10]         ;1234
00010a  2107              MOVS     r1,#7                 ;1234
00010c  0509              LSLS     r1,r1,#20             ;1234
00010e  4388              BICS     r0,r0,r1              ;1234
000110  0219              LSLS     r1,r3,#8              ;1234
000112  1840              ADDS     r0,r0,r1              ;1234
000114  6110              STR      r0,[r2,#0x10]         ;1234
000116  e035              B        |L27.388|
000118  6b8b              LDR      r3,[r1,#0x38]         ;1243
00011a  4383              BICS     r3,r3,r0              ;1243
00011c  191b              ADDS     r3,r3,r4              ;1243
00011e  638b              STR      r3,[r1,#0x38]         ;1243
000120  6b0b              LDR      r3,[r1,#0x30]         ;1246
000122  4d1f              LDR      r5,|L27.416|
000124  402b              ANDS     r3,r3,r5              ;1246
000126  4d1f              LDR      r5,|L27.420|
000128  195b              ADDS     r3,r3,r5              ;1246
00012a  630b              STR      r3,[r1,#0x30]         ;1246
00012c  6b4b              LDR      r3,[r1,#0x34]         ;1247
00012e  4d1e              LDR      r5,|L27.424|
000130  402b              ANDS     r3,r3,r5              ;1247
000132  4d1e              LDR      r5,|L27.428|
000134  195b              ADDS     r3,r3,r5              ;1247
000136  634b              STR      r3,[r1,#0x34]         ;1247
000138  6853              LDR      r3,[r2,#4]            ;1253
00013a  08db              LSRS     r3,r3,#3              ;1253
00013c  00db              LSLS     r3,r3,#3              ;1253
00013e  1c9b              ADDS     r3,r3,#2              ;1253
000140  6053              STR      r3,[r2,#4]            ;1253
000142  6b4b              LDR      r3,[r1,#0x34]         ;1256
000144  4383              BICS     r3,r3,r0              ;1256
000146  1918              ADDS     r0,r3,r4              ;1256
000148  6348              STR      r0,[r1,#0x34]         ;1256
00014a  6b88              LDR      r0,[r1,#0x38]         ;1257
00014c  0203              LSLS     r3,r0,#8              ;1257
00014e  2011              MOVS     r0,#0x11              ;1257
000150  0a1b              LSRS     r3,r3,#8              ;1257
000152  0640              LSLS     r0,r0,#25             ;1257
000154  181b              ADDS     r3,r3,r0              ;1257
000156  638b              STR      r3,[r1,#0x38]         ;1257
000158  6b0b              LDR      r3,[r1,#0x30]         ;1260
00015a  021b              LSLS     r3,r3,#8              ;1260
00015c  0a1b              LSRS     r3,r3,#8              ;1260
00015e  181b              ADDS     r3,r3,r0              ;1260
000160  630b              STR      r3,[r1,#0x30]         ;1260
000162  6bcb              LDR      r3,[r1,#0x3c]         ;1261
000164  24ff              MOVS     r4,#0xff              ;1261
000166  0424              LSLS     r4,r4,#16             ;1261
000168  43a3              BICS     r3,r3,r4              ;1261
00016a  1204              ASRS     r4,r0,#8              ;1261
00016c  191b              ADDS     r3,r3,r4              ;1261
00016e  63cb              STR      r3,[r1,#0x3c]         ;1261
000170  6851              LDR      r1,[r2,#4]            ;1262
000172  0209              LSLS     r1,r1,#8              ;1262
000174  0a09              LSRS     r1,r1,#8              ;1262
000176  1809              ADDS     r1,r1,r0              ;1262
000178  6051              STR      r1,[r2,#4]            ;1262
00017a  6811              LDR      r1,[r2,#0]            ;1263
00017c  0209              LSLS     r1,r1,#8              ;1263
00017e  0a09              LSRS     r1,r1,#8              ;1263
000180  1808              ADDS     r0,r1,r0              ;1263
000182  6010              STR      r0,[r2,#0]            ;1263
                  |L27.388|
000184  2000              MOVS     r0,#0                 ;1270
000186  bdf0              POP      {r4-r7,pc}
000188  4809              LDR      r0,|L27.432|
00018a  bdf0              POP      {r4-r7,pc}
;;;1272   
                          ENDP

                  |L27.396|
                          DCD      0x50000040
                  |L27.400|
                          DCD      0x00001111
                  |L27.404|
                          DCD      0x00002222
                  |L27.408|
                          DCD      0x00003333
                  |L27.412|
                          DCD      0x11110000
                  |L27.416|
                          DCD      0xff00000f
                  |L27.420|
                          DCD      0x00222220
                  |L27.424|
                          DCD      0xf000ffff
                  |L27.428|
                          DCD      0x02220000
                  |L27.432|
                          DCD      0xffff8901

                          AREA ||i.DrvGPIO_InitGPIO||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitGPIO PROC
;;;2196   /*---------------------------------------------------------------------------------------------------------*/
;;;2197   int32_t DrvGPIO_InitGPIO(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  b510              PUSH     {r4,lr}
;;;2198   {
;;;2199   	uint32_t reg;
;;;2200   
;;;2201   	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;2202   
;;;2203   	if (i32Bit < 8)
;;;2204   	{
;;;2205   		reg = inpw(GCR_BASE+0x30+(port*8));
000002  2405              MOVS     r4,#5
000004  0724              LSLS     r4,r4,#28
000006  00c0              LSLS     r0,r0,#3
;;;2206   		outpw(GCR_BASE+0x30+(port*8), reg & ~(0x7 << (4 * i32Bit)));
000008  008a              LSLS     r2,r1,#2
00000a  2307              MOVS     r3,#7
00000c  1900              ADDS     r0,r0,r4              ;2205
00000e  2908              CMP      r1,#8                 ;2203
000010  da04              BGE      |L28.28|
000012  6b01              LDR      r1,[r0,#0x30]         ;2205
000014  4093              LSLS     r3,r3,r2
000016  4399              BICS     r1,r1,r3
000018  6301              STR      r1,[r0,#0x30]
00001a  e004              B        |L28.38|
                  |L28.28|
;;;2207   	}
;;;2208   	else
;;;2209   	{
;;;2210   		reg = inpw(GCR_BASE+0x34+(port*8));
00001c  6b41              LDR      r1,[r0,#0x34]
;;;2211   		outpw(GCR_BASE+0x34+(port*8), reg & ~(0x7 << (4 * (i32Bit-8))));
00001e  3a20              SUBS     r2,r2,#0x20
000020  4093              LSLS     r3,r3,r2
000022  4399              BICS     r1,r1,r3
000024  6341              STR      r1,[r0,#0x34]
                  |L28.38|
;;;2212   	}
;;;2213   	return E_SUCCESS;
000026  2000              MOVS     r0,#0
;;;2214   }
000028  bd10              POP      {r4,pc}
;;;2215   
                          ENDP


                          AREA ||i.DrvGPIO_InitI2C0||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitI2C0 PROC
;;;1783   /*---------------------------------------------------------------------------------------------------------*/
;;;1784   int32_t DrvGPIO_InitI2C0(STR_GPIO_I2C0_T *I2CFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1785   {
;;;1786   	uint32_t offset, value, shift;
;;;1787   
;;;1788   	/* sda */
;;;1789   	offset = (I2CFun->i2c0SDA & 0xff000000) >> 24;
000002  6801              LDR      r1,[r0,#0]
;;;1790   	shift  = (I2CFun->i2c0SDA & 0x00ff0000) >> 16;
;;;1791   	value  = (I2CFun->i2c0SDA & 0xff) << shift;
;;;1792   
;;;1793   	if (value)
;;;1794   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000004  2305              MOVS     r3,#5
000006  0e0d              LSRS     r5,r1,#24             ;1789
000008  020a              LSLS     r2,r1,#8              ;1790
00000a  0e12              LSRS     r2,r2,#24             ;1790
00000c  b2c9              UXTB     r1,r1                 ;1791
00000e  4091              LSLS     r1,r1,r2              ;1791
000010  071b              LSLS     r3,r3,#28
000012  240f              MOVS     r4,#0xf
000014  2900              CMP      r1,#0                 ;1793
000016  d006              BEQ      |L29.38|
000018  18ed              ADDS     r5,r5,r3
00001a  682e              LDR      r6,[r5,#0]
00001c  4627              MOV      r7,r4
00001e  4097              LSLS     r7,r7,r2
000020  43be              BICS     r6,r6,r7
000022  430e              ORRS     r6,r6,r1
000024  602e              STR      r6,[r5,#0]
                  |L29.38|
;;;1795   
;;;1796   	/* sck */
;;;1797   	offset = (I2CFun->i2c0SCK & 0xff000000) >> 24;
000026  6840              LDR      r0,[r0,#4]
000028  0e02              LSRS     r2,r0,#24
;;;1798   	shift  = (I2CFun->i2c0SCK & 0x00ff0000) >> 16;
00002a  0201              LSLS     r1,r0,#8
00002c  0e09              LSRS     r1,r1,#24
;;;1799   	value  = (I2CFun->i2c0SCK & 0xff) << shift;
00002e  b2c0              UXTB     r0,r0
000030  4088              LSLS     r0,r0,r1
;;;1800   
;;;1801   	if (value)
000032  d005              BEQ      |L29.64|
;;;1802   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000034  18d2              ADDS     r2,r2,r3
000036  6813              LDR      r3,[r2,#0]
000038  408c              LSLS     r4,r4,r1
00003a  43a3              BICS     r3,r3,r4
00003c  4303              ORRS     r3,r3,r0
00003e  6013              STR      r3,[r2,#0]
                  |L29.64|
;;;1803   
;;;1804   	return E_SUCCESS;
000040  2000              MOVS     r0,#0
;;;1805   }
000042  bdf0              POP      {r4-r7,pc}
;;;1806   
                          ENDP


                          AREA ||i.DrvGPIO_InitI2C1||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitI2C1 PROC
;;;1821   /*---------------------------------------------------------------------------------------------------------*/
;;;1822   int32_t DrvGPIO_InitI2C1(STR_GPIO_I2C1_T *I2CFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1823   {
;;;1824   	uint32_t offset, value, shift;
;;;1825   
;;;1826   	/* sda */
;;;1827   	offset = (I2CFun->i2c1SDA & 0xff000000) >> 24;
000002  6801              LDR      r1,[r0,#0]
;;;1828   	shift  = (I2CFun->i2c1SDA & 0x00ff0000) >> 16;
;;;1829   	value  = (I2CFun->i2c1SDA & 0xff) << shift;
;;;1830   
;;;1831   	if (value)
;;;1832   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000004  2305              MOVS     r3,#5
000006  0e0d              LSRS     r5,r1,#24             ;1827
000008  020a              LSLS     r2,r1,#8              ;1828
00000a  0e12              LSRS     r2,r2,#24             ;1828
00000c  b2c9              UXTB     r1,r1                 ;1829
00000e  4091              LSLS     r1,r1,r2              ;1829
000010  071b              LSLS     r3,r3,#28
000012  240f              MOVS     r4,#0xf
000014  2900              CMP      r1,#0                 ;1831
000016  d006              BEQ      |L30.38|
000018  18ed              ADDS     r5,r5,r3
00001a  682e              LDR      r6,[r5,#0]
00001c  4627              MOV      r7,r4
00001e  4097              LSLS     r7,r7,r2
000020  43be              BICS     r6,r6,r7
000022  430e              ORRS     r6,r6,r1
000024  602e              STR      r6,[r5,#0]
                  |L30.38|
;;;1833   
;;;1834   	/* sck */
;;;1835   	offset = (I2CFun->i2c1SCK & 0xff000000) >> 24;
000026  6840              LDR      r0,[r0,#4]
000028  0e02              LSRS     r2,r0,#24
;;;1836   	shift  = (I2CFun->i2c1SCK & 0x00ff0000) >> 16;
00002a  0201              LSLS     r1,r0,#8
00002c  0e09              LSRS     r1,r1,#24
;;;1837   	value  = (I2CFun->i2c1SCK & 0xff) << shift;
00002e  b2c0              UXTB     r0,r0
000030  4088              LSLS     r0,r0,r1
;;;1838   
;;;1839   	if (value)
000032  d005              BEQ      |L30.64|
;;;1840   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000034  18d2              ADDS     r2,r2,r3
000036  6813              LDR      r3,[r2,#0]
000038  408c              LSLS     r4,r4,r1
00003a  43a3              BICS     r3,r3,r4
00003c  4303              ORRS     r3,r3,r0
00003e  6013              STR      r3,[r2,#0]
                  |L30.64|
;;;1841   
;;;1842   	return E_SUCCESS;
000040  2000              MOVS     r0,#0
;;;1843   }
000042  bdf0              POP      {r4-r7,pc}
;;;1844   
                          ENDP


                          AREA ||i.DrvGPIO_InitI2S||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitI2S PROC
;;;1729   /*---------------------------------------------------------------------------------------------------------*/
;;;1730   int32_t DrvGPIO_InitI2S(STR_GPIO_I2S_T *I2SFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1731   {
;;;1732   	uint32_t offset, value, shift;
;;;1733   
;;;1734   	/* mclk */
;;;1735   	offset = (I2SFun->mclk & 0xff000000) >> 24;
000002  6802              LDR      r2,[r0,#0]
000004  0e11              LSRS     r1,r2,#24
;;;1736   	shift  = (I2SFun->mclk & 0x00ff0000) >> 16;
000006  0c13              LSRS     r3,r2,#16
;;;1737   	value  = (I2SFun->mclk & 0xff) << shift;
000008  b2d4              UXTB     r4,r2
00000a  409c              LSLS     r4,r4,r3
;;;1738   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00000c  2205              MOVS     r2,#5
00000e  0712              LSLS     r2,r2,#28
000010  188d              ADDS     r5,r1,r2
000012  682f              LDR      r7,[r5,#0]
000014  210f              MOVS     r1,#0xf
000016  460e              MOV      r6,r1
000018  409e              LSLS     r6,r6,r3
00001a  43b7              BICS     r7,r7,r6
00001c  4327              ORRS     r7,r7,r4
00001e  602f              STR      r7,[r5,#0]
;;;1739   
;;;1740   	/* ws_out */
;;;1741   	offset = (I2SFun->ws_out & 0xff000000) >> 24;
000020  6844              LDR      r4,[r0,#4]
000022  0e25              LSRS     r5,r4,#24
;;;1742   	shift  = (I2SFun->ws_out & 0x00ff0000) >> 16;
000024  0c23              LSRS     r3,r4,#16
;;;1743   	value  = (I2SFun->ws_out & 0xff) << shift;
000026  b2e4              UXTB     r4,r4
000028  409c              LSLS     r4,r4,r3
;;;1744   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00002a  18ad              ADDS     r5,r5,r2
00002c  682f              LDR      r7,[r5,#0]
00002e  460e              MOV      r6,r1
000030  409e              LSLS     r6,r6,r3
000032  43b7              BICS     r7,r7,r6
000034  4327              ORRS     r7,r7,r4
000036  602f              STR      r7,[r5,#0]
;;;1745   
;;;1746   	/* bclk */
;;;1747   	offset = (I2SFun->bclk & 0xff000000) >> 24;
000038  6884              LDR      r4,[r0,#8]
00003a  0e25              LSRS     r5,r4,#24
;;;1748   	shift  = (I2SFun->bclk & 0x00ff0000) >> 16;
00003c  0c23              LSRS     r3,r4,#16
;;;1749   	value  = (I2SFun->bclk & 0xff) << shift;
00003e  b2e4              UXTB     r4,r4
000040  409c              LSLS     r4,r4,r3
;;;1750   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000042  18ad              ADDS     r5,r5,r2
000044  682f              LDR      r7,[r5,#0]
000046  460e              MOV      r6,r1
000048  409e              LSLS     r6,r6,r3
00004a  43b7              BICS     r7,r7,r6
00004c  4327              ORRS     r7,r7,r4
00004e  602f              STR      r7,[r5,#0]
;;;1751   
;;;1752   	/* din */
;;;1753   	offset = (I2SFun->din & 0xff000000) >> 24;
000050  68c4              LDR      r4,[r0,#0xc]
000052  0e25              LSRS     r5,r4,#24
;;;1754   	shift  = (I2SFun->din & 0x00ff0000) >> 16;
000054  0c23              LSRS     r3,r4,#16
;;;1755   	value  = (I2SFun->din & 0xff) << shift;
000056  b2e4              UXTB     r4,r4
000058  409c              LSLS     r4,r4,r3
;;;1756   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00005a  18ad              ADDS     r5,r5,r2
00005c  682f              LDR      r7,[r5,#0]
00005e  460e              MOV      r6,r1
000060  409e              LSLS     r6,r6,r3
000062  43b7              BICS     r7,r7,r6
000064  4327              ORRS     r7,r7,r4
000066  602f              STR      r7,[r5,#0]
;;;1757   
;;;1758   	/* dout */
;;;1759   	offset = (I2SFun->dout & 0xff000000) >> 24;
000068  6903              LDR      r3,[r0,#0x10]
00006a  0e1c              LSRS     r4,r3,#24
;;;1760   	shift  = (I2SFun->dout & 0x00ff0000) >> 16;
00006c  0c18              LSRS     r0,r3,#16
;;;1761   	value  = (I2SFun->dout & 0xff) << shift;
00006e  b2db              UXTB     r3,r3
000070  4083              LSLS     r3,r3,r0
;;;1762   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000072  18a2              ADDS     r2,r4,r2
000074  6814              LDR      r4,[r2,#0]
000076  4081              LSLS     r1,r1,r0
000078  438c              BICS     r4,r4,r1
00007a  431c              ORRS     r4,r4,r3
00007c  6014              STR      r4,[r2,#0]
;;;1763   
;;;1764   	return E_SUCCESS;
00007e  2000              MOVS     r0,#0
;;;1765   }
000080  bdf0              POP      {r4-r7,pc}
;;;1766   
                          ENDP


                          AREA ||i.DrvGPIO_InitLCD||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitLCD PROC
;;;1431   /*---------------------------------------------------------------------------------------------------------*/
;;;1432   int32_t DrvGPIO_InitLCD(E_DRVGPIO_LCDTYPE type, E_DRVGPIO_LCDSEG seg)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1433   {
;;;1434   	if (type == E_LCD_100PIN)
;;;1435   	{
;;;1436   		GCR->PB_H_MFP |= 0x7770;    // LCD V1 ~ V3
000002  4e80              LDR      r6,|L32.516|
000004  2205              MOVS     r2,#5
;;;1437   		GCR->PC_L_MFP |= 0x777777;  // LCD COM3 ~ COM0, DH1/DH2
;;;1438   
;;;1439   		switch (seg & 0x3ff)
;;;1440   		{
;;;1441   			case 0x3ff:
;;;1442   			{
;;;1443   				GCR->PA_L_MFP |= 0x77770000;    // seg 36 ~ 39
;;;1444   				GCR->PA_H_MFP |= 0x7777;        // seg 20 ~ 23
;;;1445   				GCR->PB_L_MFP = 0x77777777;     // seg 10 ~ 13, 4 ~ 7
;;;1446   				GCR->PB_H_MFP |= 0x77770007;    // seg 30 ~ 31, 24 ~ 26
;;;1447   				GCR->PC_H_MFP |= 0x77000000;    // seg 32 ~ 33
000006  0533              LSLS     r3,r6,#20
;;;1448   				GCR->PD_L_MFP |= 0x77770000;    // seg 2 ~ 3, 34 ~ 35
;;;1449   				GCR->PD_H_MFP = 0x77777777;     // seg 0 ~ 1, 14 ~ 19
;;;1450   				GCR->PE_L_MFP |= 0x70000000;    // seg 8
000008  011d              LSLS     r5,r3,#4
00000a  0712              LSLS     r2,r2,#28             ;1436
00000c  1df4              ADDS     r4,r6,#7              ;1444
00000e  2800              CMP      r0,#0                 ;1434
000010  d002              BEQ      |L32.24|
;;;1451   				GCR->PE_H_MFP |= 0x77700007;    // seg 9, 27 ~ 29
;;;1452   			}break;
;;;1453   
;;;1454   			case E_LCD_0:
;;;1455   			{
;;;1456   				GCR->PD_L_MFP |= 0x77000000;    // seg 2 ~ 3
;;;1457   				GCR->PD_H_MFP |= 0x77000000;    // seg 0 ~ 1
;;;1458   			}break;
;;;1459   
;;;1460   			case E_LCD_4:
;;;1461   			{
;;;1462   				GCR->PB_L_MFP |= 0x7777;        // seg 4 ~ 7
;;;1463   			}break;
;;;1464   
;;;1465   			case E_LCD_8:
;;;1466   			{
;;;1467   				GCR->PE_L_MFP |= 0x70000000;    // seg 8
;;;1468   				GCR->PE_H_MFP |= 0x7;           // seg 9
;;;1469   				GCR->PB_L_MFP |= 0x77000000;    // seg 10 ~ 11
;;;1470   			}break;
;;;1471   
;;;1472   			case E_LCD_12:
;;;1473   			{
;;;1474   				GCR->PB_L_MFP |= 0x770000;      // seg 12 ~ 13
;;;1475   				GCR->PD_H_MFP |= 0x770000;      // seg 14 ~ 15
;;;1476   			}break;
;;;1477   
;;;1478   			case E_LCD_16:
;;;1479   			{
;;;1480   				GCR->PD_H_MFP |= 0x7777;        // seg 16 ~ 19
;;;1481   			}break;
;;;1482   
;;;1483   			case E_LCD_20:
;;;1484   			{
;;;1485   				GCR->PA_H_MFP |= 0x7777;        // seg 20 ~ 23
;;;1486   			}break;
;;;1487   
;;;1488   			case E_LCD_24:
;;;1489   			{
;;;1490   				GCR->PB_H_MFP |= 0x7770000;     // seg 24 ~ 26
;;;1491   				GCR->PE_H_MFP |= 0x700000;      // seg 27
;;;1492   			}break;
;;;1493   
;;;1494   			case E_LCD_28:
;;;1495   			{
;;;1496   				GCR->PB_H_MFP |= 0x70000007;    // seg 30 ~ 31
;;;1497   				GCR->PE_H_MFP |= 0x77000000;    // seg 28 ~ 29
;;;1498   			}break;
;;;1499   
;;;1500   			case E_LCD_32:
;;;1501   			{
;;;1502   				GCR->PC_H_MFP |= 0x77000000;    // seg 32 ~ 33
;;;1503   				GCR->PD_L_MFP |= 0x770000;      // seg 34 ~ 35
;;;1504   			}break;
;;;1505   
;;;1506   			case E_LCD_36:
;;;1507   			{
;;;1508   				GCR->PA_L_MFP |= 0x77770000;    // seg 36 ~ 39
;;;1509   			}break;
;;;1510   
;;;1511   			default:
;;;1512   				return E_DRVGPIO_ARGUMENT;
;;;1513   		}
;;;1514   	}
;;;1515   	else if (type == E_LCD_64PIN)
000012  2801              CMP      r0,#1
000014  d071              BEQ      |L32.250|
000016  e0a7              B        |L32.360|
                  |L32.24|
000018  6bd0              LDR      r0,[r2,#0x3c]         ;1436
00001a  4330              ORRS     r0,r0,r6              ;1436
00001c  63d0              STR      r0,[r2,#0x3c]         ;1436
00001e  4e7a              LDR      r6,|L32.520|
000020  6830              LDR      r0,[r6,#0]            ;1437
000022  4f7a              LDR      r7,|L32.524|
000024  4338              ORRS     r0,r0,r7              ;1437
000026  6030              STR      r0,[r6,#0]            ;1437
000028  0588              LSLS     r0,r1,#22             ;1439
00002a  0d80              LSRS     r0,r0,#22             ;1439
00002c  2820              CMP      r0,#0x20              ;1439
00002e  d058              BEQ      |L32.226|
000030  dc0c              BGT      |L32.76|
000032  2804              CMP      r0,#4                 ;1439
000034  d03f              BEQ      |L32.182|
000036  dc04              BGT      |L32.66|
000038  2801              CMP      r0,#1                 ;1439
00003a  d033              BEQ      |L32.164|
00003c  2802              CMP      r0,#2                 ;1439
00003e  d16e              BNE      |L32.286|
000040  e036              B        |L32.176|
                  |L32.66|
000042  2808              CMP      r0,#8                 ;1439
000044  d041              BEQ      |L32.202|
000046  2810              CMP      r0,#0x10              ;1439
000048  d169              BNE      |L32.286|
00004a  e046              B        |L32.218|
                  |L32.76|
00004c  27ff              MOVS     r7,#0xff              ;1439
00004e  3701              ADDS     r7,#1                 ;1439
000050  1bc1              SUBS     r1,r0,r7              ;1439
000052  42b8              CMP      r0,r7                 ;1439
000054  d05a              BEQ      |L32.268|
000056  dc04              BGT      |L32.98|
000058  2840              CMP      r0,#0x40              ;1439
00005a  d045              BEQ      |L32.232|
00005c  2880              CMP      r0,#0x80              ;1439
00005e  d15e              BNE      |L32.286|
000060  e04c              B        |L32.252|
                  |L32.98|
000062  39ff              SUBS     r1,r1,#0xff           ;1439
000064  3901              SUBS     r1,#1                 ;1439
000066  d05b              BEQ      |L32.288|
000068  39ff              SUBS     r1,r1,#0xff           ;1439
00006a  39ff              SUBS     r1,r1,#0xff           ;1439
00006c  3901              SUBS     r1,#1                 ;1439
00006e  d17b              BNE      |L32.360|
000070  6b10              LDR      r0,[r2,#0x30]         ;1443
000072  4967              LDR      r1,|L32.528|
000074  4308              ORRS     r0,r0,r1              ;1443
000076  6310              STR      r0,[r2,#0x30]         ;1443
000078  6b50              LDR      r0,[r2,#0x34]         ;1444
00007a  4320              ORRS     r0,r0,r4              ;1444
00007c  6350              STR      r0,[r2,#0x34]         ;1444
00007e  4c65              LDR      r4,|L32.532|
000080  6394              STR      r4,[r2,#0x38]         ;1445
000082  6bd0              LDR      r0,[r2,#0x3c]         ;1446
000084  1dcf              ADDS     r7,r1,#7              ;1446
000086  4338              ORRS     r0,r0,r7              ;1446
000088  63d0              STR      r0,[r2,#0x3c]         ;1446
00008a  6870              LDR      r0,[r6,#4]            ;1447
00008c  4318              ORRS     r0,r0,r3              ;1447
00008e  6070              STR      r0,[r6,#4]            ;1447
000090  68b0              LDR      r0,[r6,#8]            ;1448
000092  4308              ORRS     r0,r0,r1              ;1448
000094  60b0              STR      r0,[r6,#8]            ;1448
000096  60f4              STR      r4,[r6,#0xc]          ;1449
000098  6930              LDR      r0,[r6,#0x10]         ;1450
00009a  4328              ORRS     r0,r0,r5              ;1450
00009c  6130              STR      r0,[r6,#0x10]         ;1450
00009e  6970              LDR      r0,[r6,#0x14]         ;1451
0000a0  495d              LDR      r1,|L32.536|
0000a2  e028              B        |L32.246|
                  |L32.164|
0000a4  68b0              LDR      r0,[r6,#8]            ;1456
0000a6  4318              ORRS     r0,r0,r3              ;1456
0000a8  60b0              STR      r0,[r6,#8]            ;1456
0000aa  68f0              LDR      r0,[r6,#0xc]          ;1457
0000ac  4318              ORRS     r0,r0,r3              ;1457
0000ae  e016              B        |L32.222|
                  |L32.176|
0000b0  6b90              LDR      r0,[r2,#0x38]         ;1462
0000b2  4320              ORRS     r0,r0,r4              ;1462
0000b4  e07b              B        |L32.430|
                  |L32.182|
0000b6  6930              LDR      r0,[r6,#0x10]         ;1467
0000b8  4328              ORRS     r0,r0,r5              ;1467
0000ba  6130              STR      r0,[r6,#0x10]         ;1467
0000bc  6970              LDR      r0,[r6,#0x14]         ;1468
0000be  2107              MOVS     r1,#7                 ;1468
0000c0  4308              ORRS     r0,r0,r1              ;1468
0000c2  6170              STR      r0,[r6,#0x14]         ;1468
0000c4  6b90              LDR      r0,[r2,#0x38]         ;1469
0000c6  4318              ORRS     r0,r0,r3              ;1469
0000c8  e071              B        |L32.430|
                  |L32.202|
0000ca  6b90              LDR      r0,[r2,#0x38]         ;1474
0000cc  2177              MOVS     r1,#0x77              ;1474
0000ce  0409              LSLS     r1,r1,#16             ;1474
0000d0  4308              ORRS     r0,r0,r1              ;1474
0000d2  6390              STR      r0,[r2,#0x38]         ;1474
0000d4  68f0              LDR      r0,[r6,#0xc]          ;1475
0000d6  4308              ORRS     r0,r0,r1              ;1475
0000d8  e001              B        |L32.222|
                  |L32.218|
0000da  68f0              LDR      r0,[r6,#0xc]          ;1480
0000dc  4320              ORRS     r0,r0,r4              ;1480
                  |L32.222|
0000de  60f0              STR      r0,[r6,#0xc]          ;1480
0000e0  e08b              B        |L32.506|
                  |L32.226|
0000e2  6b50              LDR      r0,[r2,#0x34]         ;1485
0000e4  4320              ORRS     r0,r0,r4              ;1485
0000e6  e087              B        |L32.504|
                  |L32.232|
0000e8  6bd0              LDR      r0,[r2,#0x3c]         ;1490
0000ea  494c              LDR      r1,|L32.540|
0000ec  4308              ORRS     r0,r0,r1              ;1490
0000ee  63d0              STR      r0,[r2,#0x3c]         ;1490
0000f0  6970              LDR      r0,[r6,#0x14]         ;1491
0000f2  2107              MOVS     r1,#7                 ;1491
0000f4  0509              LSLS     r1,r1,#20             ;1491
                  |L32.246|
0000f6  4308              ORRS     r0,r0,r1              ;1451
0000f8  e006              B        |L32.264|
                  |L32.250|
0000fa  e014              B        |L32.294|
                  |L32.252|
0000fc  6bd0              LDR      r0,[r2,#0x3c]         ;1496
0000fe  4948              LDR      r1,|L32.544|
000100  4308              ORRS     r0,r0,r1              ;1496
000102  63d0              STR      r0,[r2,#0x3c]         ;1496
000104  6970              LDR      r0,[r6,#0x14]         ;1497
000106  4318              ORRS     r0,r0,r3              ;1497
                  |L32.264|
000108  6170              STR      r0,[r6,#0x14]         ;1497
00010a  e076              B        |L32.506|
                  |L32.268|
00010c  6870              LDR      r0,[r6,#4]            ;1502
00010e  4318              ORRS     r0,r0,r3              ;1502
000110  6070              STR      r0,[r6,#4]            ;1502
000112  68b0              LDR      r0,[r6,#8]            ;1503
000114  2177              MOVS     r1,#0x77              ;1503
000116  0409              LSLS     r1,r1,#16             ;1503
000118  4308              ORRS     r0,r0,r1              ;1503
00011a  60b0              STR      r0,[r6,#8]            ;1503
00011c  e06d              B        |L32.506|
                  |L32.286|
00011e  e023              B        |L32.360|
                  |L32.288|
000120  6b10              LDR      r0,[r2,#0x30]         ;1508
000122  493b              LDR      r1,|L32.528|
000124  e064              B        |L32.496|
                  |L32.294|
;;;1516   	{
;;;1517   		GCR->PB_L_MFP |= 0x7700;    // COM2, COM3
000126  6b90              LDR      r0,[r2,#0x38]
000128  2777              MOVS     r7,#0x77
00012a  023f              LSLS     r7,r7,#8
00012c  4338              ORRS     r0,r0,r7
00012e  6390              STR      r0,[r2,#0x38]
;;;1518   		GCR->PB_H_MFP |= 0x7770;    // LCD V1 ~ V3
000130  6bd0              LDR      r0,[r2,#0x3c]
000132  4330              ORRS     r0,r0,r6
000134  63d0              STR      r0,[r2,#0x3c]
;;;1519   		GCR->PC_L_MFP |= 0x7777;    // LCD COM1 ~ COM0, DH1/DH2
000136  4e34              LDR      r6,|L32.520|
000138  6830              LDR      r0,[r6,#0]
00013a  4320              ORRS     r0,r0,r4
00013c  6030              STR      r0,[r6,#0]
;;;1520   
;;;1521   		switch (seg & 0xff)
00013e  b2c8              UXTB     r0,r1
000140  2810              CMP      r0,#0x10
000142  d049              BEQ      |L32.472|
000144  dc08              BGT      |L32.344|
000146  2801              CMP      r0,#1
000148  d027              BEQ      |L32.410|
00014a  2802              CMP      r0,#2
00014c  d028              BEQ      |L32.416|
00014e  2804              CMP      r0,#4
000150  d02f              BEQ      |L32.434|
000152  2808              CMP      r0,#8
000154  d108              BNE      |L32.360|
000156  e035              B        |L32.452|
                  |L32.344|
000158  2820              CMP      r0,#0x20
00015a  d046              BEQ      |L32.490|
00015c  2840              CMP      r0,#0x40
00015e  d04a              BEQ      |L32.502|
000160  2880              CMP      r0,#0x80
000162  d04c              BEQ      |L32.510|
000164  28ff              CMP      r0,#0xff
000166  d001              BEQ      |L32.364|
                  |L32.360|
;;;1522   		{
;;;1523   			case 0xff:
;;;1524   			{
;;;1525   				GCR->PA_L_MFP |= 0x77777700;    // seg 18 ~ 23
;;;1526   				GCR->PA_H_MFP = 0x77777777;     // seg 6 ~ 9, 24 ~ 27
;;;1527   				GCR->PB_L_MFP |= 0x77770077;    // seg 0 ~ 5
;;;1528   				GCR->PB_H_MFP |= 0x77770007;    // seg 10 ~ 14
;;;1529   				GCR->PC_L_MFP |= 0x70000000;    // seg 17
;;;1530   				GCR->PC_H_MFP |= 0x77007777;    // seg 28 ~ 31, 15 ~ 16
;;;1531   			}break;
;;;1532   
;;;1533   			case E_LCD_0:
;;;1534   			{
;;;1535   				GCR->PB_L_MFP |= 0x77000077;    // seg 0 ~ 3
;;;1536   			}break;
;;;1537   
;;;1538   			case E_LCD_4:
;;;1539   			{
;;;1540   				GCR->PA_H_MFP |= 0x77;          // seg 6 ~ 7
;;;1541   				GCR->PB_L_MFP |= 0x770000;      // seg 4 ~ 5
;;;1542   			}break;
;;;1543   
;;;1544   			case E_LCD_8:
;;;1545   			{
;;;1546   				GCR->PA_H_MFP |= 0x7700;        // seg 8 ~ 9
;;;1547   				GCR->PB_H_MFP |= 0x770000;      // seg 10 ~ 11
;;;1548   			}break;
;;;1549   
;;;1550   			case E_LCD_12:
;;;1551   			{
;;;1552   				GCR->PB_H_MFP |= 0x77000007;    // seg 12 ~ 14
;;;1553   				GCR->PC_H_MFP |= 0x7000000;     // seg 15
;;;1554   			}break;
;;;1555   
;;;1556   			case E_LCD_16:
;;;1557   			{
;;;1558   				GCR->PA_L_MFP |= 0x77000000;    // seg 18 ~ 19
;;;1559   				GCR->PC_L_MFP |= 0x70000000;    // seg 17
;;;1560   				GCR->PC_H_MFP |= 0x70000000;    // seg 16
;;;1561   			}break;
;;;1562   
;;;1563   			case E_LCD_20:
;;;1564   			{
;;;1565   				GCR->PA_L_MFP |= 0x777700;      // seg 20 ~ 23
;;;1566   			}break;
;;;1567   
;;;1568   			case E_LCD_24:
;;;1569   			{
;;;1570   				GCR->PA_H_MFP = 0x77770000;     // seg 24 ~ 27
;;;1571   			}break;
;;;1572   
;;;1573   			case E_LCD_28:
;;;1574   			{
;;;1575   				GCR->PC_H_MFP |= 0x7777;        // seg 28 ~ 31
;;;1576   			}break;
;;;1577   
;;;1578   			default:
;;;1579   				return E_DRVGPIO_ARGUMENT;
;;;1580   		}
;;;1581   	}
;;;1582   	else
;;;1583   		return E_DRVGPIO_ARGUMENT;
000168  482e              LDR      r0,|L32.548|
;;;1584   	return E_SUCCESS;
;;;1585   }
00016a  bdf0              POP      {r4-r7,pc}
                  |L32.364|
00016c  6b10              LDR      r0,[r2,#0x30]         ;1525
00016e  4929              LDR      r1,|L32.532|
000170  3977              SUBS     r1,r1,#0x77           ;1525
000172  4308              ORRS     r0,r0,r1              ;1525
000174  6310              STR      r0,[r2,#0x30]         ;1525
000176  4827              LDR      r0,|L32.532|
000178  6350              STR      r0,[r2,#0x34]         ;1526
00017a  6b90              LDR      r0,[r2,#0x38]         ;1527
00017c  4924              LDR      r1,|L32.528|
00017e  3177              ADDS     r1,r1,#0x77           ;1527
000180  4308              ORRS     r0,r0,r1              ;1527
000182  6390              STR      r0,[r2,#0x38]         ;1527
000184  6bd1              LDR      r1,[r2,#0x3c]         ;1528
000186  4822              LDR      r0,|L32.528|
000188  1dc0              ADDS     r0,r0,#7              ;1528
00018a  4301              ORRS     r1,r1,r0              ;1528
00018c  63d1              STR      r1,[r2,#0x3c]         ;1528
00018e  6830              LDR      r0,[r6,#0]            ;1529
000190  4328              ORRS     r0,r0,r5              ;1529
000192  6030              STR      r0,[r6,#0]            ;1529
000194  6870              LDR      r0,[r6,#4]            ;1530
000196  4924              LDR      r1,|L32.552|
000198  e01b              B        |L32.466|
                  |L32.410|
00019a  6b90              LDR      r0,[r2,#0x38]         ;1535
00019c  4923              LDR      r1,|L32.556|
00019e  e005              B        |L32.428|
                  |L32.416|
0001a0  6b50              LDR      r0,[r2,#0x34]         ;1540
0001a2  2177              MOVS     r1,#0x77              ;1540
0001a4  4308              ORRS     r0,r0,r1              ;1540
0001a6  6350              STR      r0,[r2,#0x34]         ;1540
0001a8  6b90              LDR      r0,[r2,#0x38]         ;1541
0001aa  0409              LSLS     r1,r1,#16             ;1541
                  |L32.428|
0001ac  4308              ORRS     r0,r0,r1              ;1535
                  |L32.430|
0001ae  6390              STR      r0,[r2,#0x38]         ;1535
0001b0  e023              B        |L32.506|
                  |L32.434|
0001b2  6b51              LDR      r1,[r2,#0x34]         ;1546
0001b4  4339              ORRS     r1,r1,r7              ;1546
0001b6  6351              STR      r1,[r2,#0x34]         ;1546
0001b8  6bd0              LDR      r0,[r2,#0x3c]         ;1547
0001ba  2177              MOVS     r1,#0x77              ;1547
0001bc  0409              LSLS     r1,r1,#16             ;1547
0001be  4308              ORRS     r0,r0,r1              ;1547
0001c0  63d0              STR      r0,[r2,#0x3c]         ;1547
0001c2  e01a              B        |L32.506|
                  |L32.452|
0001c4  6bd0              LDR      r0,[r2,#0x3c]         ;1552
0001c6  4919              LDR      r1,|L32.556|
0001c8  3970              SUBS     r1,r1,#0x70           ;1552
0001ca  4308              ORRS     r0,r0,r1              ;1552
0001cc  63d0              STR      r0,[r2,#0x3c]         ;1552
0001ce  6870              LDR      r0,[r6,#4]            ;1553
0001d0  0609              LSLS     r1,r1,#24             ;1553
                  |L32.466|
0001d2  4308              ORRS     r0,r0,r1              ;1530
                  |L32.468|
0001d4  6070              STR      r0,[r6,#4]            ;1530
0001d6  e010              B        |L32.506|
                  |L32.472|
0001d8  6b10              LDR      r0,[r2,#0x30]         ;1558
0001da  4318              ORRS     r0,r0,r3              ;1558
0001dc  6310              STR      r0,[r2,#0x30]         ;1558
0001de  6830              LDR      r0,[r6,#0]            ;1559
0001e0  4328              ORRS     r0,r0,r5              ;1559
0001e2  6030              STR      r0,[r6,#0]            ;1559
0001e4  6870              LDR      r0,[r6,#4]            ;1560
0001e6  4328              ORRS     r0,r0,r5              ;1560
0001e8  e7f4              B        |L32.468|
                  |L32.490|
0001ea  6b10              LDR      r0,[r2,#0x30]         ;1565
0001ec  4907              LDR      r1,|L32.524|
0001ee  3977              SUBS     r1,r1,#0x77           ;1565
                  |L32.496|
0001f0  4308              ORRS     r0,r0,r1              ;1565
0001f2  6310              STR      r0,[r2,#0x30]         ;1565
0001f4  e001              B        |L32.506|
                  |L32.502|
0001f6  4806              LDR      r0,|L32.528|
                  |L32.504|
0001f8  6350              STR      r0,[r2,#0x34]         ;1570
                  |L32.506|
0001fa  2000              MOVS     r0,#0                 ;1584
0001fc  bdf0              POP      {r4-r7,pc}
                  |L32.510|
0001fe  6870              LDR      r0,[r6,#4]            ;1575
000200  4320              ORRS     r0,r0,r4              ;1575
000202  e7e7              B        |L32.468|
;;;1586   
                          ENDP

                  |L32.516|
                          DCD      0x00007770
                  |L32.520|
                          DCD      0x50000040
                  |L32.524|
                          DCD      0x00777777
                  |L32.528|
                          DCD      0x77770000
                  |L32.532|
                          DCD      0x77777777
                  |L32.536|
                          DCD      0x77700007
                  |L32.540|
                          DCD      0x07770000
                  |L32.544|
                          DCD      0x70000007
                  |L32.548|
                          DCD      0xffff8901
                  |L32.552|
                          DCD      0x77007777
                  |L32.556|
                          DCD      0x77000077

                          AREA ||i.DrvGPIO_InitPWM||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitPWM PROC
;;;1695   /*---------------------------------------------------------------------------------------------------------*/
;;;1696   int32_t DrvGPIO_InitPWM(E_DRVGPIO_PWM channel)
000000  0e03              LSRS     r3,r0,#24
;;;1697   {
;;;1698   	uint32_t offset, value, shift;
;;;1699   
;;;1700   	offset = (channel & 0xff000000) >> 24;
;;;1701   	shift  = (channel & 0x00ff0000) >> 16;
000002  0c01              LSRS     r1,r0,#16
;;;1702   	value  = (channel & 0xff) << shift;
000004  b2c2              UXTB     r2,r0
000006  408a              LSLS     r2,r2,r1
;;;1703   
;;;1704   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000008  2005              MOVS     r0,#5
00000a  b510              PUSH     {r4,lr}               ;1697
00000c  0700              LSLS     r0,r0,#28
00000e  1818              ADDS     r0,r3,r0
000010  6803              LDR      r3,[r0,#0]
000012  240f              MOVS     r4,#0xf
000014  408c              LSLS     r4,r4,r1
000016  43a3              BICS     r3,r3,r4
000018  4313              ORRS     r3,r3,r2
00001a  6003              STR      r3,[r0,#0]
;;;1705   
;;;1706   	return E_SUCCESS;
00001c  2000              MOVS     r0,#0
;;;1707   }
00001e  bd10              POP      {r4,pc}
;;;1708   
                          ENDP


                          AREA ||i.DrvGPIO_InitRTCSnooper||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitRTCSnooper PROC
;;;1286   /*---------------------------------------------------------------------------------------------------------*/
;;;1287   int32_t DrvGPIO_InitRTCSnooper(E_DRVGPIO_RTC pin)
000000  0e03              LSRS     r3,r0,#24
;;;1288   {
;;;1289   	uint32_t offset, value, shift;
;;;1290   
;;;1291   	offset = (pin & 0xff000000) >> 24;
;;;1292   	shift  = (pin & 0x00ff0000) >> 16;
000002  0c01              LSRS     r1,r0,#16
;;;1293   	value  = (pin & 0xff) << shift;
000004  b2c2              UXTB     r2,r0
000006  408a              LSLS     r2,r2,r1
;;;1294   
;;;1295   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000008  2005              MOVS     r0,#5
00000a  b510              PUSH     {r4,lr}               ;1288
00000c  0700              LSLS     r0,r0,#28
00000e  1818              ADDS     r0,r3,r0
000010  6803              LDR      r3,[r0,#0]
000012  240f              MOVS     r4,#0xf
000014  408c              LSLS     r4,r4,r1
000016  43a3              BICS     r3,r3,r4
000018  4313              ORRS     r3,r3,r2
00001a  6003              STR      r3,[r0,#0]
;;;1296   
;;;1297   	return E_SUCCESS;
00001c  2000              MOVS     r0,#0
;;;1298   }
00001e  bd10              POP      {r4,pc}
;;;1299   
                          ENDP


                          AREA ||i.DrvGPIO_InitSPI0||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitSPI0 PROC
;;;1863   /*---------------------------------------------------------------------------------------------------------*/
;;;1864   int32_t DrvGPIO_InitSPI0(STR_GPIO_SPI0_T *SPIFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1865   {
;;;1866   	uint32_t offset, value, shift;
;;;1867   
;;;1868   	/* clk */
;;;1869   	offset = (SPIFun->clk & 0xff000000) >> 24;
000002  6802              LDR      r2,[r0,#0]
;;;1870   	shift  = (SPIFun->clk & 0x00ff0000) >> 16;
;;;1871   	value  = (SPIFun->clk & 0xff) << shift;
;;;1872   
;;;1873   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000004  2505              MOVS     r5,#5
000006  0e13              LSRS     r3,r2,#24             ;1869
000008  0c11              LSRS     r1,r2,#16             ;1870
00000a  b2d2              UXTB     r2,r2                 ;1871
00000c  408a              LSLS     r2,r2,r1              ;1871
00000e  072d              LSLS     r5,r5,#28
000010  195b              ADDS     r3,r3,r5
000012  681f              LDR      r7,[r3,#0]
000014  240f              MOVS     r4,#0xf
000016  4626              MOV      r6,r4
000018  408e              LSLS     r6,r6,r1
00001a  43b7              BICS     r7,r7,r6
00001c  4317              ORRS     r7,r7,r2
00001e  601f              STR      r7,[r3,#0]
;;;1874   
;;;1875   	/* ss0 */
;;;1876   	offset = (SPIFun->ss0 & 0xff000000) >> 24;
000020  6841              LDR      r1,[r0,#4]
000022  0e0b              LSRS     r3,r1,#24
;;;1877   	shift  = (SPIFun->ss0 & 0x00ff0000) >> 16;
000024  020a              LSLS     r2,r1,#8
000026  0e12              LSRS     r2,r2,#24
;;;1878   	value  = (SPIFun->ss0 & 0xff) << shift;
000028  b2c9              UXTB     r1,r1
00002a  4091              LSLS     r1,r1,r2
;;;1879   
;;;1880   	if (value)
00002c  d006              BEQ      |L35.60|
;;;1881   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00002e  195b              ADDS     r3,r3,r5
000030  681e              LDR      r6,[r3,#0]
000032  4627              MOV      r7,r4
000034  4097              LSLS     r7,r7,r2
000036  43be              BICS     r6,r6,r7
000038  430e              ORRS     r6,r6,r1
00003a  601e              STR      r6,[r3,#0]
                  |L35.60|
;;;1882   
;;;1883   	if (SPIFun->ss1 == 1)   /* GPB10 */
00003c  7a01              LDRB     r1,[r0,#8]
00003e  2901              CMP      r1,#1
000040  d106              BNE      |L35.80|
;;;1884   		GCR->PB_H_MFP_BITS.PB10 = 0x1;
000042  6be9              LDR      r1,[r5,#0x3c]
000044  2207              MOVS     r2,#7
000046  0212              LSLS     r2,r2,#8
000048  4391              BICS     r1,r1,r2
00004a  31ff              ADDS     r1,r1,#0xff
00004c  3101              ADDS     r1,#1
00004e  63e9              STR      r1,[r5,#0x3c]
                  |L35.80|
;;;1885   
;;;1886   	/* miso0 */
;;;1887   	offset = (SPIFun->miso0 & 0xff000000) >> 24;
000050  68c1              LDR      r1,[r0,#0xc]
000052  0e0a              LSRS     r2,r1,#24
;;;1888   	shift  = (SPIFun->miso0 & 0x00ff0000) >> 16;
000054  0c0b              LSRS     r3,r1,#16
;;;1889   	value  = (SPIFun->miso0 & 0xff) << shift;
000056  b2c9              UXTB     r1,r1
000058  4099              LSLS     r1,r1,r3
;;;1890   
;;;1891   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00005a  1952              ADDS     r2,r2,r5
00005c  6816              LDR      r6,[r2,#0]
00005e  4627              MOV      r7,r4
000060  409f              LSLS     r7,r7,r3
000062  43be              BICS     r6,r6,r7
000064  430e              ORRS     r6,r6,r1
000066  6016              STR      r6,[r2,#0]
;;;1892   
;;;1893   	/* mosi0 */
;;;1894   	offset = (SPIFun->mosi0 & 0xff000000) >> 24;
000068  6902              LDR      r2,[r0,#0x10]
00006a  0e13              LSRS     r3,r2,#24
;;;1895   	shift  = (SPIFun->mosi0 & 0x00ff0000) >> 16;
00006c  0c11              LSRS     r1,r2,#16
;;;1896   	value  = (SPIFun->mosi0 & 0xff) << shift;
00006e  b2d2              UXTB     r2,r2
000070  408a              LSLS     r2,r2,r1
;;;1897   
;;;1898   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000072  195b              ADDS     r3,r3,r5
000074  681d              LDR      r5,[r3,#0]
000076  408c              LSLS     r4,r4,r1
000078  43a5              BICS     r5,r5,r4
00007a  4315              ORRS     r5,r5,r2
00007c  601d              STR      r5,[r3,#0]
;;;1899   
;;;1900   	if (SPIFun->miso1 == 1) /* GPC4 */
00007e  7d02              LDRB     r2,[r0,#0x14]
;;;1901   		GCR->PC_L_MFP_BITS.PC4 = 0x1;
000080  490b              LDR      r1,|L35.176|
000082  2a01              CMP      r2,#1                 ;1900
000084  d106              BNE      |L35.148|
000086  680a              LDR      r2,[r1,#0]
000088  2307              MOVS     r3,#7
00008a  041b              LSLS     r3,r3,#16
00008c  439a              BICS     r2,r2,r3
00008e  028b              LSLS     r3,r1,#10
000090  18d2              ADDS     r2,r2,r3
000092  600a              STR      r2,[r1,#0]
                  |L35.148|
;;;1902   
;;;1903   	if (SPIFun->mosi1 == 1) /* GPC5 */
000094  7d40              LDRB     r0,[r0,#0x15]
000096  2801              CMP      r0,#1
000098  d107              BNE      |L35.170|
;;;1904   		GCR->PC_L_MFP_BITS.PC5 = 0x1;
00009a  6808              LDR      r0,[r1,#0]
00009c  2207              MOVS     r2,#7
00009e  0512              LSLS     r2,r2,#20
0000a0  4390              BICS     r0,r0,r2
0000a2  2201              MOVS     r2,#1
0000a4  0512              LSLS     r2,r2,#20
0000a6  1880              ADDS     r0,r0,r2
0000a8  6008              STR      r0,[r1,#0]
                  |L35.170|
;;;1905   
;;;1906   	return E_SUCCESS;
0000aa  2000              MOVS     r0,#0
;;;1907   }
0000ac  bdf0              POP      {r4-r7,pc}
;;;1908   
                          ENDP

0000ae  0000              DCW      0x0000
                  |L35.176|
                          DCD      0x50000040

                          AREA ||i.DrvGPIO_InitSPI1||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitSPI1 PROC
;;;1927   /*---------------------------------------------------------------------------------------------------------*/
;;;1928   int32_t DrvGPIO_InitSPI1(STR_GPIO_SPI1_T *SPIFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1929   {
;;;1930   	uint32_t offset, value, shift;
;;;1931   
;;;1932   	/* clk */
;;;1933   	offset = (SPIFun->clk & 0xff000000) >> 24;
000002  6802              LDR      r2,[r0,#0]
;;;1934   	shift  = (SPIFun->clk & 0x00ff0000) >> 16;
;;;1935   	value  = (SPIFun->clk & 0xff) << shift;
;;;1936   
;;;1937   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000004  2505              MOVS     r5,#5
000006  0e13              LSRS     r3,r2,#24             ;1933
000008  0c11              LSRS     r1,r2,#16             ;1934
00000a  b2d2              UXTB     r2,r2                 ;1935
00000c  408a              LSLS     r2,r2,r1              ;1935
00000e  072d              LSLS     r5,r5,#28
000010  195b              ADDS     r3,r3,r5
000012  681f              LDR      r7,[r3,#0]
000014  240f              MOVS     r4,#0xf
000016  4626              MOV      r6,r4
000018  408e              LSLS     r6,r6,r1
00001a  43b7              BICS     r7,r7,r6
00001c  4317              ORRS     r7,r7,r2
00001e  601f              STR      r7,[r3,#0]
;;;1938   
;;;1939   	/* ss0 */
;;;1940   	offset = (SPIFun->ss0 & 0xff000000) >> 24;
000020  6841              LDR      r1,[r0,#4]
000022  0e0b              LSRS     r3,r1,#24
;;;1941   	shift  = (SPIFun->ss0 & 0x00ff0000) >> 16;
000024  020a              LSLS     r2,r1,#8
000026  0e12              LSRS     r2,r2,#24
;;;1942   	value  = (SPIFun->ss0 & 0xff) << shift;
000028  b2c9              UXTB     r1,r1
00002a  4091              LSLS     r1,r1,r2
;;;1943   
;;;1944   	if (value)
00002c  d006              BEQ      |L36.60|
;;;1945   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00002e  195b              ADDS     r3,r3,r5
000030  681e              LDR      r6,[r3,#0]
000032  4627              MOV      r7,r4
000034  4097              LSLS     r7,r7,r2
000036  43be              BICS     r6,r6,r7
000038  430e              ORRS     r6,r6,r1
00003a  601e              STR      r6,[r3,#0]
                  |L36.60|
;;;1946   
;;;1947   	if (SPIFun->ss1 == 1)   /* GPB9 */
00003c  7a01              LDRB     r1,[r0,#8]
00003e  2901              CMP      r1,#1
000040  d104              BNE      |L36.76|
;;;1948   		GCR->PB_H_MFP_BITS.PB9 = 0x1;
000042  6be9              LDR      r1,[r5,#0x3c]
000044  2270              MOVS     r2,#0x70
000046  4391              BICS     r1,r1,r2
000048  3110              ADDS     r1,r1,#0x10
00004a  63e9              STR      r1,[r5,#0x3c]
                  |L36.76|
;;;1949   
;;;1950   	/* miso0 */
;;;1951   	offset = (SPIFun->miso0 & 0xff000000) >> 24;
00004c  68c1              LDR      r1,[r0,#0xc]
00004e  0e0a              LSRS     r2,r1,#24
;;;1952   	shift  = (SPIFun->miso0 & 0x00ff0000) >> 16;
000050  0c0b              LSRS     r3,r1,#16
;;;1953   	value  = (SPIFun->miso0 & 0xff) << shift;
000052  b2c9              UXTB     r1,r1
000054  4099              LSLS     r1,r1,r3
;;;1954   
;;;1955   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000056  1952              ADDS     r2,r2,r5
000058  6816              LDR      r6,[r2,#0]
00005a  4627              MOV      r7,r4
00005c  409f              LSLS     r7,r7,r3
00005e  43be              BICS     r6,r6,r7
000060  430e              ORRS     r6,r6,r1
000062  6016              STR      r6,[r2,#0]
;;;1956   
;;;1957   	/* mosi0 */
;;;1958   	offset = (SPIFun->mosi0 & 0xff000000) >> 24;
000064  6902              LDR      r2,[r0,#0x10]
000066  0e13              LSRS     r3,r2,#24
;;;1959   	shift  = (SPIFun->mosi0 & 0x00ff0000) >> 16;
000068  0c11              LSRS     r1,r2,#16
;;;1960   	value  = (SPIFun->mosi0 & 0xff) << shift;
00006a  b2d2              UXTB     r2,r2
00006c  408a              LSLS     r2,r2,r1
;;;1961   
;;;1962   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00006e  195b              ADDS     r3,r3,r5
000070  681d              LDR      r5,[r3,#0]
000072  408c              LSLS     r4,r4,r1
000074  43a5              BICS     r5,r5,r4
000076  4315              ORRS     r5,r5,r2
000078  601d              STR      r5,[r3,#0]
;;;1963   
;;;1964   	if (SPIFun->miso1 == 1) /* GPC12 */
00007a  7d02              LDRB     r2,[r0,#0x14]
;;;1965   		GCR->PC_H_MFP_BITS.PC12 = 0x1;
00007c  490b              LDR      r1,|L36.172|
00007e  2a01              CMP      r2,#1                 ;1964
000080  d106              BNE      |L36.144|
000082  684a              LDR      r2,[r1,#4]
000084  2307              MOVS     r3,#7
000086  041b              LSLS     r3,r3,#16
000088  439a              BICS     r2,r2,r3
00008a  028b              LSLS     r3,r1,#10
00008c  18d2              ADDS     r2,r2,r3
00008e  604a              STR      r2,[r1,#4]
                  |L36.144|
;;;1966   
;;;1967   	if (SPIFun->mosi1 == 1) /* GPC13 */
000090  7d40              LDRB     r0,[r0,#0x15]
000092  2801              CMP      r0,#1
000094  d107              BNE      |L36.166|
;;;1968   		GCR->PC_H_MFP_BITS.PC13 = 0x1;
000096  6848              LDR      r0,[r1,#4]
000098  2207              MOVS     r2,#7
00009a  0512              LSLS     r2,r2,#20
00009c  4390              BICS     r0,r0,r2
00009e  2201              MOVS     r2,#1
0000a0  0512              LSLS     r2,r2,#20
0000a2  1880              ADDS     r0,r0,r2
0000a4  6048              STR      r0,[r1,#4]
                  |L36.166|
;;;1969   
;;;1970   	return E_SUCCESS;
0000a6  2000              MOVS     r0,#0
;;;1971   }
0000a8  bdf0              POP      {r4-r7,pc}
;;;1972   
                          ENDP

0000aa  0000              DCW      0x0000
                  |L36.172|
                          DCD      0x50000040

                          AREA ||i.DrvGPIO_InitSPI2||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitSPI2 PROC
;;;1991   /*---------------------------------------------------------------------------------------------------------*/
;;;1992   int32_t DrvGPIO_InitSPI2(STR_GPIO_SPI2_T *SPIFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1993   {
;;;1994   	uint32_t offset, value, shift;
;;;1995   
;;;1996   	/* clk */
;;;1997   	offset = (SPIFun->clk & 0xff000000) >> 24;
000002  6802              LDR      r2,[r0,#0]
;;;1998   	shift  = (SPIFun->clk & 0x00ff0000) >> 16;
;;;1999   	value  = (SPIFun->clk & 0xff) << shift;
;;;2000   
;;;2001   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000004  2505              MOVS     r5,#5
000006  0e13              LSRS     r3,r2,#24             ;1997
000008  0c11              LSRS     r1,r2,#16             ;1998
00000a  b2d2              UXTB     r2,r2                 ;1999
00000c  408a              LSLS     r2,r2,r1              ;1999
00000e  072d              LSLS     r5,r5,#28
000010  195b              ADDS     r3,r3,r5
000012  681f              LDR      r7,[r3,#0]
000014  240f              MOVS     r4,#0xf
000016  4626              MOV      r6,r4
000018  408e              LSLS     r6,r6,r1
00001a  43b7              BICS     r7,r7,r6
00001c  4317              ORRS     r7,r7,r2
00001e  601f              STR      r7,[r3,#0]
;;;2002   
;;;2003   	/* ss0 */
;;;2004   	offset = (SPIFun->ss0 & 0xff000000) >> 24;
000020  6841              LDR      r1,[r0,#4]
000022  0e0b              LSRS     r3,r1,#24
;;;2005   	shift  = (SPIFun->ss0 & 0x00ff0000) >> 16;
000024  020a              LSLS     r2,r1,#8
000026  0e12              LSRS     r2,r2,#24
;;;2006   	value  = (SPIFun->ss0 & 0xff) << shift;
000028  b2c9              UXTB     r1,r1
00002a  4091              LSLS     r1,r1,r2
;;;2007   
;;;2008   	if (value)
00002c  d006              BEQ      |L37.60|
;;;2009   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00002e  195b              ADDS     r3,r3,r5
000030  681e              LDR      r6,[r3,#0]
000032  4627              MOV      r7,r4
000034  4097              LSLS     r7,r7,r2
000036  43be              BICS     r6,r6,r7
000038  430e              ORRS     r6,r6,r1
00003a  601e              STR      r6,[r3,#0]
                  |L37.60|
;;;2010   
;;;2011   	if (SPIFun->ss1 == 1)   /* GPB14 */
00003c  7a01              LDRB     r1,[r0,#8]
00003e  2901              CMP      r1,#1
000040  d107              BNE      |L37.82|
;;;2012   		GCR->PB_H_MFP_BITS.PB14 = 0x4;
000042  6be9              LDR      r1,[r5,#0x3c]
000044  2207              MOVS     r2,#7
000046  0612              LSLS     r2,r2,#24
000048  4391              BICS     r1,r1,r2
00004a  2201              MOVS     r2,#1
00004c  0692              LSLS     r2,r2,#26
00004e  1889              ADDS     r1,r1,r2
000050  63e9              STR      r1,[r5,#0x3c]
                  |L37.82|
;;;2013   
;;;2014   	/* miso0 */
;;;2015   	offset = (SPIFun->miso0 & 0xff000000) >> 24;
000052  68c1              LDR      r1,[r0,#0xc]
000054  0e0a              LSRS     r2,r1,#24
;;;2016   	shift  = (SPIFun->miso0 & 0x00ff0000) >> 16;
000056  0c0b              LSRS     r3,r1,#16
;;;2017   	value  = (SPIFun->miso0 & 0xff) << shift;
000058  b2c9              UXTB     r1,r1
00005a  4099              LSLS     r1,r1,r3
;;;2018   
;;;2019   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00005c  1952              ADDS     r2,r2,r5
00005e  6816              LDR      r6,[r2,#0]
000060  4627              MOV      r7,r4
000062  409f              LSLS     r7,r7,r3
000064  43be              BICS     r6,r6,r7
000066  430e              ORRS     r6,r6,r1
000068  6016              STR      r6,[r2,#0]
;;;2020   
;;;2021   	/* mosi0 */
;;;2022   	offset = (SPIFun->mosi0 & 0xff000000) >> 24;
00006a  6902              LDR      r2,[r0,#0x10]
00006c  0e13              LSRS     r3,r2,#24
;;;2023   	shift  = (SPIFun->mosi0 & 0x00ff0000) >> 16;
00006e  0c11              LSRS     r1,r2,#16
;;;2024   	value  = (SPIFun->mosi0 & 0xff) << shift;
000070  b2d2              UXTB     r2,r2
000072  408a              LSLS     r2,r2,r1
;;;2025   
;;;2026   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000074  195b              ADDS     r3,r3,r5
000076  681d              LDR      r5,[r3,#0]
000078  408c              LSLS     r4,r4,r1
00007a  43a5              BICS     r5,r5,r4
00007c  4315              ORRS     r5,r5,r2
00007e  601d              STR      r5,[r3,#0]
;;;2027   
;;;2028   	if (SPIFun->miso1 == 1) /* GPD4 */
000080  7d02              LDRB     r2,[r0,#0x14]
;;;2029   		GCR->PD_L_MFP_BITS.PD4 = 0x3;
000082  490c              LDR      r1,|L37.180|
000084  2a01              CMP      r2,#1                 ;2028
000086  d107              BNE      |L37.152|
000088  688a              LDR      r2,[r1,#8]
00008a  2307              MOVS     r3,#7
00008c  041b              LSLS     r3,r3,#16
00008e  439a              BICS     r2,r2,r3
000090  2303              MOVS     r3,#3
000092  041b              LSLS     r3,r3,#16
000094  18d2              ADDS     r2,r2,r3
000096  608a              STR      r2,[r1,#8]
                  |L37.152|
;;;2030   
;;;2031   	if (SPIFun->mosi1 == 1) /* GPD5 */
000098  7d40              LDRB     r0,[r0,#0x15]
00009a  2801              CMP      r0,#1
00009c  d107              BNE      |L37.174|
;;;2032   		GCR->PD_L_MFP_BITS.PD5 = 0x3;
00009e  6888              LDR      r0,[r1,#8]
0000a0  2207              MOVS     r2,#7
0000a2  0512              LSLS     r2,r2,#20
0000a4  4390              BICS     r0,r0,r2
0000a6  2203              MOVS     r2,#3
0000a8  0512              LSLS     r2,r2,#20
0000aa  1880              ADDS     r0,r0,r2
0000ac  6088              STR      r0,[r1,#8]
                  |L37.174|
;;;2033   
;;;2034   	return E_SUCCESS;
0000ae  2000              MOVS     r0,#0
;;;2035   }
0000b0  bdf0              POP      {r4-r7,pc}
;;;2036   
                          ENDP

0000b2  0000              DCW      0x0000
                  |L37.180|
                          DCD      0x50000040

                          AREA ||i.DrvGPIO_InitSmartCard||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitSmartCard PROC
;;;1377   /*---------------------------------------------------------------------------------------------------------*/
;;;1378   int32_t DrvGPIO_InitSmartCard(STR_GPIO_SC_T *SCFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1379   {
;;;1380   	uint32_t offset, value, shift;
;;;1381   
;;;1382   	/* power */
;;;1383   	offset = (SCFun->power & 0xff000000) >> 24;
000002  6802              LDR      r2,[r0,#0]
000004  0e11              LSRS     r1,r2,#24
;;;1384   	shift  = (SCFun->power & 0x00ff0000) >> 16;
000006  0c13              LSRS     r3,r2,#16
;;;1385   	value  = (SCFun->power & 0xff) << shift;
000008  b2d4              UXTB     r4,r2
00000a  409c              LSLS     r4,r4,r3
;;;1386   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00000c  2205              MOVS     r2,#5
00000e  0712              LSLS     r2,r2,#28
000010  188d              ADDS     r5,r1,r2
000012  682f              LDR      r7,[r5,#0]
000014  210f              MOVS     r1,#0xf
000016  460e              MOV      r6,r1
000018  409e              LSLS     r6,r6,r3
00001a  43b7              BICS     r7,r7,r6
00001c  4327              ORRS     r7,r7,r4
00001e  602f              STR      r7,[r5,#0]
;;;1387   
;;;1388   	/* reset */
;;;1389   	offset = (SCFun->reset & 0xff000000) >> 24;
000020  6844              LDR      r4,[r0,#4]
000022  0e25              LSRS     r5,r4,#24
;;;1390   	shift  = (SCFun->reset & 0x00ff0000) >> 16;
000024  0c23              LSRS     r3,r4,#16
;;;1391   	value  = (SCFun->reset & 0xff) << shift;
000026  b2e4              UXTB     r4,r4
000028  409c              LSLS     r4,r4,r3
;;;1392   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00002a  18ad              ADDS     r5,r5,r2
00002c  682f              LDR      r7,[r5,#0]
00002e  460e              MOV      r6,r1
000030  409e              LSLS     r6,r6,r3
000032  43b7              BICS     r7,r7,r6
000034  4327              ORRS     r7,r7,r4
000036  602f              STR      r7,[r5,#0]
;;;1393   
;;;1394   	/* data */
;;;1395   	offset = (SCFun->data & 0xff000000) >> 24;
000038  6884              LDR      r4,[r0,#8]
00003a  0e25              LSRS     r5,r4,#24
;;;1396   	shift  = (SCFun->data & 0x00ff0000) >> 16;
00003c  0c23              LSRS     r3,r4,#16
;;;1397   	value  = (SCFun->data & 0xff) << shift;
00003e  b2e4              UXTB     r4,r4
000040  409c              LSLS     r4,r4,r3
;;;1398   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000042  18ad              ADDS     r5,r5,r2
000044  682f              LDR      r7,[r5,#0]
000046  460e              MOV      r6,r1
000048  409e              LSLS     r6,r6,r3
00004a  43b7              BICS     r7,r7,r6
00004c  4327              ORRS     r7,r7,r4
00004e  602f              STR      r7,[r5,#0]
;;;1399   
;;;1400   	/* clock */
;;;1401   	offset = (SCFun->clock & 0xff000000) >> 24;
000050  68c4              LDR      r4,[r0,#0xc]
000052  0e25              LSRS     r5,r4,#24
;;;1402   	shift  = (SCFun->clock & 0x00ff0000) >> 16;
000054  0c23              LSRS     r3,r4,#16
;;;1403   	value  = (SCFun->clock & 0xff) << shift;
000056  b2e4              UXTB     r4,r4
000058  409c              LSLS     r4,r4,r3
;;;1404   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00005a  18ad              ADDS     r5,r5,r2
00005c  682f              LDR      r7,[r5,#0]
00005e  460e              MOV      r6,r1
000060  409e              LSLS     r6,r6,r3
000062  43b7              BICS     r7,r7,r6
000064  4327              ORRS     r7,r7,r4
000066  602f              STR      r7,[r5,#0]
;;;1405   
;;;1406   	/* card_detect */
;;;1407   	offset = (SCFun->card_detect & 0xff000000) >> 24;
000068  6903              LDR      r3,[r0,#0x10]
00006a  0e1c              LSRS     r4,r3,#24
;;;1408   	shift  = (SCFun->card_detect & 0x00ff0000) >> 16;
00006c  0c18              LSRS     r0,r3,#16
;;;1409   	value  = (SCFun->card_detect & 0xff) << shift;
00006e  b2db              UXTB     r3,r3
000070  4083              LSLS     r3,r3,r0
;;;1410   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000072  18a2              ADDS     r2,r4,r2
000074  6814              LDR      r4,[r2,#0]
000076  4081              LSLS     r1,r1,r0
000078  438c              BICS     r4,r4,r1
00007a  431c              ORRS     r4,r4,r3
00007c  6014              STR      r4,[r2,#0]
;;;1411   
;;;1412   	return E_SUCCESS;
00007e  2000              MOVS     r0,#0
;;;1413   }
000080  bdf0              POP      {r4-r7,pc}
;;;1414   
                          ENDP


                          AREA ||i.DrvGPIO_InitSmartCard0||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitSmartCard0 PROC
;;;1309   /*---------------------------------------------------------------------------------------------------------*/
;;;1310   int32_t DrvGPIO_InitSmartCard0(void)
000000  2005              MOVS     r0,#5
;;;1311   {
;;;1312   	GCR->PA_H_MFP &= ~0xffff;
000002  0700              LSLS     r0,r0,#28
000004  6b41              LDR      r1,[r0,#0x34]
000006  0c09              LSRS     r1,r1,#16
000008  0409              LSLS     r1,r1,#16
00000a  6341              STR      r1,[r0,#0x34]
;;;1313   	GCR->PA_H_MFP |= 0x3333;
00000c  6b41              LDR      r1,[r0,#0x34]
00000e  4a06              LDR      r2,|L39.40|
000010  4311              ORRS     r1,r1,r2
000012  6341              STR      r1,[r0,#0x34]
;;;1314   	GCR->PB_L_MFP_BITS.PB4 = 0x3;   // card detection
000014  6b81              LDR      r1,[r0,#0x38]
000016  2207              MOVS     r2,#7
000018  0412              LSLS     r2,r2,#16
00001a  4391              BICS     r1,r1,r2
00001c  2203              MOVS     r2,#3
00001e  0412              LSLS     r2,r2,#16
000020  1889              ADDS     r1,r1,r2
000022  6381              STR      r1,[r0,#0x38]
;;;1315   
;;;1316   	return E_SUCCESS;
000024  2000              MOVS     r0,#0
;;;1317   }
000026  4770              BX       lr
;;;1318   
                          ENDP

                  |L39.40|
                          DCD      0x00003333

                          AREA ||i.DrvGPIO_InitSmartCard1||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitSmartCard1 PROC
;;;1333   /*---------------------------------------------------------------------------------------------------------*/
;;;1334   int32_t DrvGPIO_InitSmartCard1(E_DRVGPIO_SC1 port)
000000  490c              LDR      r1,|L40.52|
;;;1335   {
;;;1336   	if (port == E_SC1_PORTC)
000002  2800              CMP      r0,#0
000004  d003              BEQ      |L40.14|
;;;1337   	{
;;;1338   		GCR->PC_L_MFP &= ~0xf00ffff;
;;;1339   		GCR->PC_L_MFP |= 0x4004444;
;;;1340   	}
;;;1341   	else if (port == E_SC1_PORTD)
000006  2801              CMP      r0,#1
000008  d00a              BEQ      |L40.32|
;;;1342   	{
;;;1343   		GCR->PD_L_MFP &= ~0xfffff;
;;;1344   		GCR->PD_L_MFP |= 0x44444;
;;;1345   	}
;;;1346   	else
;;;1347   		return E_DRVGPIO_ARGUMENT;
00000a  480b              LDR      r0,|L40.56|
;;;1348   
;;;1349   	return E_SUCCESS;
;;;1350   }
00000c  4770              BX       lr
                  |L40.14|
00000e  6808              LDR      r0,[r1,#0]            ;1338
000010  4a0a              LDR      r2,|L40.60|
000012  4010              ANDS     r0,r0,r2              ;1338
000014  6008              STR      r0,[r1,#0]            ;1338
000016  6808              LDR      r0,[r1,#0]            ;1339
000018  4a09              LDR      r2,|L40.64|
00001a  4310              ORRS     r0,r0,r2              ;1339
00001c  6008              STR      r0,[r1,#0]            ;1339
00001e  e007              B        |L40.48|
                  |L40.32|
000020  6888              LDR      r0,[r1,#8]            ;1343
000022  0d00              LSRS     r0,r0,#20             ;1343
000024  0500              LSLS     r0,r0,#20             ;1343
000026  6088              STR      r0,[r1,#8]            ;1343
000028  6888              LDR      r0,[r1,#8]            ;1344
00002a  4a06              LDR      r2,|L40.68|
00002c  4310              ORRS     r0,r0,r2              ;1344
00002e  6088              STR      r0,[r1,#8]            ;1344
                  |L40.48|
000030  2000              MOVS     r0,#0                 ;1349
000032  4770              BX       lr
;;;1351   
                          ENDP

                  |L40.52|
                          DCD      0x50000040
                  |L40.56|
                          DCD      0xffff8901
                  |L40.60|
                          DCD      0xf0ff0000
                  |L40.64|
                          DCD      0x04004444
                  |L40.68|
                          DCD      0x00044444

                          AREA ||i.DrvGPIO_InitTimerCapture||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitTimerCapture PROC
;;;1661   /*---------------------------------------------------------------------------------------------------------*/
;;;1662   int32_t DrvGPIO_InitTimerCapture(E_DRVGPIO_TMRCAP tcNo)
000000  0e03              LSRS     r3,r0,#24
;;;1663   {
;;;1664   	uint32_t offset, value, shift;
;;;1665   
;;;1666   	offset = (tcNo & 0xff000000) >> 24;
;;;1667   	shift  = (tcNo & 0x00ff0000) >> 16;
000002  0c01              LSRS     r1,r0,#16
;;;1668   	value  = (tcNo & 0xff) << shift;
000004  b2c2              UXTB     r2,r0
000006  408a              LSLS     r2,r2,r1
;;;1669   
;;;1670   	outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000008  2005              MOVS     r0,#5
00000a  b510              PUSH     {r4,lr}               ;1663
00000c  0700              LSLS     r0,r0,#28
00000e  1818              ADDS     r0,r3,r0
000010  6803              LDR      r3,[r0,#0]
000012  240f              MOVS     r4,#0xf
000014  408c              LSLS     r4,r4,r1
000016  43a3              BICS     r3,r3,r4
000018  4313              ORRS     r3,r3,r2
00001a  6003              STR      r3,[r0,#0]
;;;1671   
;;;1672   	return E_SUCCESS;
00001c  2000              MOVS     r0,#0
;;;1673   }
00001e  bd10              POP      {r4,pc}
;;;1674   
                          ENDP


                          AREA ||i.DrvGPIO_InitTouchKey||, CODE, READONLY, ALIGN=2

                  DrvGPIO_InitTouchKey PROC
;;;1603   /*---------------------------------------------------------------------------------------------------------*/
;;;1604   int32_t DrvGPIO_InitTouchKey(uint32_t cap, uint16_t KeyMask)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1605   {
;;;1606   	if (cap == 1)
;;;1607   		GCR->PA_L_MFP_BITS.PA7 = 0x4;
000002  2205              MOVS     r2,#5
000004  0712              LSLS     r2,r2,#28
000006  2801              CMP      r0,#1                 ;1606
000008  d106              BNE      |L42.24|
00000a  6b10              LDR      r0,[r2,#0x30]
00000c  2307              MOVS     r3,#7
00000e  071b              LSLS     r3,r3,#28
000010  4398              BICS     r0,r0,r3
000012  0093              LSLS     r3,r2,#2
000014  18c0              ADDS     r0,r0,r3
000016  6310              STR      r0,[r2,#0x30]
                  |L42.24|
;;;1608   
;;;1609   	if ((KeyMask & 0xffff) == 0x0001)   // key 0
;;;1610   		GCR->PD_L_MFP_BITS.PD0 = 0x6;
000018  4849              LDR      r0,|L42.320|
00001a  2901              CMP      r1,#1                 ;1609
00001c  d05f              BEQ      |L42.222|
;;;1611   	if ((KeyMask & 0xffff) == 0x0002)   // key 1
;;;1612   		GCR->PD_L_MFP_BITS.PD1 = 0x6;
00001e  2370              MOVS     r3,#0x70
000020  2902              CMP      r1,#2                 ;1611
000022  d061              BEQ      |L42.232|
;;;1613   	if ((KeyMask & 0xffff) == 0x0004)   // key 2
000024  2904              CMP      r1,#4
000026  d063              BEQ      |L42.240|
;;;1614   		GCR->PD_L_MFP_BITS.PD2 = 0x6;
;;;1615   	if ((KeyMask & 0xffff) == 0x0008)   // key 3
000028  2908              CMP      r1,#8
00002a  d069              BEQ      |L42.256|
;;;1616   		GCR->PD_L_MFP_BITS.PD3 = 0x6;
;;;1617   	if ((KeyMask & 0xffff) == 0x0010)   // key 4
;;;1618   		GCR->PD_L_MFP_BITS.PD4 = 0x6;
00002c  2403              MOVS     r4,#3
00002e  031f              LSLS     r7,r3,#12
000030  0464              LSLS     r4,r4,#17
000032  2910              CMP      r1,#0x10              ;1617
000034  d06b              BEQ      |L42.270|
;;;1619   	if ((KeyMask & 0xffff) == 0x0020)   // key 5
;;;1620   		GCR->PD_L_MFP_BITS.PD5 = 0x6;
000036  041d              LSLS     r5,r3,#16
000038  2920              CMP      r1,#0x20              ;1619
00003a  d06c              BEQ      |L42.278|
;;;1621   	if ((KeyMask & 0xffff) == 0x0040)   // key 6
00003c  2940              CMP      r1,#0x40
00003e  d073              BEQ      |L42.296|
;;;1622   		GCR->PF_L_MFP_BITS.PF4 = 0x6;
;;;1623   	if ((KeyMask & 0xffff) == 0x0080)   // key 7
000040  2980              CMP      r1,#0x80
000042  d075              BEQ      |L42.304|
;;;1624   		GCR->PF_L_MFP_BITS.PF5 = 0x6;
;;;1625   	if ((KeyMask & 0xffff) == 0x0100)   // key 8
000044  1fce              SUBS     r6,r1,#7
000046  3ef9              SUBS     r6,r6,#0xf9
000048  d104              BNE      |L42.84|
;;;1626   		GCR->PA_L_MFP_BITS.PA0 = 0x6;
00004a  6b16              LDR      r6,[r2,#0x30]
00004c  08f6              LSRS     r6,r6,#3
00004e  00f6              LSLS     r6,r6,#3
000050  1db6              ADDS     r6,r6,#6
000052  6316              STR      r6,[r2,#0x30]
                  |L42.84|
;;;1627   	if ((KeyMask & 0xffff) == 0x0200)   // key 9
000054  1fce              SUBS     r6,r1,#7
000056  3eff              SUBS     r6,r6,#0xff
000058  3efa              SUBS     r6,r6,#0xfa
00005a  d103              BNE      |L42.100|
;;;1628   		GCR->PA_L_MFP_BITS.PA1 = 0x6;
00005c  6b16              LDR      r6,[r2,#0x30]
00005e  439e              BICS     r6,r6,r3
000060  3660              ADDS     r6,r6,#0x60
000062  6316              STR      r6,[r2,#0x30]
                  |L42.100|
;;;1629   	if ((KeyMask & 0xffff) == 0x0400)   // key 10
000064  2601              MOVS     r6,#1
000066  02b6              LSLS     r6,r6,#10
000068  42b1              CMP      r1,r6
00006a  d103              BNE      |L42.116|
;;;1630   		GCR->PA_H_MFP_BITS.PA12 = 0x6;
00006c  6b56              LDR      r6,[r2,#0x34]
00006e  43be              BICS     r6,r6,r7
000070  1934              ADDS     r4,r6,r4
000072  6354              STR      r4,[r2,#0x34]
                  |L42.116|
;;;1631   	if ((KeyMask & 0xffff) == 0x0800)   // key 11
000074  2401              MOVS     r4,#1
000076  02e4              LSLS     r4,r4,#11
000078  42a1              CMP      r1,r4
00007a  d105              BNE      |L42.136|
;;;1632   		GCR->PA_H_MFP_BITS.PA13 = 0x6;
00007c  6b54              LDR      r4,[r2,#0x34]
00007e  43ac              BICS     r4,r4,r5
000080  2503              MOVS     r5,#3
000082  056d              LSLS     r5,r5,#21
000084  1964              ADDS     r4,r4,r5
000086  6354              STR      r4,[r2,#0x34]
                  |L42.136|
;;;1633   	if ((KeyMask & 0xffff) == 0x1000)   // key 12
000088  2201              MOVS     r2,#1
00008a  0312              LSLS     r2,r2,#12
00008c  4291              CMP      r1,r2
00008e  d104              BNE      |L42.154|
;;;1634   		GCR->PC_H_MFP_BITS.PC8 = 0x6;
000090  6842              LDR      r2,[r0,#4]
000092  08d2              LSRS     r2,r2,#3
000094  00d2              LSLS     r2,r2,#3
000096  1d92              ADDS     r2,r2,#6
000098  6042              STR      r2,[r0,#4]
                  |L42.154|
;;;1635   	if ((KeyMask & 0xffff) == 0x2000)   // key 13
00009a  2201              MOVS     r2,#1
00009c  0352              LSLS     r2,r2,#13
00009e  4291              CMP      r1,r2
0000a0  d103              BNE      |L42.170|
;;;1636   		GCR->PC_H_MFP_BITS.PC9 = 0x6;
0000a2  6842              LDR      r2,[r0,#4]
0000a4  439a              BICS     r2,r2,r3
0000a6  3260              ADDS     r2,r2,#0x60
0000a8  6042              STR      r2,[r0,#4]
                  |L42.170|
;;;1637   	if ((KeyMask & 0xffff) == 0x4000)   // key 14
0000aa  2201              MOVS     r2,#1
0000ac  0392              LSLS     r2,r2,#14
0000ae  4291              CMP      r1,r2
0000b0  d107              BNE      |L42.194|
;;;1638   		GCR->PC_H_MFP_BITS.PC10 = 0x6;
0000b2  6843              LDR      r3,[r0,#4]
0000b4  2207              MOVS     r2,#7
0000b6  0212              LSLS     r2,r2,#8
0000b8  4393              BICS     r3,r3,r2
0000ba  2203              MOVS     r2,#3
0000bc  0252              LSLS     r2,r2,#9
0000be  189a              ADDS     r2,r3,r2
0000c0  6042              STR      r2,[r0,#4]
                  |L42.194|
;;;1639   	if ((KeyMask & 0xffff) == 0x8000)   // key 15
0000c2  2201              MOVS     r2,#1
0000c4  03d2              LSLS     r2,r2,#15
0000c6  4291              CMP      r1,r2
0000c8  d107              BNE      |L42.218|
;;;1640   		GCR->PC_H_MFP_BITS.PC11 = 0x6;
0000ca  6842              LDR      r2,[r0,#4]
0000cc  2107              MOVS     r1,#7
0000ce  0309              LSLS     r1,r1,#12
0000d0  438a              BICS     r2,r2,r1
0000d2  2103              MOVS     r1,#3
0000d4  0349              LSLS     r1,r1,#13
0000d6  1851              ADDS     r1,r2,r1
0000d8  6041              STR      r1,[r0,#4]
                  |L42.218|
;;;1641   
;;;1642   	return E_SUCCESS;
0000da  2000              MOVS     r0,#0
;;;1643   }
0000dc  bdf0              POP      {r4-r7,pc}
                  |L42.222|
0000de  6881              LDR      r1,[r0,#8]            ;1610
0000e0  08c9              LSRS     r1,r1,#3              ;1610
0000e2  00c9              LSLS     r1,r1,#3              ;1610
0000e4  1d89              ADDS     r1,r1,#6              ;1610
0000e6  e01b              B        |L42.288|
                  |L42.232|
0000e8  6881              LDR      r1,[r0,#8]            ;1612
0000ea  4399              BICS     r1,r1,r3              ;1612
0000ec  3160              ADDS     r1,r1,#0x60           ;1612
0000ee  e017              B        |L42.288|
                  |L42.240|
0000f0  6882              LDR      r2,[r0,#8]            ;1614
0000f2  2107              MOVS     r1,#7                 ;1614
0000f4  0209              LSLS     r1,r1,#8              ;1614
0000f6  438a              BICS     r2,r2,r1              ;1614
0000f8  2103              MOVS     r1,#3                 ;1614
0000fa  0249              LSLS     r1,r1,#9              ;1614
0000fc  1851              ADDS     r1,r2,r1              ;1614
0000fe  e00f              B        |L42.288|
                  |L42.256|
000100  6881              LDR      r1,[r0,#8]            ;1616
000102  2207              MOVS     r2,#7                 ;1616
000104  0312              LSLS     r2,r2,#12             ;1616
000106  4391              BICS     r1,r1,r2              ;1616
000108  2203              MOVS     r2,#3                 ;1616
00010a  0352              LSLS     r2,r2,#13             ;1616
00010c  e007              B        |L42.286|
                  |L42.270|
00010e  6881              LDR      r1,[r0,#8]            ;1618
000110  43b9              BICS     r1,r1,r7              ;1618
000112  1909              ADDS     r1,r1,r4              ;1618
000114  e004              B        |L42.288|
                  |L42.278|
000116  6881              LDR      r1,[r0,#8]            ;1620
000118  2203              MOVS     r2,#3                 ;1620
00011a  43a9              BICS     r1,r1,r5              ;1620
00011c  0552              LSLS     r2,r2,#21             ;1620
                  |L42.286|
00011e  1889              ADDS     r1,r1,r2              ;1620
                  |L42.288|
000120  6081              STR      r1,[r0,#8]            ;1620
000122  e7da              B        |L42.218|
000124  e000              B        |L42.296|
000126  e003              B        |L42.304|
                  |L42.296|
000128  6981              LDR      r1,[r0,#0x18]         ;1622
00012a  43b9              BICS     r1,r1,r7              ;1622
00012c  1909              ADDS     r1,r1,r4              ;1622
00012e  e004              B        |L42.314|
                  |L42.304|
000130  6981              LDR      r1,[r0,#0x18]         ;1624
000132  2203              MOVS     r2,#3                 ;1624
000134  43a9              BICS     r1,r1,r5              ;1624
000136  0552              LSLS     r2,r2,#21             ;1624
000138  1889              ADDS     r1,r1,r2              ;1624
                  |L42.314|
00013a  6181              STR      r1,[r0,#0x18]         ;1624
00013c  e7cd              B        |L42.218|
;;;1644   
                          ENDP

00013e  0000              DCW      0x0000
                  |L42.320|
                          DCD      0x50000040

                          AREA ||i.DrvGPIO_InitUART0||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitUART0 PROC
;;;2052   /*---------------------------------------------------------------------------------------------------------*/
;;;2053   int32_t DrvGPIO_InitUART0(STR_GPIO_UART0_T *uartFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;2054   {
;;;2055   	uint32_t offset, value, shift;
;;;2056   
;;;2057   	/* rx */
;;;2058   	offset = (uartFun->rx & 0xff000000) >> 24;
000002  6801              LDR      r1,[r0,#0]
;;;2059   	shift  = (uartFun->rx & 0x00ff0000) >> 16;
;;;2060   	value  = (uartFun->rx & 0xff) << shift;
;;;2061   
;;;2062   	if (value)
;;;2063   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000004  2305              MOVS     r3,#5
000006  0e0d              LSRS     r5,r1,#24             ;2058
000008  020a              LSLS     r2,r1,#8              ;2059
00000a  0e12              LSRS     r2,r2,#24             ;2059
00000c  b2c9              UXTB     r1,r1                 ;2060
00000e  4091              LSLS     r1,r1,r2              ;2060
000010  071b              LSLS     r3,r3,#28
000012  240f              MOVS     r4,#0xf
000014  2900              CMP      r1,#0                 ;2062
000016  d006              BEQ      |L43.38|
000018  18ed              ADDS     r5,r5,r3
00001a  682e              LDR      r6,[r5,#0]
00001c  4627              MOV      r7,r4
00001e  4097              LSLS     r7,r7,r2
000020  43be              BICS     r6,r6,r7
000022  430e              ORRS     r6,r6,r1
000024  602e              STR      r6,[r5,#0]
                  |L43.38|
;;;2064   
;;;2065   	/* tx */
;;;2066   	offset = (uartFun->tx & 0xff000000) >> 24;
000026  6841              LDR      r1,[r0,#4]
000028  0e0d              LSRS     r5,r1,#24
;;;2067   	shift  = (uartFun->tx & 0x00ff0000) >> 16;
00002a  020a              LSLS     r2,r1,#8
00002c  0e12              LSRS     r2,r2,#24
;;;2068   	value  = (uartFun->tx & 0xff) << shift;
00002e  b2c9              UXTB     r1,r1
000030  4091              LSLS     r1,r1,r2
;;;2069   
;;;2070   	if (value)
000032  d006              BEQ      |L43.66|
;;;2071   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000034  18ed              ADDS     r5,r5,r3
000036  682e              LDR      r6,[r5,#0]
000038  4627              MOV      r7,r4
00003a  4097              LSLS     r7,r7,r2
00003c  43be              BICS     r6,r6,r7
00003e  430e              ORRS     r6,r6,r1
000040  602e              STR      r6,[r5,#0]
                  |L43.66|
;;;2072   
;;;2073   	/* rts */
;;;2074   	offset = (uartFun->rts & 0xff000000) >> 24;
000042  6881              LDR      r1,[r0,#8]
000044  0e0d              LSRS     r5,r1,#24
;;;2075   	shift  = (uartFun->rts & 0x00ff0000) >> 16;
000046  020a              LSLS     r2,r1,#8
000048  0e12              LSRS     r2,r2,#24
;;;2076   	value  = (uartFun->rts & 0xff) << shift;
00004a  b2c9              UXTB     r1,r1
00004c  4091              LSLS     r1,r1,r2
;;;2077   
;;;2078   	if (value)
00004e  d006              BEQ      |L43.94|
;;;2079   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000050  18ed              ADDS     r5,r5,r3
000052  682e              LDR      r6,[r5,#0]
000054  4627              MOV      r7,r4
000056  4097              LSLS     r7,r7,r2
000058  43be              BICS     r6,r6,r7
00005a  430e              ORRS     r6,r6,r1
00005c  602e              STR      r6,[r5,#0]
                  |L43.94|
;;;2080   
;;;2081   	/* cts */
;;;2082   	offset = (uartFun->cts & 0xff000000) >> 24;
00005e  68c0              LDR      r0,[r0,#0xc]
000060  0e02              LSRS     r2,r0,#24
;;;2083   	shift  = (uartFun->cts & 0x00ff0000) >> 16;
000062  0201              LSLS     r1,r0,#8
000064  0e09              LSRS     r1,r1,#24
;;;2084   	value  = (uartFun->cts & 0xff) << shift;
000066  b2c0              UXTB     r0,r0
000068  4088              LSLS     r0,r0,r1
;;;2085   
;;;2086   	if (value)
00006a  d005              BEQ      |L43.120|
;;;2087   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00006c  18d2              ADDS     r2,r2,r3
00006e  6813              LDR      r3,[r2,#0]
000070  408c              LSLS     r4,r4,r1
000072  43a3              BICS     r3,r3,r4
000074  4303              ORRS     r3,r3,r0
000076  6013              STR      r3,[r2,#0]
                  |L43.120|
;;;2088   
;;;2089   	return E_SUCCESS;
000078  2000              MOVS     r0,#0
;;;2090   }
00007a  bdf0              POP      {r4-r7,pc}
;;;2091   
                          ENDP


                          AREA ||i.DrvGPIO_InitUART1||, CODE, READONLY, ALIGN=1

                  DrvGPIO_InitUART1 PROC
;;;2112   /*---------------------------------------------------------------------------------------------------------*/
;;;2113   int32_t DrvGPIO_InitUART1(STR_GPIO_UART1_T *uartFun)
000000  b5f0              PUSH     {r4-r7,lr}
;;;2114   {
;;;2115   	uint32_t offset, value, shift;
;;;2116   
;;;2117   	/* rx */
;;;2118   	offset = (uartFun->rx & 0xff000000) >> 24;
000002  6801              LDR      r1,[r0,#0]
;;;2119   	shift  = (uartFun->rx & 0x00ff0000) >> 16;
;;;2120   	value  = (uartFun->rx & 0xff) << shift;
;;;2121   
;;;2122   	if (value)
;;;2123   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000004  2305              MOVS     r3,#5
000006  0e0d              LSRS     r5,r1,#24             ;2118
000008  020a              LSLS     r2,r1,#8              ;2119
00000a  0e12              LSRS     r2,r2,#24             ;2119
00000c  b2c9              UXTB     r1,r1                 ;2120
00000e  4091              LSLS     r1,r1,r2              ;2120
000010  071b              LSLS     r3,r3,#28
000012  240f              MOVS     r4,#0xf
000014  2900              CMP      r1,#0                 ;2122
000016  d006              BEQ      |L44.38|
000018  18ed              ADDS     r5,r5,r3
00001a  682e              LDR      r6,[r5,#0]
00001c  4627              MOV      r7,r4
00001e  4097              LSLS     r7,r7,r2
000020  43be              BICS     r6,r6,r7
000022  430e              ORRS     r6,r6,r1
000024  602e              STR      r6,[r5,#0]
                  |L44.38|
;;;2124   
;;;2125   	/* tx */
;;;2126   	offset = (uartFun->tx & 0xff000000) >> 24;
000026  6841              LDR      r1,[r0,#4]
000028  0e0d              LSRS     r5,r1,#24
;;;2127   	shift  = (uartFun->tx & 0x00ff0000) >> 16;
00002a  020a              LSLS     r2,r1,#8
00002c  0e12              LSRS     r2,r2,#24
;;;2128   	value  = (uartFun->tx & 0xff) << shift;
00002e  b2c9              UXTB     r1,r1
000030  4091              LSLS     r1,r1,r2
;;;2129   
;;;2130   	if (value)
000032  d006              BEQ      |L44.66|
;;;2131   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000034  18ed              ADDS     r5,r5,r3
000036  682e              LDR      r6,[r5,#0]
000038  4627              MOV      r7,r4
00003a  4097              LSLS     r7,r7,r2
00003c  43be              BICS     r6,r6,r7
00003e  430e              ORRS     r6,r6,r1
000040  602e              STR      r6,[r5,#0]
                  |L44.66|
;;;2132   
;;;2133   	/* rts */
;;;2134   	offset = (uartFun->rts & 0xff000000) >> 24;
000042  6881              LDR      r1,[r0,#8]
000044  0e0d              LSRS     r5,r1,#24
;;;2135   	shift  = (uartFun->rts & 0x00ff0000) >> 16;
000046  020a              LSLS     r2,r1,#8
000048  0e12              LSRS     r2,r2,#24
;;;2136   	value  = (uartFun->rts & 0xff) << shift;
00004a  b2c9              UXTB     r1,r1
00004c  4091              LSLS     r1,r1,r2
;;;2137   
;;;2138   	if (value)
00004e  d006              BEQ      |L44.94|
;;;2139   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
000050  18ed              ADDS     r5,r5,r3
000052  682e              LDR      r6,[r5,#0]
000054  4627              MOV      r7,r4
000056  4097              LSLS     r7,r7,r2
000058  43be              BICS     r6,r6,r7
00005a  430e              ORRS     r6,r6,r1
00005c  602e              STR      r6,[r5,#0]
                  |L44.94|
;;;2140   
;;;2141   	/* cts */
;;;2142   	offset = (uartFun->cts & 0xff000000) >> 24;
00005e  68c0              LDR      r0,[r0,#0xc]
000060  0e02              LSRS     r2,r0,#24
;;;2143   	shift  = (uartFun->cts & 0x00ff0000) >> 16;
000062  0201              LSLS     r1,r0,#8
000064  0e09              LSRS     r1,r1,#24
;;;2144   	value  = (uartFun->cts & 0xff) << shift;
000066  b2c0              UXTB     r0,r0
000068  4088              LSLS     r0,r0,r1
;;;2145   
;;;2146   	if (value)
00006a  d005              BEQ      |L44.120|
;;;2147   		outpw(GCR_BASE+offset, (inpw(GCR_BASE+offset)& ~(0xf<<shift))|value);
00006c  18d2              ADDS     r2,r2,r3
00006e  6813              LDR      r3,[r2,#0]
000070  408c              LSLS     r4,r4,r1
000072  43a3              BICS     r3,r3,r4
000074  4303              ORRS     r3,r3,r0
000076  6013              STR      r3,[r2,#0]
                  |L44.120|
;;;2148   
;;;2149   	return E_SUCCESS;
000078  2000              MOVS     r0,#0
;;;2150   }
00007a  bdf0              POP      {r4-r7,pc}
;;;2151   
                          ENDP


                          AREA ||i.DrvGPIO_Open||, CODE, READONLY, ALIGN=2

                  DrvGPIO_Open PROC
;;;118    /*---------------------------------------------------------------------------------------------------------*/
;;;119    int32_t DrvGPIO_Open(E_DRVGPIO_PORT port, int32_t i32Bit, E_DRVGPIO_IO mode)
000000  4b0a              LDR      r3,|L45.44|
;;;120    {
;;;121    	GPIO_TypeDef *base;
;;;122    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;123    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  b530              PUSH     {r4,r5,lr}            ;120
000006  18c0              ADDS     r0,r0,r3
;;;124    
;;;125    	/* enable GPIO clock */
;;;126    	CLK->AHBCLK_BITS.GPIO_EN = 1;
000008  4b09              LDR      r3,|L45.48|
00000a  685c              LDR      r4,[r3,#4]
00000c  2501              MOVS     r5,#1
00000e  432c              ORRS     r4,r4,r5
000010  605c              STR      r4,[r3,#4]
;;;127    
;;;128    	base->PMD &= ~(0x3<<(i32Bit*2));
000012  6803              LDR      r3,[r0,#0]
000014  0049              LSLS     r1,r1,#1
000016  2403              MOVS     r4,#3
000018  408c              LSLS     r4,r4,r1
00001a  43a3              BICS     r3,r3,r4
00001c  6003              STR      r3,[r0,#0]
;;;129    	base->PMD |= (mode<<(i32Bit*2));
00001e  6803              LDR      r3,[r0,#0]
000020  408a              LSLS     r2,r2,r1
000022  4313              ORRS     r3,r3,r2
000024  6003              STR      r3,[r0,#0]
;;;130    
;;;131    	return E_SUCCESS;
000026  2000              MOVS     r0,#0
;;;132    }
000028  bd30              POP      {r4,r5,pc}
;;;133    
                          ENDP

00002a  0000              DCW      0x0000
                  |L45.44|
                          DCD      0x50004000
                  |L45.48|
                          DCD      0x50000200

                          AREA ||i.DrvGPIO_SetBit||, CODE, READONLY, ALIGN=2

                  DrvGPIO_SetBit PROC
;;;176    /*---------------------------------------------------------------------------------------------------------*/
;;;177    int32_t DrvGPIO_SetBit(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a04              LDR      r2,|L46.20|
;;;178    {
;;;179    	GPIO_TypeDef *base;
;;;180    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;181    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;182    
;;;183    	base->DOUT |= (1 << i32Bit);
000006  6882              LDR      r2,[r0,#8]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  431a              ORRS     r2,r2,r3
00000e  6082              STR      r2,[r0,#8]
;;;184    
;;;185    	return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;186    }
000012  4770              BX       lr
;;;187    
                          ENDP

                  |L46.20|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_SetBitMask||, CODE, READONLY, ALIGN=2

                  DrvGPIO_SetBitMask PROC
;;;338    /*---------------------------------------------------------------------------------------------------------*/
;;;339    int32_t DrvGPIO_SetBitMask(E_DRVGPIO_PORT port, int32_t i32Bit)
000000  4a04              LDR      r2,|L47.20|
;;;340    {
;;;341    	GPIO_TypeDef *base;
;;;342    	assert_param(CHECK_GPIO_PORTPIN(port, i32Bit));
;;;343    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;344    
;;;345    	base->DMASK |= (1<<i32Bit);
000006  68c2              LDR      r2,[r0,#0xc]
000008  2301              MOVS     r3,#1
00000a  408b              LSLS     r3,r3,r1
00000c  431a              ORRS     r2,r2,r3
00000e  60c2              STR      r2,[r0,#0xc]
;;;346    
;;;347    	return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;348    }
000012  4770              BX       lr
;;;349    
                          ENDP

                  |L47.20|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_SetDebounceTime||, CODE, READONLY, ALIGN=2

                  DrvGPIO_SetDebounceTime PROC
;;;583    /*---------------------------------------------------------------------------------------------------------*/
;;;584    int32_t DrvGPIO_SetDebounceTime(uint32_t u32CycleSelection, E_DRVGPIO_DBCLKSRC ClockSource)
000000  4a08              LDR      r2,|L48.36|
;;;585    {
;;;586    	/* Maximum debounce time is 2^(15)*(clk src) */
;;;587    	assert_param(CHECK_GPIO_DEBCYCLE(u32CycleSelection));
;;;588    
;;;589    	GPIODBNCE->CON_BITS.DBCLKSEL = u32CycleSelection ;
000002  6813              LDR      r3,[r2,#0]
000004  0700              LSLS     r0,r0,#28
000006  091b              LSRS     r3,r3,#4
000008  011b              LSLS     r3,r3,#4
00000a  0f00              LSRS     r0,r0,#28
00000c  4303              ORRS     r3,r3,r0
00000e  6013              STR      r3,[r2,#0]
;;;590    
;;;591    	GPIODBNCE->CON_BITS.DBCLKSRC = ClockSource ;
000010  6810              LDR      r0,[r2,#0]
000012  2310              MOVS     r3,#0x10
000014  07c9              LSLS     r1,r1,#31
000016  4398              BICS     r0,r0,r3
000018  0ec9              LSRS     r1,r1,#27
00001a  4308              ORRS     r0,r0,r1
00001c  6010              STR      r0,[r2,#0]
;;;592    
;;;593    	return E_SUCCESS;
00001e  2000              MOVS     r0,#0
;;;594    }
000020  4770              BX       lr
;;;595    
                          ENDP

000022  0000              DCW      0x0000
                  |L48.36|
                          DCD      0x50004180

                          AREA ||i.DrvGPIO_SetIntCallback||, CODE, READONLY, ALIGN=2

                  DrvGPIO_SetIntCallback PROC
;;;728    /*---------------------------------------------------------------------------------------------------------*/
;;;729    void DrvGPIO_SetIntCallback(GPIO_GPABC_CALLBACK pfGPABCCallback, GPIO_GPDEF_CALLBACK pfGPDEFCallback)
000000  4a01              LDR      r2,|L49.8|
;;;730    {
;;;731    	_pfGPABCCallback = (void (*)(uint32_t, uint32_t, uint32_t))pfGPABCCallback;
;;;732    	_pfGPDEFCallback = (void (*)(uint32_t, uint32_t, uint32_t))pfGPDEFCallback;
000002  60d1              STR      r1,[r2,#0xc]  ; _pfGPDEFCallback
000004  6090              STR      r0,[r2,#8]  ; _pfGPABCCallback
;;;733    }
000006  4770              BX       lr
;;;734    
                          ENDP

                  |L49.8|
                          DCD      ||.data||

                          AREA ||i.DrvGPIO_SetPortBits||, CODE, READONLY, ALIGN=2

                  DrvGPIO_SetPortBits PROC
;;;246    /*---------------------------------------------------------------------------------------------------------*/
;;;247    int32_t DrvGPIO_SetPortBits(E_DRVGPIO_PORT port,int32_t i32Data)
000000  4a02              LDR      r2,|L50.12|
;;;248    {
;;;249    	GPIO_TypeDef *base;
;;;250    	assert_param(CHECK_GPIO_PORT(port));
;;;251    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;252    
;;;253    	base->DOUT = i32Data;
000006  6081              STR      r1,[r0,#8]
;;;254    
;;;255    	return E_SUCCESS;
000008  2000              MOVS     r0,#0
;;;256    }
00000a  4770              BX       lr
;;;257    
                          ENDP

                  |L50.12|
                          DCD      0x50004000

                          AREA ||i.DrvGPIO_SetPortMask||, CODE, READONLY, ALIGN=2

                  DrvGPIO_SetPortMask PROC
;;;412    /*---------------------------------------------------------------------------------------------------------*/
;;;413    int32_t DrvGPIO_SetPortMask(E_DRVGPIO_PORT port, int32_t i32MaskData)
000000  4a03              LDR      r2,|L51.16|
;;;414    {
;;;415    	GPIO_TypeDef *base;
;;;416    	assert_param(CHECK_GPIO_PORT(port));
;;;417    	base = (GPIO_TypeDef *)get_port_base(port);
000002  0180              LSLS     r0,r0,#6
000004  1880              ADDS     r0,r0,r2
;;;418    	base->DMASK |= i32MaskData;
000006  68c2              LDR      r2,[r0,#0xc]
000008  430a              ORRS     r2,r2,r1
00000a  60c2              STR      r2,[r0,#0xc]
;;;419    
;;;420    	return E_SUCCESS;
00000c  2000              MOVS     r0,#0
;;;421    }
00000e  4770              BX       lr
;;;422    
                          ENDP

                  |L51.16|
                          DCD      0x50004000

                          AREA ||i.EINT0_IRQHandler||, CODE, READONLY, ALIGN=2

                  EINT0_IRQHandler PROC
;;;38     /*---------------------------------------------------------------------------------------------------------*/
;;;39     void EINT0_IRQHandler(void)
000000  4805              LDR      r0,|L52.24|
;;;40     {
;;;41     	/* EINT0 Clear the interrupt */
;;;42     	gGPIO_EXT0_Base->ISR = 1UL << gGPIO_EXT0_Pin;
000002  2101              MOVS     r1,#1
000004  6a02              LDR      r2,[r0,#0x20]  ; gGPIO_EXT0_Pin
000006  4091              LSLS     r1,r1,r2
000008  6982              LDR      r2,[r0,#0x18]  ; gGPIO_EXT0_Base
00000a  6211              STR      r1,[r2,#0x20]
;;;43     	if ( _pfEINT0Callback )
00000c  6900              LDR      r0,[r0,#0x10]  ; _pfEINT0Callback
00000e  2800              CMP      r0,#0
000010  d000              BEQ      |L52.20|
;;;44     		_pfEINT0Callback();
000012  4700              BX       r0
                  |L52.20|
;;;45     }
000014  4770              BX       lr
;;;46     
                          ENDP

000016  0000              DCW      0x0000
                  |L52.24|
                          DCD      ||.data||

                          AREA ||i.EINT1_IRQHandler||, CODE, READONLY, ALIGN=2

                  EINT1_IRQHandler PROC
;;;49     /*---------------------------------------------------------------------------------------------------------*/
;;;50     void EINT1_IRQHandler(void)
000000  4805              LDR      r0,|L53.24|
;;;51     {
;;;52     	/* EINT0 = GPB15. Clear the interrupt */
;;;53     	gGPIO_EXT1_Base->ISR = 1UL << gGPIO_EXT1_Pin;
000002  2101              MOVS     r1,#1
000004  6a42              LDR      r2,[r0,#0x24]  ; gGPIO_EXT1_Pin
000006  4091              LSLS     r1,r1,r2
000008  69c2              LDR      r2,[r0,#0x1c]  ; gGPIO_EXT1_Base
00000a  6211              STR      r1,[r2,#0x20]
;;;54     	if ( _pfEINT1Callback )
00000c  6940              LDR      r0,[r0,#0x14]  ; _pfEINT1Callback
00000e  2800              CMP      r0,#0
000010  d000              BEQ      |L53.20|
;;;55     		_pfEINT1Callback();
000012  4700              BX       r0
                  |L53.20|
;;;56     }
000014  4770              BX       lr
;;;57     
                          ENDP

000016  0000              DCW      0x0000
                  |L53.24|
                          DCD      ||.data||

                          AREA ||i.GPABC_IRQHandler||, CODE, READONLY, ALIGN=2

                  GPABC_IRQHandler PROC
;;;60     /*---------------------------------------------------------------------------------------------------------*/
;;;61     void GPABC_IRQHandler(void)
000000  b430              PUSH     {r4,r5}
;;;62     {
;;;63     	uint32_t u32GPAStatus, u32GPBStatus, u32GPCStatus;
;;;64     
;;;65     	/* Keep the interrupt source */
;;;66     	u32GPAStatus = GPIOA->ISR;
000002  4b09              LDR      r3,|L54.40|
000004  6a18              LDR      r0,[r3,#0x20]
;;;67     	u32GPBStatus = GPIOB->ISR;
000006  4c08              LDR      r4,|L54.40|
000008  3440              ADDS     r4,r4,#0x40
00000a  6a21              LDR      r1,[r4,#0x20]
;;;68     	u32GPCStatus = GPIOC->ISR;
00000c  4d06              LDR      r5,|L54.40|
00000e  3580              ADDS     r5,r5,#0x80
000010  6a2a              LDR      r2,[r5,#0x20]
;;;69     
;;;70     	/* Clear the interrupt */
;;;71     	GPIOA->ISR = u32GPAStatus;
000012  6218              STR      r0,[r3,#0x20]
;;;72     	GPIOB->ISR = u32GPBStatus;
000014  6221              STR      r1,[r4,#0x20]
;;;73     	GPIOC->ISR = u32GPCStatus;
000016  622a              STR      r2,[r5,#0x20]
;;;74     
;;;75     	/* Call the callback function of GPIOAB interrupt */
;;;76     	if ( _pfGPABCCallback )
000018  4b04              LDR      r3,|L54.44|
00001a  689b              LDR      r3,[r3,#8]  ; _pfGPABCCallback
00001c  2b00              CMP      r3,#0
00001e  d001              BEQ      |L54.36|
;;;77     		_pfGPABCCallback(u32GPAStatus, u32GPBStatus, u32GPCStatus);
000020  bc30              POP      {r4,r5}
000022  4718              BX       r3
                  |L54.36|
;;;78     
;;;79     }
000024  bc30              POP      {r4,r5}
000026  4770              BX       lr
;;;80     
                          ENDP

                  |L54.40|
                          DCD      0x50004000
                  |L54.44|
                          DCD      ||.data||

                          AREA ||i.GPDEF_IRQHandler||, CODE, READONLY, ALIGN=2

                  GPDEF_IRQHandler PROC
;;;83     /*---------------------------------------------------------------------------------------------------------*/
;;;84     void GPDEF_IRQHandler(void)
000000  b430              PUSH     {r4,r5}
;;;85     {
;;;86     	uint32_t u32GPDStatus, u32GPEStatus, u32GPFStatus;
;;;87     
;;;88     	/* Keep the interrupt source */
;;;89     	u32GPDStatus = GPIOD->ISR;
000002  4b09              LDR      r3,|L55.40|
000004  6a18              LDR      r0,[r3,#0x20]
;;;90     	u32GPEStatus = GPIOE->ISR;
000006  4c08              LDR      r4,|L55.40|
000008  3440              ADDS     r4,r4,#0x40
00000a  6a21              LDR      r1,[r4,#0x20]
;;;91     	u32GPFStatus = GPIOF->ISR;
00000c  4d06              LDR      r5,|L55.40|
00000e  3580              ADDS     r5,r5,#0x80
000010  6a2a              LDR      r2,[r5,#0x20]
;;;92     
;;;93     	/* Clear the interrupt */
;;;94     	GPIOD->ISR = u32GPDStatus;
000012  6218              STR      r0,[r3,#0x20]
;;;95     	GPIOE->ISR = u32GPEStatus;
000014  6221              STR      r1,[r4,#0x20]
;;;96     	GPIOF->ISR = u32GPFStatus;
000016  622a              STR      r2,[r5,#0x20]
;;;97     
;;;98     	/* Call the callback function of GPIOABC interrupt */
;;;99     	if ( _pfGPDEFCallback )
000018  4b04              LDR      r3,|L55.44|
00001a  68db              LDR      r3,[r3,#0xc]  ; _pfGPDEFCallback
00001c  2b00              CMP      r3,#0
00001e  d001              BEQ      |L55.36|
;;;100    		_pfGPDEFCallback(u32GPDStatus, u32GPEStatus, u32GPFStatus);
000020  bc30              POP      {r4,r5}
000022  4718              BX       r3
                  |L55.36|
;;;101    }
000024  bc30              POP      {r4,r5}
000026  4770              BX       lr
;;;102    
                          ENDP

                  |L55.40|
                          DCD      0x500040c0
                  |L55.44|
                          DCD      ||.data||

                          AREA ||i.NVIC_DisableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_DisableIRQ PROC
;;;809     */
;;;810    static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;811    {
;;;812      NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L56.16|
00000a  6008              STR      r0,[r1,#0]
;;;813    }
00000c  4770              BX       lr
;;;814    
                          ENDP

00000e  0000              DCW      0x0000
                  |L56.16|
                          DCD      0xe000e180

                          AREA ||i.NVIC_EnableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_EnableIRQ PROC
;;;796     */
;;;797    static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;798    {
;;;799      NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L57.16|
00000a  6008              STR      r0,[r1,#0]
;;;800    }
00000c  4770              BX       lr
;;;801    
                          ENDP

00000e  0000              DCW      0x0000
                  |L57.16|
                          DCD      0xe000e100

                          AREA ||.data||, DATA, ALIGN=2

                  gIsEXT0_Config
                          DCD      0x00000000
                  gIsEXT1_Config
                          DCD      0x00000000
                  _pfGPABCCallback
                          DCD      0x00000000
                  _pfGPDEFCallback
                          DCD      0x00000000
                  _pfEINT0Callback
                          DCD      0x00000000
                  _pfEINT1Callback
                          DCD      0x00000000
                  gGPIO_EXT0_Base
                          DCD      0x00000000
                  gGPIO_EXT1_Base
                          DCD      0x00000000
                  gGPIO_EXT0_Pin
                          DCD      0x00000000
                  gGPIO_EXT1_Pin
                          DCD      0x00000000
                  gPreGPIO_EXT0
                          DCD      0x00000000
                  gPreGPIO_EXT1
                          DCD      0x00000000

                          AREA ||area_number.61||, DATA, ALIGN=2

                          EXPORTAS ||area_number.61||, ||.data||
                  gGPIOBase
                          DCD      0x00000000

                          AREA ||i.__ARM_common_switch8||, COMGROUP=__ARM_common_switch8, CODE, READONLY, ALIGN=1

                  __ARM_common_switch8 PROC
000000  b430              PUSH     {r4,r5}
000002  4674              MOV      r4,lr
000004  1e64              SUBS     r4,r4,#1
000006  7825              LDRB     r5,[r4,#0]
000008  1c64              ADDS     r4,r4,#1
00000a  42ab              CMP      r3,r5
00000c  d200              BCS      |L351.16|
00000e  461d              MOV      r5,r3
                  |L351.16|
000010  5d63              LDRB     r3,[r4,r5]
000012  005b              LSLS     r3,r3,#1
000014  18e3              ADDS     r3,r4,r3
000016  bc30              POP      {r4,r5}
000018  4718              BX       r3
                          ENDP

