; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\drvi2s.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvi2s.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvi2s.crf ..\bsp\Driver\DrvI2S.c]
                          THUMB

                          AREA ||i.DrvI2S_ClearRxFIFO||, CODE, READONLY, ALIGN=2

                  DrvI2S_ClearRxFIFO PROC
;;;489      */
;;;490    void DrvI2S_ClearRxFIFO(void)
000000  4803              LDR      r0,|L1.16|
;;;491    {
;;;492    	I2S->CTRL_BITS.CLR_RXFIFO = 1;
000002  6801              LDR      r1,[r0,#0]
000004  2201              MOVS     r2,#1
000006  04d2              LSLS     r2,r2,#19
000008  4311              ORRS     r1,r1,r2
00000a  6001              STR      r1,[r0,#0]
;;;493    }
00000c  4770              BX       lr
;;;494    
                          ENDP

00000e  0000              DCW      0x0000
                  |L1.16|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_ClearTxFIFO||, CODE, READONLY, ALIGN=2

                  DrvI2S_ClearTxFIFO PROC
;;;479      */
;;;480    void DrvI2S_ClearTxFIFO(void)
000000  4803              LDR      r0,|L2.16|
;;;481    {
;;;482    	I2S->CTRL_BITS.CLR_TXFIFO = 1;
000002  6801              LDR      r1,[r0,#0]
000004  2201              MOVS     r2,#1
000006  0492              LSLS     r2,r2,#18
000008  4311              ORRS     r1,r1,r2
00000a  6001              STR      r1,[r0,#0]
;;;483    }
00000c  4770              BX       lr
;;;484    
                          ENDP

00000e  0000              DCW      0x0000
                  |L2.16|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_Close||, CODE, READONLY, ALIGN=2

                  DrvI2S_Close PROC
;;;162      */
;;;163    void DrvI2S_Close(void)
000000  4809              LDR      r0,|L3.40|
;;;164    {
;;;165    	I2S->CTRL_BITS.I2SEN = 0;
000002  6801              LDR      r1,[r0,#0]
000004  0849              LSRS     r1,r1,#1
000006  0049              LSLS     r1,r1,#1
000008  6001              STR      r1,[r0,#0]
;;;166    	GCR->IPRST_CTL2_BITS.I2S_RST = 1;
00000a  2005              MOVS     r0,#5
00000c  0700              LSLS     r0,r0,#28
00000e  68c2              LDR      r2,[r0,#0xc]
000010  2101              MOVS     r1,#1
000012  0749              LSLS     r1,r1,#29
000014  430a              ORRS     r2,r2,r1
000016  60c2              STR      r2,[r0,#0xc]
;;;167    	GCR->IPRST_CTL2_BITS.I2S_RST = 0;
000018  68c2              LDR      r2,[r0,#0xc]
00001a  438a              BICS     r2,r2,r1
00001c  60c2              STR      r2,[r0,#0xc]
;;;168    	CLK->APBCLK_BITS.I2S_EN = 0;
00001e  4803              LDR      r0,|L3.44|
000020  6882              LDR      r2,[r0,#8]
000022  438a              BICS     r2,r2,r1
000024  6082              STR      r2,[r0,#8]
;;;169    }
000026  4770              BX       lr
;;;170    
                          ENDP

                  |L3.40|
                          DCD      0x401a0000
                  |L3.44|
                          DCD      0x50000200

                          AREA ||i.DrvI2S_DisableInt||, CODE, READONLY, ALIGN=2

                  DrvI2S_DisableInt PROC
;;;242      */
;;;243    int32_t DrvI2S_DisableInt(E_I2S_CALLBACK_TYPE Type)
000000  b500              PUSH     {lr}
;;;244    {	
;;;245    	I2S->INTEN &= ~(1<<Type);
000002  4913              LDR      r1,|L4.80|
000004  688a              LDR      r2,[r1,#8]
000006  2301              MOVS     r3,#1
000008  4083              LSLS     r3,r3,r0
00000a  439a              BICS     r2,r2,r3
00000c  608a              STR      r2,[r1,#8]
00000e  2100              MOVS     r1,#0                 ;244
;;;246    	
;;;247    	switch(Type)
;;;248        {
;;;249            case I2S_RX_UNDERFLOW:
;;;250            {
;;;251               	I2SHandler.RxUnderflowFn = NULL;  
000010  4a10              LDR      r2,|L4.84|
000012  0003              MOVS     r3,r0                 ;247
000014  f7fffffe          BL       __ARM_common_switch8
000018  0d080a0c          DCB      0x0d,0x08,0x0a,0x0c
00001c  19191919          DCB      0x19,0x19,0x19,0x19
000020  190e1012          DCB      0x19,0x0e,0x10,0x12
000024  14161900          DCB      0x14,0x16,0x19,0x00
;;;252            	break;
000028  6011              STR      r1,[r2,#0]  ; I2SHandler
00002a  e00c              B        |L4.70|
;;;253            }
;;;254            case I2S_RX_OVERFLOW:
;;;255            {
;;;256               	I2SHandler.RxOverflowFn = NULL; 
;;;257            	break;
00002c  6051              STR      r1,[r2,#4]  ; I2SHandler
00002e  e00a              B        |L4.70|
;;;258            }
;;;259            case I2S_RX_FIFO_THRESHOLD:
;;;260            {
;;;261               	I2SHandler.RxFifoThresholdFn = NULL;  
;;;262            	break;
000030  6091              STR      r1,[r2,#8]  ; I2SHandler
000032  e008              B        |L4.70|
;;;263            }        
;;;264            case I2S_TX_UNDERFLOW:
;;;265            {
;;;266               	I2SHandler.TxUnderflowFn = NULL;  
;;;267            	break;
000034  60d1              STR      r1,[r2,#0xc]  ; I2SHandler
000036  e006              B        |L4.70|
;;;268            }
;;;269            case I2S_TX_OVERFLOW:
;;;270            {
;;;271               	I2SHandler.TxOverflowFn = NULL;  
;;;272            	break;
000038  6111              STR      r1,[r2,#0x10]  ; I2SHandler
00003a  e004              B        |L4.70|
;;;273            }
;;;274            case I2S_TX_FIFO_THRESHOLD:
;;;275            {
;;;276               	I2SHandler.TxFifoThresholdFn = NULL;  
;;;277            	break;
00003c  6151              STR      r1,[r2,#0x14]  ; I2SHandler
00003e  e002              B        |L4.70|
;;;278            }
;;;279            case I2S_TX_RIGHT_ZERO_CROSS:
;;;280            {
;;;281               	I2SHandler.TxRightZeroCrossFn = NULL; 
;;;282            	break;
000040  6191              STR      r1,[r2,#0x18]  ; I2SHandler
000042  e000              B        |L4.70|
;;;283            }
;;;284            case I2S_TX_LEFT_ZERO_CROSS:
;;;285            {
;;;286               	I2SHandler.TxLeftZeroCrossFn = NULL; 
000044  61d1              STR      r1,[r2,#0x1c]  ; I2SHandler
                  |L4.70|
;;;287            	break;
;;;288            }		 
;;;289    		default:
;;;290    			return -1;                             	
;;;291    	}
;;;292    	
;;;293    	return E_SUCCESS;
000046  2000              MOVS     r0,#0
;;;294    }
000048  bd00              POP      {pc}
00004a  2000              MOVS     r0,#0                 ;290
00004c  43c0              MVNS     r0,r0                 ;290
00004e  bd00              POP      {pc}
;;;295    
                          ENDP

                  |L4.80|
                          DCD      0x401a0000
                  |L4.84|
                          DCD      ||.bss||

                          AREA ||i.DrvI2S_DisableRx||, CODE, READONLY, ALIGN=2

                  DrvI2S_DisableRx PROC
;;;449      */
;;;450    void DrvI2S_DisableRx(void)
000000  4802              LDR      r0,|L5.12|
;;;451    {
;;;452    	I2S->CTRL_BITS.RXEN = 0;	
000002  6801              LDR      r1,[r0,#0]
000004  2204              MOVS     r2,#4
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;453    }
00000a  4770              BX       lr
;;;454    
                          ENDP

                  |L5.12|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_DisableTx||, CODE, READONLY, ALIGN=2

                  DrvI2S_DisableTx PROC
;;;429      */
;;;430    void DrvI2S_DisableTx(void)
000000  4802              LDR      r0,|L6.12|
;;;431    {
;;;432    	I2S->CTRL_BITS.TXEN = 0;
000002  6801              LDR      r1,[r0,#0]
000004  2202              MOVS     r2,#2
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;433    }
00000a  4770              BX       lr
;;;434    
                          ENDP

                  |L6.12|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_EnableInt||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableInt PROC
;;;179      */
;;;180    int32_t DrvI2S_EnableInt(E_I2S_CALLBACK_TYPE Type, I2S_CALLBACK callbackfn)
000000  b500              PUSH     {lr}
;;;181    {
;;;182    	switch (Type)
;;;183        {
;;;184            case I2S_RX_UNDERFLOW:
;;;185            {
;;;186               	I2SHandler.RxUnderflowFn = callbackfn;  
000002  4a15              LDR      r2,|L7.88|
000004  0003              MOVS     r3,r0                 ;182
000006  f7fffffe          BL       __ARM_common_switch8
00000a  0d08              DCB      0x0d,0x08
00000c  0a0c2323          DCB      0x0a,0x0c,0x23,0x23
000010  2323230e          DCB      0x23,0x23,0x23,0x0e
000014  10121416          DCB      0x10,0x12,0x14,0x16
000018  2300              DCB      0x23,0x00
;;;187            	break;
00001a  6011              STR      r1,[r2,#0]  ; I2SHandler
00001c  e00c              B        |L7.56|
;;;188            }
;;;189            case I2S_RX_OVERFLOW:
;;;190            {
;;;191               	I2SHandler.RxOverflowFn = callbackfn; 
;;;192            	break;
00001e  6051              STR      r1,[r2,#4]  ; I2SHandler
000020  e00a              B        |L7.56|
;;;193            }
;;;194            case I2S_RX_FIFO_THRESHOLD:
;;;195            {
;;;196               	I2SHandler.RxFifoThresholdFn = callbackfn;  
;;;197            	break;
000022  6091              STR      r1,[r2,#8]  ; I2SHandler
000024  e008              B        |L7.56|
;;;198            }        
;;;199            case I2S_TX_UNDERFLOW:
;;;200            {
;;;201               	I2SHandler.TxUnderflowFn = callbackfn;  
;;;202            	break;
000026  60d1              STR      r1,[r2,#0xc]  ; I2SHandler
000028  e006              B        |L7.56|
;;;203            }
;;;204            case I2S_TX_OVERFLOW:
;;;205            {
;;;206               	I2SHandler.TxOverflowFn = callbackfn;  
;;;207            	break;
00002a  6111              STR      r1,[r2,#0x10]  ; I2SHandler
00002c  e004              B        |L7.56|
;;;208            }
;;;209            case I2S_TX_FIFO_THRESHOLD:
;;;210            {
;;;211               	I2SHandler.TxFifoThresholdFn = callbackfn;  
;;;212            	break;
00002e  6151              STR      r1,[r2,#0x14]  ; I2SHandler
000030  e002              B        |L7.56|
;;;213            }
;;;214            case I2S_TX_RIGHT_ZERO_CROSS:
;;;215            {
;;;216               	I2SHandler.TxRightZeroCrossFn = callbackfn; 
;;;217            	break;
000032  6191              STR      r1,[r2,#0x18]  ; I2SHandler
000034  e000              B        |L7.56|
;;;218            }
;;;219            case I2S_TX_LEFT_ZERO_CROSS:
;;;220            {
;;;221               	I2SHandler.TxLeftZeroCrossFn = callbackfn; 
000036  61d1              STR      r1,[r2,#0x1c]  ; I2SHandler
                  |L7.56|
;;;222            	break;
;;;223            }		 
;;;224    		default:
;;;225    			return -1;                             	
;;;226    	}
;;;227    		
;;;228    	I2S->INTEN |= (1<<Type);	
000038  4a08              LDR      r2,|L7.92|
00003a  6893              LDR      r3,[r2,#8]
00003c  2101              MOVS     r1,#1
00003e  4081              LSLS     r1,r1,r0
000040  430b              ORRS     r3,r3,r1
000042  6093              STR      r3,[r2,#8]
000044  2001              MOVS     r0,#1
000046  4906              LDR      r1,|L7.96|
000048  06c0              LSLS     r0,r0,#27
00004a  6008              STR      r0,[r1,#0]
;;;229    	NVIC_EnableIRQ(I2S_IRQn);
;;;230    	
;;;231    	return E_SUCCESS;
00004c  2000              MOVS     r0,#0
;;;232    }
00004e  bd00              POP      {pc}
000050  2000              MOVS     r0,#0                 ;225
000052  43c0              MVNS     r0,r0                 ;225
000054  bd00              POP      {pc}
;;;233    
                          ENDP

000056  0000              DCW      0x0000
                  |L7.88|
                          DCD      ||.bss||
                  |L7.92|
                          DCD      0x401a0000
                  |L7.96|
                          DCD      0xe000e100

                          AREA ||i.DrvI2S_EnableMCLK||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableMCLK PROC
;;;469      */
;;;470    void DrvI2S_EnableMCLK(int32_t i32flag)
000000  4a04              LDR      r2,|L8.20|
;;;471    {	
;;;472    	I2S->CTRL_BITS.MCLKEN = i32flag;	
000002  6811              LDR      r1,[r2,#0]
000004  2301              MOVS     r3,#1
000006  03db              LSLS     r3,r3,#15
000008  07c0              LSLS     r0,r0,#31
00000a  4399              BICS     r1,r1,r3
00000c  0c00              LSRS     r0,r0,#16
00000e  4301              ORRS     r1,r1,r0
000010  6011              STR      r1,[r2,#0]
;;;473    }
000012  4770              BX       lr
;;;474    
                          ENDP

                  |L8.20|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_EnableRx||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableRx PROC
;;;439      */
;;;440    void DrvI2S_EnableRx(void)
000000  4802              LDR      r0,|L9.12|
;;;441    {
;;;442    	I2S->CTRL_BITS.RXEN = 1;	
000002  6801              LDR      r1,[r0,#0]
000004  2204              MOVS     r2,#4
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;443    }
00000a  4770              BX       lr
;;;444    
                          ENDP

                  |L9.12|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_EnableRxDMA||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableRxDMA PROC
;;;409      */
;;;410    void DrvI2S_EnableRxDMA(int32_t i32flag)
000000  4a04              LDR      r2,|L10.20|
;;;411    {
;;;412    	I2S->CTRL_BITS.RXDMA = i32flag;		
000002  6811              LDR      r1,[r2,#0]
000004  2301              MOVS     r3,#1
000006  055b              LSLS     r3,r3,#21
000008  07c0              LSLS     r0,r0,#31
00000a  4399              BICS     r1,r1,r3
00000c  0a80              LSRS     r0,r0,#10
00000e  4301              ORRS     r1,r1,r0
000010  6011              STR      r1,[r2,#0]
;;;413    }
000012  4770              BX       lr
;;;414    
                          ENDP

                  |L10.20|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_EnableTx||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableTx PROC
;;;419      */
;;;420    void DrvI2S_EnableTx(void)
000000  4802              LDR      r0,|L11.12|
;;;421    {
;;;422    	I2S->CTRL_BITS.TXEN = 1;
000002  6801              LDR      r1,[r0,#0]
000004  2202              MOVS     r2,#2
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;423    }
00000a  4770              BX       lr
;;;424    
                          ENDP

                  |L11.12|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_EnableTxDMA||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableTxDMA PROC
;;;399      */
;;;400    void DrvI2S_EnableTxDMA(int32_t i32flag)
000000  4a04              LDR      r2,|L12.20|
;;;401    {	
;;;402    	I2S->CTRL_BITS.TXDMA = i32flag;	
000002  6811              LDR      r1,[r2,#0]
000004  2301              MOVS     r3,#1
000006  051b              LSLS     r3,r3,#20
000008  07c0              LSLS     r0,r0,#31
00000a  4399              BICS     r1,r1,r3
00000c  0ac0              LSRS     r0,r0,#11
00000e  4301              ORRS     r1,r1,r0
000010  6011              STR      r1,[r2,#0]
;;;403    }
000012  4770              BX       lr
;;;404    
                          ENDP

                  |L12.20|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_EnableTxMute||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableTxMute PROC
;;;459      */
;;;460    void DrvI2S_EnableTxMute(int32_t i32flag)
000000  4a04              LDR      r2,|L13.20|
;;;461    {
;;;462    	I2S->CTRL_BITS.MUTE = i32flag;		
000002  6811              LDR      r1,[r2,#0]
000004  2308              MOVS     r3,#8
000006  07c0              LSLS     r0,r0,#31
000008  4399              BICS     r1,r1,r3
00000a  0f00              LSRS     r0,r0,#28
00000c  4301              ORRS     r1,r1,r0
00000e  6011              STR      r1,[r2,#0]
;;;463    }
000010  4770              BX       lr
;;;464    
                          ENDP

000012  0000              DCW      0x0000
                  |L13.20|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_EnableZeroCrossDetect||, CODE, READONLY, ALIGN=2

                  DrvI2S_EnableZeroCrossDetect PROC
;;;378      */
;;;379    int32_t DrvI2S_EnableZeroCrossDetect(E_I2S_CHANNEL channel, int32_t i32flag)
000000  4a0c              LDR      r2,|L14.52|
;;;380    {
;;;381    	if (channel == I2S_LEFT_CHANNEL)
000002  2800              CMP      r0,#0
000004  d004              BEQ      |L14.16|
;;;382    	{
;;;383    		I2S->CTRL_BITS.LCHZCEN = i32flag;
;;;384    	}
;;;385    	else if (channel == I2S_RIGHT_CHANNEL)
000006  2801              CMP      r0,#1
000008  d009              BEQ      |L14.30|
;;;386    	{
;;;387    		I2S->CTRL_BITS.RCHZCEN = i32flag;
;;;388    	}
;;;389    	else
;;;390    		return -1;
00000a  2000              MOVS     r0,#0
00000c  43c0              MVNS     r0,r0
;;;391    
;;;392    	return E_SUCCESS;
;;;393    }
00000e  4770              BX       lr
                  |L14.16|
000010  6810              LDR      r0,[r2,#0]            ;383
000012  2301              MOVS     r3,#1                 ;383
000014  045b              LSLS     r3,r3,#17             ;383
000016  4398              BICS     r0,r0,r3              ;383
000018  07c9              LSLS     r1,r1,#31             ;383
00001a  0b89              LSRS     r1,r1,#14             ;383
00001c  e005              B        |L14.42|
                  |L14.30|
00001e  6810              LDR      r0,[r2,#0]            ;387
000020  2301              MOVS     r3,#1                 ;387
000022  041b              LSLS     r3,r3,#16             ;387
000024  4398              BICS     r0,r0,r3              ;387
000026  07c9              LSLS     r1,r1,#31             ;387
000028  0bc9              LSRS     r1,r1,#15             ;387
                  |L14.42|
00002a  4308              ORRS     r0,r0,r1              ;387
00002c  6010              STR      r0,[r2,#0]            ;387
00002e  2000              MOVS     r0,#0                 ;392
000030  4770              BX       lr
;;;394    
                          ENDP

000032  0000              DCW      0x0000
                  |L14.52|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_GetBCLKFreq||, CODE, READONLY, ALIGN=2

                  DrvI2S_GetBCLKFreq PROC
;;;300      */
;;;301    uint32_t DrvI2S_GetBCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;302    {
;;;303    	uint32_t u32Reg, u32SrcClk;
;;;304    	
;;;305    	u32SrcClk = DrvI2S_GetSourceClockFreq(); 		
000002  f7fffffe          BL       DrvI2S_GetSourceClockFreq
;;;306    	
;;;307    	u32Reg = I2S->CLKDIV_BITS.BCLK_DIV;
000006  4904              LDR      r1,|L15.24|
000008  6849              LDR      r1,[r1,#4]
;;;308    	
;;;309    	return ((u32SrcClk >> 1) / (u32Reg + 1));
00000a  0840              LSRS     r0,r0,#1
00000c  0409              LSLS     r1,r1,#16             ;307
00000e  0e09              LSRS     r1,r1,#24             ;307
000010  1c49              ADDS     r1,r1,#1
000012  f7fffffe          BL       __aeabi_uidivmod
;;;310    }
000016  bd10              POP      {r4,pc}
;;;311    
                          ENDP

                  |L15.24|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_GetMCLKFreq||, CODE, READONLY, ALIGN=2

                  DrvI2S_GetMCLKFreq PROC
;;;333      */
;;;334    uint32_t DrvI2S_GetMCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;335    {
;;;336    	uint32_t u32Reg, u32SrcClk;
;;;337    
;;;338    	u32Reg = I2S->CLKDIV_BITS.MCLK_DIV;
000002  4806              LDR      r0,|L16.28|
000004  6840              LDR      r0,[r0,#4]
000006  0744              LSLS     r4,r0,#29
000008  0f64              LSRS     r4,r4,#29
;;;339    
;;;340    	u32SrcClk = DrvI2S_GetSourceClockFreq(); 	
00000a  f7fffffe          BL       DrvI2S_GetSourceClockFreq
;;;341    
;;;342    	if (u32Reg == 0)
00000e  2c00              CMP      r4,#0
000010  d003              BEQ      |L16.26|
;;;343    		return u32SrcClk;
;;;344    	else
;;;345    		return ((u32SrcClk >> 1) / u32Reg);
000012  0840              LSRS     r0,r0,#1
000014  4621              MOV      r1,r4
000016  f7fffffe          BL       __aeabi_uidivmod
                  |L16.26|
;;;346    }
00001a  bd10              POP      {r4,pc}
;;;347    
                          ENDP

                  |L16.28|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_GetSourceClockFreq||, CODE, READONLY, ALIGN=2

                  DrvI2S_GetSourceClockFreq PROC
;;;509      */
;;;510    uint32_t DrvI2S_GetSourceClockFreq(void)
000000  b510              PUSH     {r4,lr}
;;;511    {
;;;512    	uint8_t  u8ClkSrcSel;
;;;513    	uint32_t u32Freq = 12000000, u32Div;
;;;514    	
;;;515    	// get I2S selection clock source
;;;516    	u8ClkSrcSel = CLK->CLKSEL2_BITS.I2S_S;
000002  4c0b              LDR      r4,|L17.48|
000004  4809              LDR      r0,|L17.44|
000006  69a1              LDR      r1,[r4,#0x18]
000008  0389              LSLS     r1,r1,#14
00000a  0f89              LSRS     r1,r1,#30
;;;517    
;;;518    	switch (u8ClkSrcSel)
00000c  d00a              BEQ      |L17.36|
00000e  2901              CMP      r1,#1
000010  d107              BNE      |L17.34|
;;;519    	{
;;;520    		case DRVI2S_SOURCE_HXT:
;;;521    			u32Freq = DrvSYS_GetExtClockFreq();
;;;522    			break;
;;;523    		case DRVI2S_SOURCE_PLL:
;;;524    			u32Freq = DrvSYS_GetPLLClockFreq();
000012  f7fffffe          BL       DrvSYS_GetPLLClockFreq
;;;525    			u32Div = CLK->CLKDIV0_BITS.I2S_N+1;
000016  69e1              LDR      r1,[r4,#0x1c]
000018  0409              LSLS     r1,r1,#16
00001a  0f09              LSRS     r1,r1,#28
00001c  1c49              ADDS     r1,r1,#1
;;;526    			u32Freq /= u32Div;			
00001e  f7fffffe          BL       __aeabi_uidivmod
                  |L17.34|
;;;527    			break;
;;;528    		case DRVI2S_SOURCE_HIRC:
;;;529    			u32Freq = __IRC12M;
;;;530    			break;		
;;;531    	}
;;;532    
;;;533    	return u32Freq;
;;;534    }
000022  bd10              POP      {r4,pc}
                  |L17.36|
000024  f7fffffe          BL       DrvSYS_GetExtClockFreq
000028  bd10              POP      {r4,pc}
;;;535    
                          ENDP

00002a  0000              DCW      0x0000
                  |L17.44|
                          DCD      0x00b71b00
                  |L17.48|
                          DCD      0x50000200

                          AREA ||i.DrvI2S_Open||, CODE, READONLY, ALIGN=2

                  DrvI2S_Open PROC
;;;127      */
;;;128    int32_t DrvI2S_Open(S_DRVI2S_DATA_T *sParam)
000000  b570              PUSH     {r4-r6,lr}
;;;129    {
000002  4604              MOV      r4,r0
;;;130    	uint8_t u8Divider;
;;;131    	uint32_t u32BitRate, u32SrcClk;
;;;132    	
;;;133    	GCR->IPRST_CTL2_BITS.I2S_RST = 1;
000004  2005              MOVS     r0,#5
000006  0700              LSLS     r0,r0,#28
000008  68c2              LDR      r2,[r0,#0xc]
00000a  2101              MOVS     r1,#1
00000c  0749              LSLS     r1,r1,#29
00000e  430a              ORRS     r2,r2,r1
000010  60c2              STR      r2,[r0,#0xc]
;;;134    	GCR->IPRST_CTL2_BITS.I2S_RST = 0;
000012  68c2              LDR      r2,[r0,#0xc]
000014  438a              BICS     r2,r2,r1
000016  60c2              STR      r2,[r0,#0xc]
;;;135    
;;;136    	CLK->APBCLK_BITS.I2S_EN = 1;
000018  4829              LDR      r0,|L18.192|
00001a  6882              LDR      r2,[r0,#8]
00001c  430a              ORRS     r2,r2,r1
00001e  6082              STR      r2,[r0,#8]
;;;137    				
;;;138    	I2S->CTRL_BITS.WORDWIDTH 	= sParam->u8WordWidth;
000020  4d28              LDR      r5,|L18.196|
000022  6828              LDR      r0,[r5,#0]
000024  2130              MOVS     r1,#0x30
000026  4388              BICS     r0,r0,r1
000028  7921              LDRB     r1,[r4,#4]
00002a  0789              LSLS     r1,r1,#30
00002c  0e89              LSRS     r1,r1,#26
00002e  4308              ORRS     r0,r0,r1
000030  6028              STR      r0,[r5,#0]
;;;139    	I2S->CTRL_BITS.MONO 		= sParam->u8AudioFormat;
000032  6828              LDR      r0,[r5,#0]
000034  2140              MOVS     r1,#0x40
000036  4388              BICS     r0,r0,r1
000038  7961              LDRB     r1,[r4,#5]
00003a  07c9              LSLS     r1,r1,#31
00003c  0e49              LSRS     r1,r1,#25
00003e  4308              ORRS     r0,r0,r1
000040  6028              STR      r0,[r5,#0]
;;;140    	I2S->CTRL_BITS.FORMAT 		= sParam->u8DataFormat;
000042  6828              LDR      r0,[r5,#0]
000044  2180              MOVS     r1,#0x80
000046  4388              BICS     r0,r0,r1
000048  79a1              LDRB     r1,[r4,#6]
00004a  07c9              LSLS     r1,r1,#31
00004c  0e09              LSRS     r1,r1,#24
00004e  4308              ORRS     r0,r0,r1
000050  6028              STR      r0,[r5,#0]
;;;141    	I2S->CTRL_BITS.SLAVE 		= sParam->u8Mode;
000052  6828              LDR      r0,[r5,#0]
000054  15a9              ASRS     r1,r5,#22
000056  4388              BICS     r0,r0,r1
000058  79e1              LDRB     r1,[r4,#7]
00005a  07c9              LSLS     r1,r1,#31
00005c  0dc9              LSRS     r1,r1,#23
00005e  4308              ORRS     r0,r0,r1
000060  6028              STR      r0,[r5,#0]
;;;142    	I2S->CTRL_BITS.TXTH 		= sParam->u8TxFIFOThreshold;
000062  6828              LDR      r0,[r5,#0]
000064  2107              MOVS     r1,#7
000066  0249              LSLS     r1,r1,#9
000068  4388              BICS     r0,r0,r1
00006a  7a21              LDRB     r1,[r4,#8]
00006c  0749              LSLS     r1,r1,#29
00006e  0d09              LSRS     r1,r1,#20
000070  4308              ORRS     r0,r0,r1
000072  6028              STR      r0,[r5,#0]
;;;143    	I2S->CTRL_BITS.RXTH 		= sParam->u8RxFIFOThreshold - 1;
000074  7a60              LDRB     r0,[r4,#9]
000076  2107              MOVS     r1,#7
000078  0300              LSLS     r0,r0,#12
00007a  0309              LSLS     r1,r1,#12
00007c  1840              ADDS     r0,r0,r1
00007e  0440              LSLS     r0,r0,#17
000080  6829              LDR      r1,[r5,#0]
000082  0c40              LSRS     r0,r0,#17
000084  2207              MOVS     r2,#7
000086  0312              LSLS     r2,r2,#12
000088  4391              BICS     r1,r1,r2
00008a  4308              ORRS     r0,r0,r1
00008c  6028              STR      r0,[r5,#0]
;;;144    
;;;145    	u32SrcClk = DrvI2S_GetSourceClockFreq();
00008e  f7fffffe          BL       DrvI2S_GetSourceClockFreq
;;;146    	
;;;147    	u32BitRate = sParam->u32SampleRate * (sParam->u8WordWidth + 1) * 16;
000092  7922              LDRB     r2,[r4,#4]
000094  6821              LDR      r1,[r4,#0]
000096  1c52              ADDS     r2,r2,#1
000098  4351              MULS     r1,r2,r1
00009a  0109              LSLS     r1,r1,#4
;;;148    
;;;149    	u8Divider = ((u32SrcClk/u32BitRate) >> 1) - 1;
00009c  f7fffffe          BL       __aeabi_uidivmod
0000a0  0840              LSRS     r0,r0,#1
0000a2  1e40              SUBS     r0,r0,#1
;;;150    	
;;;151    	I2S->CLKDIV_BITS.BCLK_DIV = u8Divider;	
0000a4  6869              LDR      r1,[r5,#4]
0000a6  0600              LSLS     r0,r0,#24             ;149
0000a8  22ff              MOVS     r2,#0xff
0000aa  0212              LSLS     r2,r2,#8
0000ac  4391              BICS     r1,r1,r2
0000ae  0c00              LSRS     r0,r0,#16
0000b0  4301              ORRS     r1,r1,r0
0000b2  6069              STR      r1,[r5,#4]
;;;152    	
;;;153    	I2S->CTRL_BITS.I2SEN = 1;	
0000b4  6828              LDR      r0,[r5,#0]
0000b6  2101              MOVS     r1,#1
0000b8  4308              ORRS     r0,r0,r1
0000ba  6028              STR      r0,[r5,#0]
;;;154    
;;;155    	return E_SUCCESS;
0000bc  2000              MOVS     r0,#0
;;;156    }
0000be  bd70              POP      {r4-r6,pc}
;;;157    
                          ENDP

                  |L18.192|
                          DCD      0x50000200
                  |L18.196|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_SelClockSource||, CODE, READONLY, ALIGN=2

                  DrvI2S_SelClockSource PROC
;;;499      */
;;;500    void DrvI2S_SelClockSource(uint8_t u8ClkSrcSel)
000000  4a04              LDR      r2,|L19.20|
;;;501    {
;;;502    	CLK->CLKSEL2_BITS.I2S_S = u8ClkSrcSel;
000002  6991              LDR      r1,[r2,#0x18]
000004  2303              MOVS     r3,#3
000006  041b              LSLS     r3,r3,#16
000008  0780              LSLS     r0,r0,#30
00000a  4399              BICS     r1,r1,r3
00000c  0b80              LSRS     r0,r0,#14
00000e  4301              ORRS     r1,r1,r0
000010  6191              STR      r1,[r2,#0x18]
;;;503    }
000012  4770              BX       lr
;;;504    
                          ENDP

                  |L19.20|
                          DCD      0x50000200

                          AREA ||i.DrvI2S_SetBCLKFreq||, CODE, READONLY, ALIGN=2

                  DrvI2S_SetBCLKFreq PROC
;;;316      */
;;;317    void DrvI2S_SetBCLKFreq(uint32_t u32Bclk)
000000  b510              PUSH     {r4,lr}
;;;318    {
000002  4604              MOV      r4,r0
;;;319    	uint8_t u8Divider;
;;;320    	uint32_t u32SrcClk;
;;;321    
;;;322    	u32SrcClk = DrvI2S_GetSourceClockFreq(); 
000004  f7fffffe          BL       DrvI2S_GetSourceClockFreq
;;;323    	
;;;324    	u8Divider = ((u32SrcClk/u32Bclk) >> 1) - 1;
000008  4621              MOV      r1,r4
00000a  f7fffffe          BL       __aeabi_uidivmod
;;;325    
;;;326    	I2S->CLKDIV_BITS.BCLK_DIV = u8Divider;
00000e  4a06              LDR      r2,|L20.40|
000010  0840              LSRS     r0,r0,#1              ;324
000012  1e40              SUBS     r0,r0,#1              ;324
000014  6851              LDR      r1,[r2,#4]
000016  0600              LSLS     r0,r0,#24             ;324
000018  23ff              MOVS     r3,#0xff
00001a  021b              LSLS     r3,r3,#8
00001c  4399              BICS     r1,r1,r3
00001e  0c00              LSRS     r0,r0,#16
000020  4301              ORRS     r1,r1,r0
000022  6051              STR      r1,[r2,#4]
;;;327    }
000024  bd10              POP      {r4,pc}
;;;328    
                          ENDP

000026  0000              DCW      0x0000
                  |L20.40|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_SetMCLKFreq||, CODE, READONLY, ALIGN=2

                  DrvI2S_SetMCLKFreq PROC
;;;352      */
;;;353    void DrvI2S_SetMCLKFreq(uint32_t u32Mclk)
000000  b510              PUSH     {r4,lr}
;;;354    {
000002  4604              MOV      r4,r0
;;;355    	uint8_t u8Divider;
;;;356    	uint32_t u32SrcClk;
;;;357    
;;;358    	u32SrcClk = DrvI2S_GetSourceClockFreq(); 
000004  f7fffffe          BL       DrvI2S_GetSourceClockFreq
;;;359    
;;;360    	if (u32Mclk == u32SrcClk)
000008  4284              CMP      r4,r0
00000a  d101              BNE      |L21.16|
;;;361    	{
;;;362    		u8Divider = 0;
00000c  2000              MOVS     r0,#0
00000e  e004              B        |L21.26|
                  |L21.16|
;;;363    	}
;;;364    	else
;;;365    	{
;;;366    		u8Divider = (u32SrcClk/u32Mclk) >> 1;
000010  4621              MOV      r1,r4
000012  f7fffffe          BL       __aeabi_uidivmod
000016  05c0              LSLS     r0,r0,#23
000018  0e00              LSRS     r0,r0,#24
                  |L21.26|
;;;367    	}
;;;368    	
;;;369    	I2S->CLKDIV_BITS.MCLK_DIV = u8Divider;
00001a  4904              LDR      r1,|L21.44|
00001c  684a              LDR      r2,[r1,#4]
00001e  0740              LSLS     r0,r0,#29
000020  08d2              LSRS     r2,r2,#3
000022  00d2              LSLS     r2,r2,#3
000024  0f40              LSRS     r0,r0,#29
000026  4302              ORRS     r2,r2,r0
000028  604a              STR      r2,[r1,#4]
;;;370    }
00002a  bd10              POP      {r4,pc}
;;;371    
                          ENDP

                  |L21.44|
                          DCD      0x401a0000

                          AREA ||i.DrvI2S_SetMonoSrcChannel||, CODE, READONLY, ALIGN=2

                  DrvI2S_SetMonoSrcChannel PROC
;;;540      */
;;;541    void DrvI2S_SetMonoSrcChannel(uint8_t u8Ch)
000000  4a04              LDR      r2,|L22.20|
;;;542    {
;;;543    	I2S->CTRL_BITS.RXLCH = u8Ch;
000002  6811              LDR      r1,[r2,#0]
000004  2301              MOVS     r3,#1
000006  05db              LSLS     r3,r3,#23
000008  07c0              LSLS     r0,r0,#31
00000a  4399              BICS     r1,r1,r3
00000c  0a00              LSRS     r0,r0,#8
00000e  4301              ORRS     r1,r1,r0
000010  6011              STR      r1,[r2,#0]
;;;544    }
000012  4770              BX       lr
;;;545    
                          ENDP

                  |L22.20|
                          DCD      0x401a0000

                          AREA ||i.I2S_IRQHandler||, CODE, READONLY, ALIGN=2

                  I2S_IRQHandler PROC
;;;24       */
;;;25     void I2S_IRQHandler(void)
000000  b510              PUSH     {r4,lr}
;;;26     {
;;;27         uint32_t u32Reg;
;;;28     
;;;29     	u32Reg = I2S->STATUS;
000002  4c32              LDR      r4,|L23.204|
000004  68e0              LDR      r0,[r4,#0xc]
;;;30     
;;;31     	if (u32Reg & I2S_I2STXINT)
;;;32     	{
;;;33     		/* Tx underflow */
;;;34     		if ((u32Reg & I2S_TXUDF) && (I2S->INTIE_BITS.TXUDFIE == 1))
;;;35     		{
;;;36     			if (I2SHandler.TxUnderflowFn)
000006  4932              LDR      r1,|L23.208|
000008  0742              LSLS     r2,r0,#29             ;31
00000a  d53a              BPL      |L23.130|
00000c  03c2              LSLS     r2,r0,#15             ;34
00000e  d50a              BPL      |L23.38|
000010  68a2              LDR      r2,[r4,#8]            ;34
000012  05d2              LSLS     r2,r2,#23             ;34
000014  d507              BPL      |L23.38|
000016  68c9              LDR      r1,[r1,#0xc]  ; I2SHandler
000018  2900              CMP      r1,#0
00001a  d000              BEQ      |L23.30|
;;;37     				I2SHandler.TxUnderflowFn(u32Reg);
00001c  4788              BLX      r1
                  |L23.30|
;;;38     			
;;;39     			I2S->STATUS_BITS.TXUDF = 1;
00001e  68e0              LDR      r0,[r4,#0xc]
000020  2101              MOVS     r1,#1
000022  0409              LSLS     r1,r1,#16
000024  e00b              B        |L23.62|
                  |L23.38|
;;;40     		}
;;;41     		/* Tx overflow */
;;;42     		else if ((u32Reg & I2S_TXOVF) && (I2S->INTIE_BITS.TXOVFIE == 1))
000026  0382              LSLS     r2,r0,#14
000028  d50c              BPL      |L23.68|
00002a  68a2              LDR      r2,[r4,#8]
00002c  0592              LSLS     r2,r2,#22
00002e  d509              BPL      |L23.68|
;;;43     		{
;;;44     			if (I2SHandler.TxOverflowFn)
000030  6909              LDR      r1,[r1,#0x10]  ; I2SHandler
000032  2900              CMP      r1,#0
000034  d000              BEQ      |L23.56|
;;;45     				I2SHandler.TxOverflowFn(u32Reg);
000036  4788              BLX      r1
                  |L23.56|
;;;46     			
;;;47     			I2S->STATUS_BITS.TXOVF = 1;		
000038  68e0              LDR      r0,[r4,#0xc]
00003a  2101              MOVS     r1,#1
00003c  0449              LSLS     r1,r1,#17
                  |L23.62|
00003e  4308              ORRS     r0,r0,r1              ;39
000040  60e0              STR      r0,[r4,#0xc]          ;39
                  |L23.66|
;;;48     		}
;;;49     		/* Tx right zero cross */
;;;50     		else if ((u32Reg & I2S_RZCF) && (I2S->INTIE_BITS.RZCIE == 1))
;;;51     		{
;;;52     			if (I2SHandler.TxRightZeroCrossFn)
;;;53     				I2SHandler.TxRightZeroCrossFn(u32Reg);
;;;54     			I2S->STATUS_BITS.RZCF = 1;
;;;55     		}
;;;56     		/* Tx left zero cross */
;;;57     		else if ((u32Reg & I2S_LZCF) && (I2S->INTIE_BITS.LZCIE == 1))
;;;58     		{
;;;59     			if (I2SHandler.TxLeftZeroCrossFn)
;;;60     				I2SHandler.TxLeftZeroCrossFn(u32Reg);
;;;61     			I2S->STATUS_BITS.LZCF = 1;
;;;62     		}						  
;;;63     		/* Tx threshold level */
;;;64     		else if (I2S->INTIE_BITS.TXTHIE == 1)
;;;65     		{
;;;66     			if (I2SHandler.TxFifoThresholdFn)
;;;67     				I2SHandler.TxFifoThresholdFn(u32Reg);		
;;;68     		}
;;;69     	}
;;;70     	else if (u32Reg & I2S_I2SRXINT)
;;;71     	{
;;;72     		/* Rx underflow */
;;;73     		if ((u32Reg & I2S_RXUDF) && (I2S->INTIE_BITS.RXUDFIE == 1))
;;;74     		{
;;;75     			if (I2SHandler.RxUnderflowFn)
;;;76     				I2SHandler.RxUnderflowFn(u32Reg);
;;;77     			
;;;78     			I2S->STATUS_BITS.RXUDF = 1;
;;;79     		}
;;;80     		/* Rx overflow */
;;;81     		else if ((u32Reg & I2S_RXOVF) && (I2S->INTIE_BITS.RXOVFIE == 1))
;;;82     		{
;;;83     			if (I2SHandler.RxOverflowFn)
;;;84     				I2SHandler.RxOverflowFn(u32Reg);
;;;85     
;;;86     			I2S->STATUS_BITS.RXOVF = 1;
;;;87     		}
;;;88     		/* Rx threshold level */
;;;89     		else if (I2S->INTIE_BITS.RXTHIE == 1)
;;;90     		{
;;;91     			if (I2SHandler.RxFifoThresholdFn)
;;;92     				I2SHandler.RxFifoThresholdFn(u32Reg);		
;;;93     		}	
;;;94     	}	
;;;95     }
000042  bd10              POP      {r4,pc}
                  |L23.68|
000044  0242              LSLS     r2,r0,#9              ;50
000046  d50a              BPL      |L23.94|
000048  68a2              LDR      r2,[r4,#8]            ;50
00004a  0512              LSLS     r2,r2,#20             ;50
00004c  d507              BPL      |L23.94|
00004e  6989              LDR      r1,[r1,#0x18]         ;52  ; I2SHandler
000050  2900              CMP      r1,#0                 ;52
000052  d000              BEQ      |L23.86|
000054  4788              BLX      r1                    ;53
                  |L23.86|
000056  68e0              LDR      r0,[r4,#0xc]          ;54
000058  2101              MOVS     r1,#1                 ;54
00005a  0589              LSLS     r1,r1,#22             ;54
00005c  e7ef              B        |L23.62|
                  |L23.94|
00005e  0202              LSLS     r2,r0,#8              ;57
000060  d50a              BPL      |L23.120|
000062  68a2              LDR      r2,[r4,#8]            ;57
000064  04d2              LSLS     r2,r2,#19             ;57
000066  d507              BPL      |L23.120|
000068  69c9              LDR      r1,[r1,#0x1c]         ;59  ; I2SHandler
00006a  2900              CMP      r1,#0                 ;59
00006c  d000              BEQ      |L23.112|
00006e  4788              BLX      r1                    ;60
                  |L23.112|
000070  68e0              LDR      r0,[r4,#0xc]          ;61
000072  2101              MOVS     r1,#1                 ;61
000074  05c9              LSLS     r1,r1,#23             ;61
000076  e7e2              B        |L23.62|
                  |L23.120|
000078  68a2              LDR      r2,[r4,#8]            ;64
00007a  0552              LSLS     r2,r2,#21             ;64
00007c  d5e1              BPL      |L23.66|
00007e  6949              LDR      r1,[r1,#0x14]         ;66  ; I2SHandler
000080  e01f              B        |L23.194|
                  |L23.130|
000082  0782              LSLS     r2,r0,#30             ;70
000084  d5dd              BPL      |L23.66|
000086  05c2              LSLS     r2,r0,#23             ;73
000088  d50a              BPL      |L23.160|
00008a  68a2              LDR      r2,[r4,#8]            ;73
00008c  07d2              LSLS     r2,r2,#31             ;73
00008e  d007              BEQ      |L23.160|
000090  6809              LDR      r1,[r1,#0]            ;75  ; I2SHandler
000092  2900              CMP      r1,#0                 ;75
000094  d000              BEQ      |L23.152|
000096  4788              BLX      r1                    ;76
                  |L23.152|
000098  68e0              LDR      r0,[r4,#0xc]          ;78
00009a  21ff              MOVS     r1,#0xff              ;78
00009c  3101              ADDS     r1,#1                 ;78
00009e  e7ce              B        |L23.62|
                  |L23.160|
0000a0  0582              LSLS     r2,r0,#22             ;81
0000a2  d50a              BPL      |L23.186|
0000a4  68a2              LDR      r2,[r4,#8]            ;81
0000a6  0792              LSLS     r2,r2,#30             ;81
0000a8  d507              BPL      |L23.186|
0000aa  6849              LDR      r1,[r1,#4]            ;83  ; I2SHandler
0000ac  2900              CMP      r1,#0                 ;83
0000ae  d000              BEQ      |L23.178|
0000b0  4788              BLX      r1                    ;84
                  |L23.178|
0000b2  68e0              LDR      r0,[r4,#0xc]          ;86
0000b4  2101              MOVS     r1,#1                 ;86
0000b6  0249              LSLS     r1,r1,#9              ;86
0000b8  e7c1              B        |L23.62|
                  |L23.186|
0000ba  68a2              LDR      r2,[r4,#8]            ;89
0000bc  0752              LSLS     r2,r2,#29             ;89
0000be  d5c0              BPL      |L23.66|
0000c0  6889              LDR      r1,[r1,#8]            ;91  ; I2SHandler
                  |L23.194|
0000c2  2900              CMP      r1,#0                 ;66
0000c4  d0bd              BEQ      |L23.66|
0000c6  4788              BLX      r1                    ;92
0000c8  bd10              POP      {r4,pc}
;;;96     
                          ENDP

0000ca  0000              DCW      0x0000
                  |L23.204|
                          DCD      0x401a0000
                  |L23.208|
                          DCD      ||.bss||

                          AREA ||.bss||, DATA, NOINIT, ALIGN=2

                  I2SHandler
                          %        32

                          AREA ||i.__ARM_common_switch8||, COMGROUP=__ARM_common_switch8, CODE, READONLY, ALIGN=1

                  __ARM_common_switch8 PROC
000000  b430              PUSH     {r4,r5}
000002  4674              MOV      r4,lr
000004  1e64              SUBS     r4,r4,#1
000006  7825              LDRB     r5,[r4,#0]
000008  1c64              ADDS     r4,r4,#1
00000a  42ab              CMP      r3,r5
00000c  d200              BCS      |L147.16|
00000e  461d              MOV      r5,r3
                  |L147.16|
000010  5d63              LDRB     r3,[r4,r5]
000012  005b              LSLS     r3,r3,#1
000014  18e3              ADDS     r3,r4,r3
000016  bc30              POP      {r4,r5}
000018  4718              BX       r3
                          ENDP

