; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\drvpwm.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvpwm.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvpwm.crf ..\bsp\Driver\DrvPWM.c]
                          THUMB

                          AREA ||i.DrvPWM_ClearCaptureIntStatus||, CODE, READONLY, ALIGN=2

                  DrvPWM_ClearCaptureIntStatus PROC
;;;540    /*---------------------------------------------------------------------------------------------------------*/
;;;541    void DrvPWM_ClearCaptureIntStatus(uint8_t u8Capture, uint8_t u8IntType)
000000  4602              MOV      r2,r0
;;;542    {
;;;543    	switch (u8Capture)
000002  3a10              SUBS     r2,r2,#0x10
;;;544    	{
;;;545    		case DRVPWM_CAP0:
;;;546    		case DRVPWM_CAP1:
;;;547    		case DRVPWM_CAP2:																  
;;;548    		case DRVPWM_CAP3:
;;;549    			PWM0->CAPINTSTS = u8IntType << ((u8Capture & 0x3) * 8);	
000004  0780              LSLS     r0,r0,#30
000006  b500              PUSH     {lr}                  ;542
000008  0ec0              LSRS     r0,r0,#27
00000a  4081              LSLS     r1,r1,r0
00000c  0013              MOVS     r3,r2                 ;543
00000e  f7fffffe          BL       __ARM_common_switch8
000012  0805              DCB      0x08,0x05
000014  05050507          DCB      0x05,0x05,0x05,0x07
000018  07070709          DCB      0x07,0x07,0x07,0x09
00001c  4802              LDR      r0,|L1.40|
;;;550    			break;
00001e  e000              B        |L1.34|
;;;551    		case DRVPWM_CAP4:
;;;552    		case DRVPWM_CAP5:
;;;553    		case DRVPWM_CAP6:																	  
;;;554    		case DRVPWM_CAP7:
;;;555    			PWM1->CAPINTSTS = u8IntType << ((u8Capture & 0x3) * 8);	
000020  4802              LDR      r0,|L1.44|
                  |L1.34|
000022  61c1              STR      r1,[r0,#0x1c]
;;;556    			break;
;;;557    	}
;;;558    }
000024  bd00              POP      {pc}
;;;559    
                          ENDP

000026  0000              DCW      0x0000
                  |L1.40|
                          DCD      0x40040040
                  |L1.44|
                          DCD      0x40140040

                          AREA ||i.DrvPWM_ClearInt||, CODE, READONLY, ALIGN=2

                  DrvPWM_ClearInt PROC
;;;324    /*---------------------------------------------------------------------------------------------------------*/
;;;325    void DrvPWM_ClearInt(uint8_t u8Timer)
000000  0782              LSLS     r2,r0,#30
;;;326    {
;;;327    	switch (u8Timer)
;;;328    	{
;;;329    		case DRVPWM_TIMER0:
;;;330    		case DRVPWM_TIMER1:
;;;331    		case DRVPWM_TIMER2:
;;;332    		case DRVPWM_TIMER3:
;;;333    		    PWM0->INTSTS = 1 << u8Timer;
;;;334    			break;
;;;335    		case DRVPWM_TIMER4:
;;;336    		case DRVPWM_TIMER5:
;;;337    		case DRVPWM_TIMER6:
;;;338    		case DRVPWM_TIMER7:
;;;339    			PWM1->INTSTS = 1 << (u8Timer & 0x3);
000002  0f92              LSRS     r2,r2,#30
000004  b510              PUSH     {r4,lr}               ;326
;;;340    			break;
;;;341    
;;;342    		case DRVPWM_CAP0:
;;;343    		case DRVPWM_CAP1:
;;;344    		case DRVPWM_CAP2:																  
;;;345    		case DRVPWM_CAP3:
;;;346    			PWM0->CAPINTSTS = 0x7 << ((u8Timer & 0x3) * 8);	
000006  00d3              LSLS     r3,r2,#3
000008  2107              MOVS     r1,#7
00000a  4099              LSLS     r1,r1,r3
00000c  2401              MOVS     r4,#1                 ;333
00000e  0003              MOVS     r3,r0                 ;327
000010  f7fffffe          BL       __ARM_common_switch8
000014  180d0d0d          DCB      0x18,0x0d,0x0d,0x0d
000018  0d101010          DCB      0x0d,0x10,0x10,0x10
00001c  10131313          DCB      0x10,0x13,0x13,0x13
000020  13131313          DCB      0x13,0x13,0x13,0x13
000024  13141414          DCB      0x13,0x14,0x14,0x14
000028  14171717          DCB      0x14,0x17,0x17,0x17
00002c  1713              DCB      0x17,0x13
00002e  4084              LSLS     r4,r4,r0              ;333
000030  4806              LDR      r0,|L2.76|
000032  e001              B        |L2.56|
000034  4806              LDR      r0,|L2.80|
000036  4094              LSLS     r4,r4,r2              ;339
                  |L2.56|
000038  6104              STR      r4,[r0,#0x10]         ;339
;;;347    			break;
;;;348    		case DRVPWM_CAP4:
;;;349    		case DRVPWM_CAP5:
;;;350    		case DRVPWM_CAP6:																	  
;;;351    		case DRVPWM_CAP7:
;;;352    			PWM1->CAPINTSTS = 0x7 << ((u8Timer & 0x3) * 8);	
;;;353    			break;
;;;354    	}
;;;355    }
00003a  bd10              POP      {r4,pc}
00003c  4803              LDR      r0,|L2.76|
00003e  3040              ADDS     r0,r0,#0x40           ;346
000040  e001              B        |L2.70|
000042  4803              LDR      r0,|L2.80|
000044  3040              ADDS     r0,r0,#0x40           ;352
                  |L2.70|
000046  61c1              STR      r1,[r0,#0x1c]         ;352
000048  bd10              POP      {r4,pc}
;;;356    
                          ENDP

00004a  0000              DCW      0x0000
                  |L2.76|
                          DCD      0x40040000
                  |L2.80|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_Close||, CODE, READONLY, ALIGN=2

                  DrvPWM_Close PROC
;;;605    /*---------------------------------------------------------------------------------------------------------*/
;;;606    void DrvPWM_Close(uint8_t u8Timer)
000000  b5f0              PUSH     {r4-r7,lr}
;;;607    {
;;;608        uint8_t set, ch;
;;;609        PWM_TypeDef *base;
;;;610    
;;;611        set = (u8Timer & 0x4) >> 2;
000002  0741              LSLS     r1,r0,#29
000004  0fca              LSRS     r2,r1,#31
;;;612        ch = u8Timer & 0x3;
000006  0781              LSLS     r1,r0,#30
000008  0f89              LSRS     r1,r1,#30
;;;613        base = (set == 0) ? PWM0 : PWM1;
00000a  2a00              CMP      r2,#0
00000c  d017              BEQ      |L3.62|
00000e  4833              LDR      r0,|L3.220|
                  |L3.16|
;;;614    
;;;615    	base->OE &= ~(1 << ch);
000010  6943              LDR      r3,[r0,#0x14]
000012  2701              MOVS     r7,#1
000014  463c              MOV      r4,r7
000016  408c              LSLS     r4,r4,r1
000018  43a3              BICS     r3,r3,r4
00001a  6143              STR      r3,[r0,#0x14]
;;;616    	base->CAPCTL &= ~(0x4 << (8 * ch));
00001c  6d46              LDR      r6,[r0,#0x54]
00001e  00cb              LSLS     r3,r1,#3
000020  2504              MOVS     r5,#4
000022  409d              LSLS     r5,r5,r3
000024  43ae              BICS     r6,r6,r5
000026  6546              STR      r6,[r0,#0x54]
;;;617        base->CAPINTSTS = 0x7 << (ch * 8);
000028  2507              MOVS     r5,#7
00002a  409d              LSLS     r5,r5,r3
00002c  65c5              STR      r5,[r0,#0x5c]
;;;618        base->INTSTS = 1 << ch;	
00002e  6104              STR      r4,[r0,#0x10]
;;;619    
;;;620    	if(!((PWM0->INTEN & 0xF) || (PWM0->CAPINTEN & 0x03030303)))
000030  4b2b              LDR      r3,|L3.224|
000032  68db              LDR      r3,[r3,#0xc]
000034  4c2b              LDR      r4,|L3.228|
000036  4d2c              LDR      r5,|L3.232|
000038  071b              LSLS     r3,r3,#28
00003a  d002              BEQ      |L3.66|
00003c  e008              B        |L3.80|
                  |L3.62|
00003e  4828              LDR      r0,|L3.224|
000040  e7e6              B        |L3.16|
                  |L3.66|
000042  4b27              LDR      r3,|L3.224|
000044  3340              ADDS     r3,r3,#0x40
000046  699b              LDR      r3,[r3,#0x18]
000048  4223              TST      r3,r4
00004a  d101              BNE      |L3.80|
00004c  2340              MOVS     r3,#0x40
00004e  602b              STR      r3,[r5,#0]
                  |L3.80|
;;;621    		NVIC_DisableIRQ(PWM0_IRQn);
;;;622    	if(!((PWM1->INTEN & 0xF) || (PWM1->CAPINTEN & 0x03030303)))
000050  4b22              LDR      r3,|L3.220|
000052  68db              LDR      r3,[r3,#0xc]
000054  071b              LSLS     r3,r3,#28
000056  d106              BNE      |L3.102|
000058  4b20              LDR      r3,|L3.220|
00005a  3340              ADDS     r3,r3,#0x40
00005c  699b              LDR      r3,[r3,#0x18]
00005e  4223              TST      r3,r4
000060  d101              BNE      |L3.102|
000062  2380              MOVS     r3,#0x80
000064  602b              STR      r3,[r5,#0]
                  |L3.102|
;;;623    		NVIC_DisableIRQ(PWM1_IRQn);
;;;624    	
;;;625        ch = (ch >> 1) << 1;
000066  0849              LSRS     r1,r1,#1
;;;626    	if((base->OE &= (1 << ch) == 0) && 
000068  6943              LDR      r3,[r0,#0x14]
00006a  0049              LSLS     r1,r1,#1              ;625
00006c  463c              MOV      r4,r7
00006e  408c              LSLS     r4,r4,r1
000070  d021              BEQ      |L3.182|
000072  2400              MOVS     r4,#0
                  |L3.116|
000074  4023              ANDS     r3,r3,r4
000076  6143              STR      r3,[r0,#0x14]
000078  d028              BEQ      |L3.204|
;;;627           (base->OE &= (1 << (ch + 1)) == 0) &&
00007a  6943              LDR      r3,[r0,#0x14]
00007c  1c4c              ADDS     r4,r1,#1
00007e  40a7              LSLS     r7,r7,r4
000080  d01b              BEQ      |L3.186|
000082  2400              MOVS     r4,#0
                  |L3.132|
000084  4023              ANDS     r3,r3,r4
000086  6143              STR      r3,[r0,#0x14]
000088  d020              BEQ      |L3.204|
;;;628           (base->CAPCTL &= (0x4 << (8 * ch))) &&
00008a  6d45              LDR      r5,[r0,#0x54]
00008c  2304              MOVS     r3,#4
00008e  00cc              LSLS     r4,r1,#3
000090  461e              MOV      r6,r3
000092  40a6              LSLS     r6,r6,r4
000094  4035              ANDS     r5,r5,r6
000096  6545              STR      r5,[r0,#0x54]
000098  d018              BEQ      |L3.204|
;;;629           (base->CAPCTL &= (0x4 << (8 * (ch + 1))))
00009a  3408              ADDS     r4,r4,#8
00009c  40a3              LSLS     r3,r3,r4
00009e  6d44              LDR      r4,[r0,#0x54]
0000a0  4023              ANDS     r3,r3,r4
0000a2  6543              STR      r3,[r0,#0x54]
0000a4  d012              BEQ      |L3.204|
;;;630        ) {
;;;631    		if(set == 0) {
;;;632    			if(ch == 0)
;;;633    				CLK->APBCLK_BITS.PWM0_CH01_EN = 0;
0000a6  4811              LDR      r0,|L3.236|
0000a8  2a00              CMP      r2,#0                 ;631
0000aa  d008              BEQ      |L3.190|
;;;634    			else
;;;635    				CLK->APBCLK_BITS.PWM0_CH23_EN = 0;
;;;636    		} else {
;;;637    			if(ch == 0)
0000ac  2900              CMP      r1,#0
;;;638    				CLK->APBCLK_BITS.PWM1_CH01_EN = 0;
;;;639    			else
;;;640    				CLK->APBCLK_BITS.PWM1_CH23_EN = 0;
0000ae  6881              LDR      r1,[r0,#8]
0000b0  d010              BEQ      |L3.212|
0000b2  0382              LSLS     r2,r0,#14
0000b4  e008              B        |L3.200|
                  |L3.182|
0000b6  2401              MOVS     r4,#1                 ;626
0000b8  e7dc              B        |L3.116|
                  |L3.186|
0000ba  2401              MOVS     r4,#1                 ;627
0000bc  e7e2              B        |L3.132|
                  |L3.190|
0000be  2900              CMP      r1,#0                 ;632
0000c0  6881              LDR      r1,[r0,#8]            ;635
0000c2  d004              BEQ      |L3.206|
0000c4  2201              MOVS     r2,#1                 ;635
0000c6  0552              LSLS     r2,r2,#21             ;635
                  |L3.200|
0000c8  4391              BICS     r1,r1,r2              ;633
0000ca  6081              STR      r1,[r0,#8]            ;633
                  |L3.204|
;;;641    		}
;;;642    	}
;;;643    }
0000cc  bdf0              POP      {r4-r7,pc}
                  |L3.206|
0000ce  2201              MOVS     r2,#1                 ;633
0000d0  0512              LSLS     r2,r2,#20             ;633
0000d2  e7f9              B        |L3.200|
                  |L3.212|
0000d4  2201              MOVS     r2,#1                 ;638
0000d6  0592              LSLS     r2,r2,#22             ;638
0000d8  e7f6              B        |L3.200|
;;;644    
                          ENDP

0000da  0000              DCW      0x0000
                  |L3.220|
                          DCD      0x40140000
                  |L3.224|
                          DCD      0x40040000
                  |L3.228|
                          DCD      0x03030303
                  |L3.232|
                          DCD      0xe000e180
                  |L3.236|
                          DCD      0x50000200

                          AREA ||i.DrvPWM_ConfigCascade||, CODE, READONLY, ALIGN=2

                  DrvPWM_ConfigCascade PROC
;;;1172     */
;;;1173   uint32_t DrvPWM_ConfigCascade(uint8_t u8Capture, uint8_t enable)
000000  0782              LSLS     r2,r0,#30
;;;1174   {
;;;1175   
;;;1176   	switch (u8Capture)
;;;1177   	{
;;;1178   		case DRVPWM_CAP0:
;;;1179   		case DRVPWM_CAP2:								
;;;1180   			if(enable)
;;;1181   				PWM0->CAPCTL |= 0x2000 << (8 * (u8Capture & 0x3));
000002  0ed3              LSRS     r3,r2,#27
000004  2201              MOVS     r2,#1
000006  0352              LSLS     r2,r2,#13
000008  409a              LSLS     r2,r2,r3
00000a  2810              CMP      r0,#0x10              ;1176
00000c  d006              BEQ      |L4.28|
00000e  2812              CMP      r0,#0x12              ;1176
000010  d004              BEQ      |L4.28|
000012  2814              CMP      r0,#0x14              ;1176
000014  d00a              BEQ      |L4.44|
000016  2816              CMP      r0,#0x16              ;1176
000018  d106              BNE      |L4.40|
00001a  e007              B        |L4.44|
                  |L4.28|
00001c  4806              LDR      r0,|L4.56|
00001e  e006              B        |L4.46|
                  |L4.32|
000020  4311              ORRS     r1,r1,r2
000022  e000              B        |L4.38|
                  |L4.36|
;;;1182   			else
;;;1183   				PWM0->CAPCTL &= ~(0x2000 << (8 * (u8Capture & 0x3))); 
000024  4391              BICS     r1,r1,r2
                  |L4.38|
;;;1184   			break;
;;;1185   		case DRVPWM_CAP4:
;;;1186   		case DRVPWM_CAP6:																	  
;;;1187   			if(enable)
;;;1188   				PWM1->CAPCTL |= 0x2000 << (8 * (u8Capture & 0x3));
000026  6141              STR      r1,[r0,#0x14]
                  |L4.40|
;;;1189   			else
;;;1190   				PWM1->CAPCTL &= ~(0x2000 << (8 * (u8Capture & 0x3))); 	
;;;1191   			break;
;;;1192   		default:
;;;1193   			assert_param(0);
;;;1194   	}
;;;1195   	return(0);
000028  2000              MOVS     r0,#0
;;;1196   }
00002a  4770              BX       lr
                  |L4.44|
00002c  4803              LDR      r0,|L4.60|
                  |L4.46|
00002e  2900              CMP      r1,#0                 ;1187
000030  6941              LDR      r1,[r0,#0x14]         ;1183
000032  d0f7              BEQ      |L4.36|
000034  e7f4              B        |L4.32|
;;;1197   
                          ENDP

000036  0000              DCW      0x0000
                  |L4.56|
                          DCD      0x40040040
                  |L4.60|
                          DCD      0x40140040

                          AREA ||i.DrvPWM_Disable||, CODE, READONLY, ALIGN=2

                  DrvPWM_Disable PROC
;;;753    /*---------------------------------------------------------------------------------------------------------*/
;;;754    void DrvPWM_Disable(uint8_t u8Timer)
000000  0741              LSLS     r1,r0,#29
;;;755    {
;;;756    	PWM_TypeDef *base;
;;;757    	base = ((u8Timer & 7) < 4) ? PWM0 : PWM1;
000002  0f49              LSRS     r1,r1,#29
000004  2904              CMP      r1,#4
000006  d201              BCS      |L5.12|
000008  490b              LDR      r1,|L5.56|
00000a  e000              B        |L5.14|
                  |L5.12|
00000c  490b              LDR      r1,|L5.60|
                  |L5.14|
;;;758    	
;;;759    	if (u8Timer & 0x10)
00000e  06c2              LSLS     r2,r0,#27
;;;760    	{
;;;761    		base->CTL &= ~(0x9 << ((u8Timer & 0x3) * 8));
000010  0780              LSLS     r0,r0,#30
000012  0ec0              LSRS     r0,r0,#27
000014  2a00              CMP      r2,#0                 ;759
;;;762    		base->CAPCTL &= ~(2 << ((u8Timer & 0x3) * 8));
;;;763    	} else
;;;764    			base->CTL &= ~(1 << ((u8Timer & 0x3) * 8));
000016  688a              LDR      r2,[r1,#8]
000018  da09              BGE      |L5.46|
00001a  2309              MOVS     r3,#9                 ;761
00001c  4083              LSLS     r3,r3,r0              ;761
00001e  439a              BICS     r2,r2,r3              ;761
000020  608a              STR      r2,[r1,#8]            ;761
000022  6d4a              LDR      r2,[r1,#0x54]         ;762
000024  2302              MOVS     r3,#2                 ;762
000026  4083              LSLS     r3,r3,r0              ;762
000028  439a              BICS     r2,r2,r3              ;762
00002a  654a              STR      r2,[r1,#0x54]         ;762
;;;765    			
;;;766    }
00002c  4770              BX       lr
                  |L5.46|
00002e  2301              MOVS     r3,#1                 ;764
000030  4083              LSLS     r3,r3,r0              ;764
000032  439a              BICS     r2,r2,r3              ;764
000034  608a              STR      r2,[r1,#8]            ;764
000036  4770              BX       lr
;;;767    
                          ENDP

                  |L5.56|
                          DCD      0x40040000
                  |L5.60|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_DisableDeadZone||, CODE, READONLY, ALIGN=2

                  DrvPWM_DisableDeadZone PROC
;;;686    
;;;687    void DrvPWM_DisableDeadZone(uint8_t u8Timer)
000000  b530              PUSH     {r4,r5,lr}
;;;688    {
;;;689    	switch (u8Timer & 0x07)
000002  0744              LSLS     r4,r0,#29
000004  0f64              LSRS     r4,r4,#29
;;;690    	{
;;;691    		case DRVPWM_TIMER0:
;;;692    		case DRVPWM_TIMER1:
;;;693    			PWM0->CTL_BITS.DZEN01 = 0;
000006  480d              LDR      r0,|L6.60|
000008  2210              MOVS     r2,#0x10
;;;694    			break;
;;;695    		case DRVPWM_TIMER2:
;;;696    		case DRVPWM_TIMER3:
;;;697    			PWM0->CTL_BITS.DZEN23 = 0;
00000a  2520              MOVS     r5,#0x20
;;;698    			break;
;;;699    		case DRVPWM_TIMER4:
;;;700    		case DRVPWM_TIMER5:
;;;701    			PWM1->CTL_BITS.DZEN01 = 0;
00000c  490c              LDR      r1,|L6.64|
00000e  0023              MOVS     r3,r4                 ;689
000010  f7fffffe          BL       __ARM_common_switch8
000014  08050508          DCB      0x08,0x05,0x05,0x08
000018  080c0c0f          DCB      0x08,0x0c,0x0c,0x0f
00001c  0f0b              DCB      0x0f,0x0b
00001e  6881              LDR      r1,[r0,#8]            ;693
000020  4391              BICS     r1,r1,r2              ;693
000022  e001              B        |L6.40|
000024  6881              LDR      r1,[r0,#8]            ;697
000026  43a9              BICS     r1,r1,r5              ;697
                  |L6.40|
000028  6081              STR      r1,[r0,#8]            ;697
;;;702    			break;
;;;703    		case DRVPWM_TIMER6:
;;;704    		case DRVPWM_TIMER7:
;;;705    			PWM1->CTL_BITS.DZEN23 = 0;
;;;706    			break;
;;;707    	} 	
;;;708    }
00002a  bd30              POP      {r4,r5,pc}
00002c  6888              LDR      r0,[r1,#8]            ;701
00002e  4390              BICS     r0,r0,r2              ;701
000030  e001              B        |L6.54|
000032  6888              LDR      r0,[r1,#8]            ;705
000034  43a8              BICS     r0,r0,r5              ;705
                  |L6.54|
000036  6088              STR      r0,[r1,#8]            ;705
000038  bd30              POP      {r4,r5,pc}
;;;709    
                          ENDP

00003a  0000              DCW      0x0000
                  |L6.60|
                          DCD      0x40040000
                  |L6.64|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_DisableInt||, CODE, READONLY, ALIGN=2

                  DrvPWM_DisableInt PROC
;;;282    /*---------------------------------------------------------------------------------------------------------*/
;;;283    void DrvPWM_DisableInt(uint8_t u8Timer)
000000  b5f0              PUSH     {r4-r7,lr}
;;;284    {   	
;;;285    	PWM_TypeDef *base;
;;;286    	uint8_t ch;
;;;287    	
;;;288    	base = ((u8Timer & 0x7) < 4) ? PWM0 : PWM1;
000002  0741              LSLS     r1,r0,#29
000004  0f49              LSRS     r1,r1,#29
000006  4c17              LDR      r4,|L7.100|
000008  2904              CMP      r1,#4
00000a  d201              BCS      |L7.16|
00000c  4621              MOV      r1,r4
00000e  e000              B        |L7.18|
                  |L7.16|
000010  4915              LDR      r1,|L7.104|
                  |L7.18|
;;;289    	ch = u8Timer & 0x3;	
000012  0782              LSLS     r2,r0,#30
;;;290    	
;;;291    	if(u8Timer & 0x10) { // capture
000014  06c5              LSLS     r5,r0,#27
000016  0780              LSLS     r0,r0,#30             ;289
000018  0f92              LSRS     r2,r2,#30             ;289
;;;292    		base->CAPINTEN &= ~(0x3 << (ch * 8));	
;;;293    		base->CAPINTSTS = 0x7 << (ch * 8);	
;;;294    		if(base == PWM0)
;;;295    			g_sDrvPWM0Handler.pfnCAPCallBack[ch] = NULL;
00001a  4f14              LDR      r7,|L7.108|
00001c  2300              MOVS     r3,#0
00001e  0f00              LSRS     r0,r0,#28
000020  2d00              CMP      r5,#0                 ;291
000022  da11              BGE      |L7.72|
000024  6d8d              LDR      r5,[r1,#0x58]         ;292
000026  00d2              LSLS     r2,r2,#3              ;292
000028  2603              MOVS     r6,#3                 ;292
00002a  4096              LSLS     r6,r6,r2              ;292
00002c  43b5              BICS     r5,r5,r6              ;292
00002e  658d              STR      r5,[r1,#0x58]         ;292
000030  2507              MOVS     r5,#7                 ;293
000032  4095              LSLS     r5,r5,r2              ;293
000034  65cd              STR      r5,[r1,#0x5c]         ;293
000036  42a1              CMP      r1,r4                 ;294
000038  d101              BNE      |L7.62|
00003a  19c0              ADDS     r0,r0,r7
00003c  e002              B        |L7.68|
                  |L7.62|
;;;296    		else
;;;297    			g_sDrvPWM1Handler.pfnCAPCallBack[ch] = NULL;		
00003e  490b              LDR      r1,|L7.108|
000040  3120              ADDS     r1,r1,#0x20
000042  1840              ADDS     r0,r0,r1
                  |L7.68|
000044  6103              STR      r3,[r0,#0x10]
;;;298    
;;;299    	} else {
;;;300    		base->INTEN &= ~(1 << ch);
;;;301    		base->INTSTS = 1 << ch;
;;;302    		if(base == PWM0)
;;;303    			g_sDrvPWM0Handler.pfnPWMCallBack[ch] = NULL;
;;;304    		else
;;;305    			g_sDrvPWM1Handler.pfnPWMCallBack[ch] = NULL;		
;;;306    	}	
;;;307    	
;;;308    }
000046  bdf0              POP      {r4-r7,pc}
                  |L7.72|
000048  68ce              LDR      r6,[r1,#0xc]          ;300
00004a  2501              MOVS     r5,#1                 ;300
00004c  4095              LSLS     r5,r5,r2              ;300
00004e  43ae              BICS     r6,r6,r5              ;300
000050  60ce              STR      r6,[r1,#0xc]          ;300
000052  610d              STR      r5,[r1,#0x10]         ;301
000054  42a1              CMP      r1,r4                 ;302
000056  d101              BNE      |L7.92|
000058  503b              STR      r3,[r7,r0]            ;303
00005a  bdf0              POP      {r4-r7,pc}
                  |L7.92|
00005c  4903              LDR      r1,|L7.108|
00005e  3120              ADDS     r1,r1,#0x20           ;305
000060  500b              STR      r3,[r1,r0]            ;305
000062  bdf0              POP      {r4-r7,pc}
;;;309    
                          ENDP

                  |L7.100|
                          DCD      0x40040000
                  |L7.104|
                          DCD      0x40140000
                  |L7.108|
                          DCD      ||.bss||

                          AREA ||i.DrvPWM_DisablePdma||, CODE, READONLY, ALIGN=2

                  DrvPWM_DisablePdma PROC
;;;1239     */
;;;1240   int32_t DrvPWM_DisablePdma(uint8_t u8Capture)
000000  0741              LSLS     r1,r0,#29
;;;1241   {
;;;1242       PWM_TypeDef *base;
;;;1243   	uint8_t set, ch;
;;;1244   	
;;;1245   	assert_param((u8Capture & 0x10) != 0);
;;;1246   
;;;1247   	set = (u8Capture & 0x4) >> 2;
000002  0fca              LSRS     r2,r1,#31
;;;1248   	ch = u8Capture & 0x3;
000004  0781              LSLS     r1,r0,#30
000006  0f89              LSRS     r1,r1,#30
;;;1249   
;;;1250   
;;;1251       if(set == 0) 
000008  2a00              CMP      r2,#0
00000a  d008              BEQ      |L8.30|
;;;1252           base = PWM0;
;;;1253       else
;;;1254           base = PWM1;
00000c  4805              LDR      r0,|L8.36|
                  |L8.14|
;;;1255   
;;;1256       base->CAPCTL &= ~(0x8 << (ch * 8));
00000e  6d42              LDR      r2,[r0,#0x54]
000010  00cb              LSLS     r3,r1,#3
000012  2108              MOVS     r1,#8
000014  4099              LSLS     r1,r1,r3
000016  438a              BICS     r2,r2,r1
000018  6542              STR      r2,[r0,#0x54]
;;;1257   
;;;1258       return(0);                    
00001a  2000              MOVS     r0,#0
;;;1259   }
00001c  4770              BX       lr
                  |L8.30|
00001e  4802              LDR      r0,|L8.40|
000020  e7f5              B        |L8.14|
;;;1260   
                          ENDP

000022  0000              DCW      0x0000
                  |L8.36|
                          DCD      0x40140000
                  |L8.40|
                          DCD      0x40040000

                          AREA ||i.DrvPWM_Enable||, CODE, READONLY, ALIGN=2

                  DrvPWM_Enable PROC
;;;724    /*---------------------------------------------------------------------------------------------------------*/
;;;725    void DrvPWM_Enable(uint8_t u8Timer)
000000  0741              LSLS     r1,r0,#29
;;;726    {
;;;727    	PWM_TypeDef *base;
;;;728    	base = ((u8Timer & 7) < 4) ? PWM0 : PWM1;
000002  0f49              LSRS     r1,r1,#29
000004  2904              CMP      r1,#4
000006  d201              BCS      |L9.12|
000008  490b              LDR      r1,|L9.56|
00000a  e000              B        |L9.14|
                  |L9.12|
00000c  490b              LDR      r1,|L9.60|
                  |L9.14|
;;;729    	
;;;730    	if (u8Timer & 0x10)
00000e  06c2              LSLS     r2,r0,#27
;;;731    	{
;;;732    		base->CTL |= (0x9 << ((u8Timer & 0x3) * 8));
000010  0780              LSLS     r0,r0,#30
000012  0ec0              LSRS     r0,r0,#27
000014  2a00              CMP      r2,#0                 ;730
;;;733    		base->CAPCTL |= (2 << ((u8Timer & 0x3) * 8));
;;;734    	} else
;;;735    		base->CTL |= (1 << ((u8Timer & 0x3) * 8));
000016  688a              LDR      r2,[r1,#8]
000018  da09              BGE      |L9.46|
00001a  2309              MOVS     r3,#9                 ;732
00001c  4083              LSLS     r3,r3,r0              ;732
00001e  431a              ORRS     r2,r2,r3              ;732
000020  608a              STR      r2,[r1,#8]            ;732
000022  6d4a              LDR      r2,[r1,#0x54]         ;733
000024  2302              MOVS     r3,#2                 ;733
000026  4083              LSLS     r3,r3,r0              ;733
000028  431a              ORRS     r2,r2,r3              ;733
00002a  654a              STR      r2,[r1,#0x54]         ;733
;;;736    			
;;;737    }
00002c  4770              BX       lr
                  |L9.46|
00002e  2301              MOVS     r3,#1                 ;735
000030  4083              LSLS     r3,r3,r0              ;735
000032  431a              ORRS     r2,r2,r3              ;735
000034  608a              STR      r2,[r1,#8]            ;735
000036  4770              BX       lr
;;;738    
                          ENDP

                  |L9.56|
                          DCD      0x40040000
                  |L9.60|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_EnableDeadZone||, CODE, READONLY, ALIGN=2

                  DrvPWM_EnableDeadZone PROC
;;;659    /*---------------------------------------------------------------------------------------------------------*/
;;;660    void DrvPWM_EnableDeadZone(uint8_t u8Timer, uint8_t u8Length)
000000  b5f0              PUSH     {r4-r7,lr}
;;;661    {
;;;662    	switch (u8Timer & 0x07)
000002  0745              LSLS     r5,r0,#29
000004  0f6d              LSRS     r5,r5,#29
;;;663    	{
;;;664    		case DRVPWM_TIMER0:
;;;665    		case DRVPWM_TIMER1:
;;;666    			PWM0->PRES_BITS.DZ01  = u8Length;
000006  24ff              MOVS     r4,#0xff
000008  4e17              LDR      r6,|L10.104|
00000a  0424              LSLS     r4,r4,#16
00000c  0408              LSLS     r0,r1,#16
;;;667    			PWM0->CTL_BITS.DZEN01 = 1;
00000e  2710              MOVS     r7,#0x10
;;;668    			break;
;;;669    		case DRVPWM_TIMER2:
;;;670    		case DRVPWM_TIMER3:
;;;671    			PWM0->PRES_BITS.DZ23  = u8Length;
;;;672    			PWM0->CTL_BITS.DZEN23 = 1;
;;;673    			break;
;;;674    		case DRVPWM_TIMER4:
;;;675    		case DRVPWM_TIMER5:
;;;676    			PWM1->PRES_BITS.DZ01  = u8Length;
000010  4a16              LDR      r2,|L10.108|
000012  002b              MOVS     r3,r5                 ;662
000014  f7fffffe          BL       __ARM_common_switch8
000018  0805050c          DCB      0x08,0x05,0x05,0x0c
00001c  0c17171e          DCB      0x0c,0x17,0x17,0x1e
000020  1e16              DCB      0x1e,0x16
000022  6831              LDR      r1,[r6,#0]            ;666
000024  43a1              BICS     r1,r1,r4              ;666
000026  4301              ORRS     r1,r1,r0              ;666
000028  6031              STR      r1,[r6,#0]            ;666
00002a  68b0              LDR      r0,[r6,#8]            ;667
00002c  4338              ORRS     r0,r0,r7              ;667
00002e  e008              B        |L10.66|
000030  6830              LDR      r0,[r6,#0]            ;671
000032  0200              LSLS     r0,r0,#8              ;671
000034  0a00              LSRS     r0,r0,#8              ;671
000036  0609              LSLS     r1,r1,#24             ;671
000038  4308              ORRS     r0,r0,r1              ;671
00003a  6030              STR      r0,[r6,#0]            ;671
00003c  68b0              LDR      r0,[r6,#8]            ;672
00003e  2120              MOVS     r1,#0x20              ;672
000040  4308              ORRS     r0,r0,r1              ;672
                  |L10.66|
000042  60b0              STR      r0,[r6,#8]            ;672
;;;677    			PWM1->CTL_BITS.DZEN01 = 1;
;;;678    			break;
;;;679    		case DRVPWM_TIMER6:
;;;680    		case DRVPWM_TIMER7:
;;;681    			PWM1->PRES_BITS.DZ01  = u8Length;
;;;682    			PWM1->CTL_BITS.DZEN23 = 1;
;;;683    			break;
;;;684    	} 	
;;;685    }
000044  bdf0              POP      {r4-r7,pc}
000046  6811              LDR      r1,[r2,#0]            ;676
000048  43a1              BICS     r1,r1,r4              ;676
00004a  4301              ORRS     r1,r1,r0              ;676
00004c  6011              STR      r1,[r2,#0]            ;676
00004e  6890              LDR      r0,[r2,#8]            ;677
000050  4338              ORRS     r0,r0,r7              ;677
000052  e006              B        |L10.98|
000054  6811              LDR      r1,[r2,#0]            ;681
000056  43a1              BICS     r1,r1,r4              ;681
000058  4301              ORRS     r1,r1,r0              ;681
00005a  6011              STR      r1,[r2,#0]            ;681
00005c  6890              LDR      r0,[r2,#8]            ;682
00005e  2120              MOVS     r1,#0x20              ;682
000060  4308              ORRS     r0,r0,r1              ;682
                  |L10.98|
000062  6090              STR      r0,[r2,#8]            ;682
000064  bdf0              POP      {r4-r7,pc}
;;;686    
                          ENDP

000066  0000              DCW      0x0000
                  |L10.104|
                          DCD      0x40040000
                  |L10.108|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_EnableInt||, CODE, READONLY, ALIGN=2

                  DrvPWM_EnableInt PROC
;;;233    /*---------------------------------------------------------------------------------------------------------*/
;;;234    void DrvPWM_EnableInt(uint8_t u8Timer, uint8_t u8Int, PFN_DRVPWM_CALLBACK pfncallback)
000000  b5f0              PUSH     {r4-r7,lr}
;;;235    {
000002  468c              MOV      r12,r1
;;;236    	PWM_TypeDef *base;
;;;237    	uint8_t ch;
;;;238    	
;;;239    	base = ((u8Timer & 0x7) < 4) ? PWM0 : PWM1;
000004  0743              LSLS     r3,r0,#29
000006  0f5b              LSRS     r3,r3,#29
000008  491c              LDR      r1,|L11.124|
00000a  2b04              CMP      r3,#4
00000c  d201              BCS      |L11.18|
00000e  460b              MOV      r3,r1
000010  e000              B        |L11.20|
                  |L11.18|
000012  4b1b              LDR      r3,|L11.128|
                  |L11.20|
;;;240    	ch = u8Timer & 0x3;
000014  0785              LSLS     r5,r0,#30
000016  0784              LSLS     r4,r0,#30
000018  0fad              LSRS     r5,r5,#30
;;;241    
;;;242    	
;;;243    	if(u8Timer & 0x10) { // capture
00001a  06c6              LSLS     r6,r0,#27
;;;244    		base->CAPINTSTS = 0x7 << (ch * 8);
;;;245    		base->CAPINTEN &= ~(0x3 << (ch * 8));
;;;246    		base->CAPINTEN |= ((u8Int) << (ch * 8));	
;;;247    		if(base == PWM0)
;;;248    			g_sDrvPWM0Handler.pfnCAPCallBack[ch] = pfncallback;
00001c  0f24              LSRS     r4,r4,#28
;;;249    		else
;;;250    			g_sDrvPWM1Handler.pfnCAPCallBack[ch] = pfncallback;		
;;;251    
;;;252    	} else {
;;;253    		base->INTSTS = 1 << ch;
00001e  2701              MOVS     r7,#1
000020  2e00              CMP      r6,#0                 ;243
000022  da16              BGE      |L11.82|
000024  00ed              LSLS     r5,r5,#3              ;244
000026  2607              MOVS     r6,#7                 ;244
000028  40ae              LSLS     r6,r6,r5              ;244
00002a  65de              STR      r6,[r3,#0x5c]         ;244
00002c  6d9e              LDR      r6,[r3,#0x58]         ;245
00002e  2703              MOVS     r7,#3                 ;245
000030  40af              LSLS     r7,r7,r5              ;245
000032  43be              BICS     r6,r6,r7              ;245
000034  659e              STR      r6,[r3,#0x58]         ;245
000036  6d9e              LDR      r6,[r3,#0x58]         ;246
000038  4667              MOV      r7,r12                ;246
00003a  40af              LSLS     r7,r7,r5              ;246
00003c  433e              ORRS     r6,r6,r7              ;246
00003e  659e              STR      r6,[r3,#0x58]         ;246
000040  428b              CMP      r3,r1                 ;247
000042  d101              BNE      |L11.72|
000044  490f              LDR      r1,|L11.132|
000046  e001              B        |L11.76|
                  |L11.72|
000048  490e              LDR      r1,|L11.132|
00004a  3120              ADDS     r1,r1,#0x20           ;250
                  |L11.76|
00004c  1861              ADDS     r1,r4,r1              ;248
00004e  610a              STR      r2,[r1,#0x10]         ;248
000050  e00b              B        |L11.106|
                  |L11.82|
000052  40af              LSLS     r7,r7,r5
000054  611f              STR      r7,[r3,#0x10]
;;;254    		base->INTEN |= 1 << ch;	
000056  68dd              LDR      r5,[r3,#0xc]
000058  433d              ORRS     r5,r5,r7
00005a  60dd              STR      r5,[r3,#0xc]
;;;255    		if(base == PWM0)
00005c  428b              CMP      r3,r1
00005e  d101              BNE      |L11.100|
;;;256    			g_sDrvPWM0Handler.pfnPWMCallBack[ch] = pfncallback;
000060  4908              LDR      r1,|L11.132|
000062  e001              B        |L11.104|
                  |L11.100|
;;;257    		else
;;;258    			g_sDrvPWM1Handler.pfnPWMCallBack[ch] = pfncallback;		
000064  4907              LDR      r1,|L11.132|
000066  3120              ADDS     r1,r1,#0x20
                  |L11.104|
000068  510a              STR      r2,[r1,r4]            ;256
                  |L11.106|
;;;259    	}
;;;260    		
;;;261    		
;;;262    	if (u8Timer & 0x04)
00006a  0741              LSLS     r1,r0,#29
00006c  4806              LDR      r0,|L11.136|
00006e  d501              BPL      |L11.116|
000070  2180              MOVS     r1,#0x80
;;;263    		NVIC_EnableIRQ(PWM1_IRQn);
000072  e000              B        |L11.118|
                  |L11.116|
000074  2140              MOVS     r1,#0x40
                  |L11.118|
000076  6001              STR      r1,[r0,#0]
;;;264    	else
;;;265    		NVIC_EnableIRQ(PWM0_IRQn);			 
;;;266    }
000078  bdf0              POP      {r4-r7,pc}
;;;267    
                          ENDP

00007a  0000              DCW      0x0000
                  |L11.124|
                          DCD      0x40040000
                  |L11.128|
                          DCD      0x40140000
                  |L11.132|
                          DCD      ||.bss||
                  |L11.136|
                          DCD      0xe000e100

                          AREA ||i.DrvPWM_EnablePdma||, CODE, READONLY, ALIGN=2

                  DrvPWM_EnablePdma PROC
;;;1206     */
;;;1207   int32_t DrvPWM_EnablePdma(uint8_t u8Capture, E_PWM_CAP_ORDER order, E_PWM_CAP_MODE mode)
000000  b530              PUSH     {r4,r5,lr}
;;;1208   {
;;;1209       PWM_TypeDef *base;
;;;1210   	uint8_t set, ch;
;;;1211   	
;;;1212   	assert_param((u8Capture & 0x10) != 0)
;;;1213   
;;;1214   	set = (u8Capture & 0x4) >> 2;
000002  0743              LSLS     r3,r0,#29
;;;1215   	ch = u8Capture & 0x3;
000004  0784              LSLS     r4,r0,#30
000006  0fdb              LSRS     r3,r3,#31             ;1214
000008  0fa4              LSRS     r4,r4,#30
;;;1216   	
;;;1217       if(set == 0) 
00000a  2b00              CMP      r3,#0
00000c  d01d              BEQ      |L12.74|
;;;1218           base = PWM0;
;;;1219       else
;;;1220           base = PWM1;
00000e  4810              LDR      r0,|L12.80|
                  |L12.16|
;;;1221   
;;;1222      
;;;1223       base->CAPCTL &= ~((0x1000) << (ch * 8));          
000010  6d45              LDR      r5,[r0,#0x54]
000012  00e3              LSLS     r3,r4,#3
000014  2401              MOVS     r4,#1
000016  0324              LSLS     r4,r4,#12
000018  409c              LSLS     r4,r4,r3
00001a  43a5              BICS     r5,r5,r4
00001c  6545              STR      r5,[r0,#0x54]
;;;1224       base->CAPCTL |= (order << 12) << (ch * 8);
00001e  6d44              LDR      r4,[r0,#0x54]
000020  4099              LSLS     r1,r1,r3
000022  0309              LSLS     r1,r1,#12
000024  430c              ORRS     r4,r4,r1
000026  6544              STR      r4,[r0,#0x54]
;;;1225       base->CAPCTL &= ~((0x30) << (ch * 8));  
000028  6d41              LDR      r1,[r0,#0x54]
00002a  2430              MOVS     r4,#0x30
00002c  409c              LSLS     r4,r4,r3
00002e  43a1              BICS     r1,r1,r4
000030  6541              STR      r1,[r0,#0x54]
;;;1226       base->CAPCTL |= (mode << 4) << (ch * 8); 
000032  6d41              LDR      r1,[r0,#0x54]
000034  409a              LSLS     r2,r2,r3
000036  0112              LSLS     r2,r2,#4
000038  4311              ORRS     r1,r1,r2
00003a  6541              STR      r1,[r0,#0x54]
;;;1227       base->CAPCTL |= 0x8 << (ch * 8);        
00003c  6d41              LDR      r1,[r0,#0x54]
00003e  2208              MOVS     r2,#8
000040  409a              LSLS     r2,r2,r3
000042  4311              ORRS     r1,r1,r2
000044  6541              STR      r1,[r0,#0x54]
;;;1228   
;;;1229       return(0);                    
000046  2000              MOVS     r0,#0
;;;1230   }
000048  bd30              POP      {r4,r5,pc}
                  |L12.74|
00004a  4802              LDR      r0,|L12.84|
00004c  e7e0              B        |L12.16|
;;;1231   
                          ENDP

00004e  0000              DCW      0x0000
                  |L12.80|
                          DCD      0x40140000
                  |L12.84|
                          DCD      0x40040000

                          AREA ||i.DrvPWM_GetCaptureIntStatus||, CODE, READONLY, ALIGN=2

                  DrvPWM_GetCaptureIntStatus PROC
;;;481    /*---------------------------------------------------------------------------------------------------------*/
;;;482    int32_t DrvPWM_GetCaptureIntStatus(uint8_t u8Capture, uint8_t u8IntType)
000000  b530              PUSH     {r4,r5,lr}
;;;483    {	
000002  4605              MOV      r5,r0
;;;484    	int32_t status;
;;;485    
;;;486    	status = 0;	
;;;487    
;;;488    	switch (u8Capture)
000004  3d10              SUBS     r5,r5,#0x10
000006  2000              MOVS     r0,#0                 ;486
;;;489    	{
;;;490    		case DRVPWM_CAP0:
;;;491    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM0->CAPINTSTS_BITS.CRLI0 : 
000008  4a1b              LDR      r2,|L13.120|
;;;492    															PWM0->CAPINTSTS_BITS.CFLI0;
;;;493    			break;
;;;494    		case DRVPWM_CAP1:
;;;495    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM0->CAPINTSTS_BITS.CRLI1 :
;;;496    															PWM0->CAPINTSTS_BITS.CFLI1;
;;;497    			break;
;;;498    		case DRVPWM_CAP2:
;;;499    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM0->CAPINTSTS_BITS.CRLI2 :
;;;500    															PWM0->CAPINTSTS_BITS.CFLI2;
;;;501    			break;																	  
;;;502    		case DRVPWM_CAP3:
;;;503    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM0->CAPINTSTS_BITS.CRLI3 :
;;;504    															PWM0->CAPINTSTS_BITS.CFLI3;
;;;505    			break;
;;;506    		case DRVPWM_CAP4:
;;;507    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM1->CAPINTSTS_BITS.CRLI0 :
00000a  4c1c              LDR      r4,|L13.124|
00000c  002b              MOVS     r3,r5                 ;488
00000e  f7fffffe          BL       __ARM_common_switch8
000012  0805              DCB      0x08,0x05
000014  0b0f1317          DCB      0x0b,0x0f,0x13,0x17
000018  1e252c0a          DCB      0x1e,0x25,0x2c,0x0a
00001c  69d0              LDR      r0,[r2,#0x1c]         ;492
00001e  2902              CMP      r1,#2                 ;491
000020  d011              BEQ      |L13.70|
000022  e012              B        |L13.74|
                  |L13.36|
000024  0fc0              LSRS     r0,r0,#31             ;492
;;;508    															PWM1->CAPINTSTS_BITS.CFLI0;
;;;509    			break;
;;;510    		case DRVPWM_CAP5:
;;;511    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM1->CAPINTSTS_BITS.CRLI1 :
;;;512    															PWM1->CAPINTSTS_BITS.CFLI1;
;;;513    			break;
;;;514    		case DRVPWM_CAP6:
;;;515    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM1->CAPINTSTS_BITS.CRLI2 :
;;;516    															PWM1->CAPINTSTS_BITS.CFLI2;
;;;517    			break;																	  
;;;518    		case DRVPWM_CAP7:
;;;519    			status = (u8IntType == DRVPWM_CAP_RISING_FLAG)? PWM1->CAPINTSTS_BITS.CRLI3 :
;;;520    															PWM1->CAPINTSTS_BITS.CFLI3;
;;;521    			break;
;;;522    	}
;;;523    	
;;;524    	return status;
;;;525    }
000026  bd30              POP      {r4,r5,pc}
000028  69d0              LDR      r0,[r2,#0x1c]         ;496
00002a  2902              CMP      r1,#2                 ;495
00002c  d012              BEQ      |L13.84|
00002e  e013              B        |L13.88|
000030  69d0              LDR      r0,[r2,#0x1c]         ;500
000032  2902              CMP      r1,#2                 ;499
000034  d015              BEQ      |L13.98|
000036  e016              B        |L13.102|
000038  69d0              LDR      r0,[r2,#0x1c]         ;504
00003a  2902              CMP      r1,#2                 ;503
00003c  d018              BEQ      |L13.112|
00003e  e019              B        |L13.116|
000040  69e0              LDR      r0,[r4,#0x1c]         ;508
000042  2902              CMP      r1,#2                 ;507
000044  d101              BNE      |L13.74|
                  |L13.70|
000046  0780              LSLS     r0,r0,#30             ;507
000048  e7ec              B        |L13.36|
                  |L13.74|
00004a  0740              LSLS     r0,r0,#29             ;508
00004c  e7ea              B        |L13.36|
00004e  69e0              LDR      r0,[r4,#0x1c]         ;512
000050  2902              CMP      r1,#2                 ;511
000052  d101              BNE      |L13.88|
                  |L13.84|
000054  0580              LSLS     r0,r0,#22             ;511
000056  e7e5              B        |L13.36|
                  |L13.88|
000058  0540              LSLS     r0,r0,#21             ;512
00005a  e7e3              B        |L13.36|
00005c  69e0              LDR      r0,[r4,#0x1c]         ;516
00005e  2902              CMP      r1,#2                 ;515
000060  d101              BNE      |L13.102|
                  |L13.98|
000062  0380              LSLS     r0,r0,#14             ;515
000064  e7de              B        |L13.36|
                  |L13.102|
000066  0340              LSLS     r0,r0,#13             ;516
000068  e7dc              B        |L13.36|
00006a  69e0              LDR      r0,[r4,#0x1c]         ;520
00006c  2902              CMP      r1,#2                 ;519
00006e  d101              BNE      |L13.116|
                  |L13.112|
000070  0180              LSLS     r0,r0,#6              ;519
000072  e7d7              B        |L13.36|
                  |L13.116|
000074  0140              LSLS     r0,r0,#5              ;520
000076  e7d5              B        |L13.36|
;;;526    
                          ENDP

                  |L13.120|
                          DCD      0x40040040
                  |L13.124|
                          DCD      0x40140040

                          AREA ||i.DrvPWM_GetFallingCounter||, CODE, READONLY, ALIGN=2

                  DrvPWM_GetFallingCounter PROC
;;;451    /*---------------------------------------------------------------------------------------------------------*/
;;;452    uint32_t DrvPWM_GetFallingCounter(uint8_t u8Capture)
000000  0781              LSLS     r1,r0,#30
;;;453    {
;;;454    	uint32_t u32Reg;
;;;455    	
;;;456    	if (u8Capture >= DRVPWM_CAP4)
;;;457    	{
;;;458    		u32Reg = *(__IO uint32_t *)(&PWM1->CFL0 + 0x2 * (u8Capture & 0x3));
000002  0ec9              LSRS     r1,r1,#27
000004  2814              CMP      r0,#0x14              ;456
000006  d301              BCC      |L14.12|
000008  4802              LDR      r0,|L14.20|
00000a  e000              B        |L14.14|
                  |L14.12|
;;;459    	}
;;;460    	else
;;;461    	{
;;;462    		u32Reg = *(__IO uint32_t *)(&PWM0->CFL0 + 0x2 * (u8Capture & 0x3));
00000c  4802              LDR      r0,|L14.24|
                  |L14.14|
00000e  1808              ADDS     r0,r1,r0              ;458
000010  6a40              LDR      r0,[r0,#0x24]         ;458
;;;463    	}
;;;464    
;;;465    	return u32Reg;
;;;466    }
000012  4770              BX       lr
;;;467    
                          ENDP

                  |L14.20|
                          DCD      0x40140040
                  |L14.24|
                          DCD      0x40040040

                          AREA ||i.DrvPWM_GetIntFlag||, CODE, READONLY, ALIGN=2

                  DrvPWM_GetIntFlag PROC
;;;371    /*---------------------------------------------------------------------------------------------------------*/
;;;372    int32_t DrvPWM_GetIntFlag(uint8_t u8Timer)
000000  b530              PUSH     {r4,r5,lr}
;;;373    {
000002  4602              MOV      r2,r0
;;;374    	int32_t status = 0;
;;;375    	
;;;376    	switch (u8Timer)
;;;377    	{
;;;378    		case DRVPWM_TIMER0:
;;;379    		case DRVPWM_TIMER1:
;;;380    		case DRVPWM_TIMER2:
;;;381    		case DRVPWM_TIMER3:
;;;382    			status = (PWM0->INTSTS & (1 << u8Timer)) ? 1 : 0;
;;;383    			break;
;;;384    		case DRVPWM_TIMER4:
;;;385    		case DRVPWM_TIMER5:
;;;386    		case DRVPWM_TIMER6:
;;;387    		case DRVPWM_TIMER7:
;;;388    			status = (PWM1->INTSTS & (1 << (u8Timer & 0x3))) ? 1 : 0;
000004  0794              LSLS     r4,r2,#30
000006  2501              MOVS     r5,#1                 ;382
000008  0fa4              LSRS     r4,r4,#30
;;;389    			break;
;;;390    		case DRVPWM_CAP0:
;;;391    		case DRVPWM_CAP1:
;;;392    		case DRVPWM_CAP2:																  
;;;393    		case DRVPWM_CAP3:
;;;394    			status = (PWM0->CAPINTSTS & (0x1 << ((u8Timer & 0x3) * 8))) ? 1 : 0;
00000a  00e3              LSLS     r3,r4,#3
00000c  4629              MOV      r1,r5
00000e  4099              LSLS     r1,r1,r3
000010  2000              MOVS     r0,#0                 ;374
000012  0013              MOVS     r3,r2                 ;376
000014  f7fffffe          BL       __ARM_common_switch8
000018  180d0d0d          DCB      0x18,0x0d,0x0d,0x0d
00001c  0d131313          DCB      0x0d,0x13,0x13,0x13
000020  13121212          DCB      0x13,0x12,0x12,0x12
000024  12121212          DCB      0x12,0x12,0x12,0x12
000028  12181818          DCB      0x12,0x18,0x18,0x18
00002c  181b1b1b          DCB      0x18,0x1b,0x1b,0x1b
000030  1b12              DCB      0x1b,0x12
000032  480a              LDR      r0,|L15.92|
000034  6900              LDR      r0,[r0,#0x10]         ;382
000036  4095              LSLS     r5,r5,r2              ;382
000038  e004              B        |L15.68|
                  |L15.58|
00003a  2001              MOVS     r0,#1                 ;382
;;;395    			break;
;;;396    		case DRVPWM_CAP4:
;;;397    		case DRVPWM_CAP5:
;;;398    		case DRVPWM_CAP6:																  
;;;399    		case DRVPWM_CAP7:
;;;400    			status = (PWM1->CAPINTSTS & (0x1 << ((u8Timer & 0x3) * 8))) ? 1 : 0;
;;;401    	 		break;
;;;402    	}	
;;;403    
;;;404    	return status;		
;;;405    }
00003c  bd30              POP      {r4,r5,pc}
00003e  4808              LDR      r0,|L15.96|
000040  6900              LDR      r0,[r0,#0x10]         ;388
000042  40a5              LSLS     r5,r5,r4              ;388
                  |L15.68|
000044  4028              ANDS     r0,r0,r5              ;382
000046  e006              B        |L15.86|
000048  4804              LDR      r0,|L15.92|
00004a  3040              ADDS     r0,r0,#0x40           ;394
00004c  e001              B        |L15.82|
00004e  4804              LDR      r0,|L15.96|
000050  3040              ADDS     r0,r0,#0x40           ;400
                  |L15.82|
000052  69c0              LDR      r0,[r0,#0x1c]         ;394
000054  4008              ANDS     r0,r0,r1              ;394
                  |L15.86|
000056  2800              CMP      r0,#0                 ;394
000058  d1ef              BNE      |L15.58|
00005a  bd30              POP      {r4,r5,pc}
;;;406    
                          ENDP

                  |L15.92|
                          DCD      0x40040000
                  |L15.96|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_GetRisingCounter||, CODE, READONLY, ALIGN=2

                  DrvPWM_GetRisingCounter PROC
;;;421    /*---------------------------------------------------------------------------------------------------------*/
;;;422    uint32_t DrvPWM_GetRisingCounter(uint8_t u8Capture)
000000  0781              LSLS     r1,r0,#30
;;;423    {
;;;424    	uint32_t u32Reg;
;;;425    	
;;;426    	if (u8Capture >= DRVPWM_CAP4)
;;;427    	{
;;;428    		u32Reg = *(__IO uint32_t *)(&PWM1->CRL0 + 0x2 * (u8Capture & 0x3));
000002  0ec9              LSRS     r1,r1,#27
000004  2814              CMP      r0,#0x14              ;426
000006  d301              BCC      |L16.12|
000008  4802              LDR      r0,|L16.20|
00000a  e000              B        |L16.14|
                  |L16.12|
;;;429    	}
;;;430    	else
;;;431    	{
;;;432    		u32Reg = *(__IO uint32_t *)(&PWM0->CRL0 + 0x2 * (u8Capture & 3));
00000c  4802              LDR      r0,|L16.24|
                  |L16.14|
00000e  1808              ADDS     r0,r1,r0              ;428
000010  6a00              LDR      r0,[r0,#0x20]         ;428
;;;433    	}
;;;434    
;;;435    	return u32Reg;
;;;436    }
000012  4770              BX       lr
;;;437    
                          ENDP

                  |L16.20|
                          DCD      0x40140040
                  |L16.24|
                          DCD      0x40040040

                          AREA ||i.DrvPWM_GetTimerCounter||, CODE, READONLY, ALIGN=1

                  DrvPWM_GetTimerCounter PROC
;;;209    /*---------------------------------------------------------------------------------------------------------*/
;;;210    uint32_t DrvPWM_GetTimerCounter(uint8_t u8Timer)
000000  2000              MOVS     r0,#0
;;;211    {
;;;212    	return 0;
;;;213    }
000002  4770              BX       lr
;;;214    
                          ENDP


                          AREA ||i.DrvPWM_GetVersion||, CODE, READONLY, ALIGN=1

                  DrvPWM_GetVersion PROC
;;;33     /*---------------------------------------------------------------------------------------------------------*/
;;;34     uint32_t DrvPWM_GetVersion(void)
000000  2001              MOVS     r0,#1
;;;35     {
;;;36     	return DRVPWM_VERSION_NUM;
000002  0400              LSLS     r0,r0,#16
;;;37     }
000004  4770              BX       lr
;;;38     
                          ENDP


                          AREA ||i.DrvPWM_IsTimerEnabled||, CODE, READONLY, ALIGN=2

                  DrvPWM_IsTimerEnabled PROC
;;;143    /*---------------------------------------------------------------------------------------------------------*/
;;;144    int32_t DrvPWM_IsTimerEnabled(uint8_t u8Timer)
000000  4602              MOV      r2,r0
;;;145    {
000002  b510              PUSH     {r4,lr}
;;;146    	int32_t status;
;;;147    
;;;148    	status = 0;
000004  2000              MOVS     r0,#0
;;;149    	
;;;150    	switch (u8Timer)
;;;151    	{
;;;152    		case DRVPWM_TIMER0:
;;;153    		case DRVPWM_TIMER1:
;;;154    		case DRVPWM_TIMER2:
;;;155    		case DRVPWM_TIMER3:
;;;156    			status = ( inp32(&PWM0->CTL) & (1 << (u8Timer << 3) ) )? 1 : 0;
000006  00d1              LSLS     r1,r2,#3
000008  2401              MOVS     r4,#1
00000a  0013              MOVS     r3,r2                 ;150
00000c  f7fffffe          BL       __ARM_common_switch8
000010  08050505          DCB      0x08,0x05,0x05,0x05
000014  050c0c0c          DCB      0x05,0x0c,0x0c,0x0c
000018  0c0b              DCB      0x0c,0x0b
00001a  4807              LDR      r0,|L19.56|
00001c  6880              LDR      r0,[r0,#8]
00001e  408c              LSLS     r4,r4,r1
000020  4020              ANDS     r0,r0,r4
000022  d000              BEQ      |L19.38|
                  |L19.36|
000024  2001              MOVS     r0,#1
                  |L19.38|
;;;157    			break;		
;;;158    		case DRVPWM_TIMER4:
;;;159    		case DRVPWM_TIMER5:
;;;160    		case DRVPWM_TIMER6:
;;;161    		case DRVPWM_TIMER7:
;;;162    			status = ( inp32(&PWM1->CTL) & (1 << ((u8Timer - 4) << 3) ) )? 1 : 0;
;;;163    			break;	
;;;164    	}
;;;165    	return status;
;;;166    }
000026  bd10              POP      {r4,pc}
000028  4804              LDR      r0,|L19.60|
00002a  3920              SUBS     r1,r1,#0x20           ;162
00002c  6880              LDR      r0,[r0,#8]            ;162
00002e  408c              LSLS     r4,r4,r1              ;162
000030  4204              TST      r4,r0                 ;162
000032  d1f7              BNE      |L19.36|
000034  2000              MOVS     r0,#0                 ;162
000036  bd10              POP      {r4,pc}
;;;167    
                          ENDP

                  |L19.56|
                          DCD      0x40040000
                  |L19.60|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_Open||, CODE, READONLY, ALIGN=2

                  DrvPWM_Open PROC
;;;571    /*---------------------------------------------------------------------------------------------------------*/
;;;572    void DrvPWM_Open(uint8_t u8Timer)
000000  0741              LSLS     r1,r0,#29
;;;573    { 
;;;574        uint8_t set, ch;
;;;575    
;;;576        set = (u8Timer & 0x4) >> 2;
000002  0fca              LSRS     r2,r1,#31
;;;577        ch = u8Timer & 0x3;
000004  0780              LSLS     r0,r0,#30
000006  0f80              LSRS     r0,r0,#30
;;;578    
;;;579    	if(set == 0) {
;;;580    		if(ch < 2) {
;;;581    			CLK->APBCLK_BITS.PWM0_CH01_EN = 1;
000008  490a              LDR      r1,|L20.52|
00000a  2a00              CMP      r2,#0                 ;579
00000c  d004              BEQ      |L20.24|
;;;582    		} else {
;;;583    			CLK->APBCLK_BITS.PWM0_CH23_EN = 1;
;;;584    		}
;;;585    	} else {	
;;;586    		if(ch < 2) {
00000e  2802              CMP      r0,#2
;;;587    			CLK->APBCLK_BITS.PWM1_CH01_EN = 1;
;;;588    		} else {
;;;589    			CLK->APBCLK_BITS.PWM1_CH23_EN = 1;
000010  6888              LDR      r0,[r1,#8]
000012  d20c              BCS      |L20.46|
000014  034a              LSLS     r2,r1,#13             ;587
000016  e007              B        |L20.40|
                  |L20.24|
000018  2802              CMP      r0,#2                 ;580
00001a  6888              LDR      r0,[r1,#8]            ;583
00001c  d202              BCS      |L20.36|
00001e  2201              MOVS     r2,#1                 ;581
000020  0512              LSLS     r2,r2,#20             ;581
000022  e001              B        |L20.40|
                  |L20.36|
000024  2201              MOVS     r2,#1                 ;583
000026  0552              LSLS     r2,r2,#21             ;583
                  |L20.40|
000028  4310              ORRS     r0,r0,r2              ;583
00002a  6088              STR      r0,[r1,#8]            ;583
;;;590    		}
;;;591        }
;;;592    }
00002c  4770              BX       lr
                  |L20.46|
00002e  2201              MOVS     r2,#1                 ;589
000030  05d2              LSLS     r2,r2,#23             ;589
000032  e7f9              B        |L20.40|
;;;593    
                          ENDP

                  |L20.52|
                          DCD      0x50000200

                          AREA ||i.DrvPWM_SelectClearLatchFlagOption||, CODE, READONLY, ALIGN=1

                  DrvPWM_SelectClearLatchFlagOption PROC
;;;1159   /*---------------------------------------------------------------------------------------------------------*/
;;;1160   int32_t DrvPWM_SelectClearLatchFlagOption(int32_t i32option)
000000  2000              MOVS     r0,#0
;;;1161   {
;;;1162   	return(0);
;;;1163   }
000002  4770              BX       lr
;;;1164   
                          ENDP


                          AREA ||i.DrvPWM_SelectClockSource||, CODE, READONLY, ALIGN=2

                  DrvPWM_SelectClockSource PROC
;;;1122   /*---------------------------------------------------------------------------------------------------------*/
;;;1123   void DrvPWM_SelectClockSource(uint8_t u8Timer, uint8_t u8ClockSourceSelector)
000000  b570              PUSH     {r4-r6,lr}
;;;1124   {
;;;1125   	switch (u8Timer & 0x07)
000002  0745              LSLS     r5,r0,#29
;;;1126   	{
;;;1127   		case DRVPWM_TIMER0:
;;;1128   		case DRVPWM_TIMER1:
;;;1129   			CLK->CLKSEL1_BITS.PWM0_CH01_S = u8ClockSourceSelector;				
000004  0789              LSLS     r1,r1,#30
000006  0f89              LSRS     r1,r1,#30
000008  0f6d              LSRS     r5,r5,#29             ;1125
00000a  0108              LSLS     r0,r1,#4
00000c  4a0f              LDR      r2,|L22.76|
00000e  2430              MOVS     r4,#0x30
;;;1130   			break;
;;;1131   		case DRVPWM_TIMER2:
;;;1132   		case DRVPWM_TIMER3:
;;;1133   			CLK->CLKSEL1_BITS.PWM0_CH23_S = u8ClockSourceSelector;
000010  26c0              MOVS     r6,#0xc0
000012  0189              LSLS     r1,r1,#6
000014  002b              MOVS     r3,r5                 ;1125
000016  f7fffffe          BL       __ARM_common_switch8
00001a  0805              DCB      0x08,0x05
00001c  050a0a0f          DCB      0x05,0x0a,0x0a,0x0f
000020  0f141409          DCB      0x0f,0x14,0x14,0x09
000024  6951              LDR      r1,[r2,#0x14]         ;1129
000026  43a1              BICS     r1,r1,r4              ;1129
000028  4301              ORRS     r1,r1,r0              ;1129
00002a  6151              STR      r1,[r2,#0x14]         ;1129
;;;1134   			break;		
;;;1135   		case DRVPWM_TIMER4:
;;;1136   		case DRVPWM_TIMER5:
;;;1137   			CLK->CLKSEL2_BITS.PWM1_CH01_S = u8ClockSourceSelector;				
;;;1138   			break;
;;;1139   		case DRVPWM_TIMER6:
;;;1140   		case DRVPWM_TIMER7:
;;;1141   			CLK->CLKSEL2_BITS.PWM1_CH23_S = u8ClockSourceSelector;
;;;1142   			break;	
;;;1143   	}
;;;1144   }
00002c  bd70              POP      {r4-r6,pc}
00002e  6950              LDR      r0,[r2,#0x14]         ;1133
000030  43b0              BICS     r0,r0,r6              ;1133
000032  4308              ORRS     r0,r0,r1              ;1133
000034  6150              STR      r0,[r2,#0x14]         ;1133
000036  bd70              POP      {r4-r6,pc}
000038  6991              LDR      r1,[r2,#0x18]         ;1137
00003a  43a1              BICS     r1,r1,r4              ;1137
00003c  4301              ORRS     r1,r1,r0              ;1137
00003e  6191              STR      r1,[r2,#0x18]         ;1137
000040  bd70              POP      {r4-r6,pc}
000042  6990              LDR      r0,[r2,#0x18]         ;1141
000044  43b0              BICS     r0,r0,r6              ;1141
000046  4308              ORRS     r0,r0,r1              ;1141
000048  6190              STR      r0,[r2,#0x18]         ;1141
00004a  bd70              POP      {r4-r6,pc}
;;;1145   
                          ENDP

                  |L22.76|
                          DCD      0x50000200

                          AREA ||i.DrvPWM_SetCaptureAttribute||, CODE, READONLY, ALIGN=2

                  DrvPWM_SetCaptureAttribute PROC
;;;1270     */
;;;1271   int32_t DrvPWM_SetCaptureAttribute(uint8_t u8Capture, uint8_t inv, uint8_t cas, E_PWM_RELOAD reload)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1272   {
;;;1273   
;;;1274       PWM_TypeDef *base;
;;;1275       uint8_t ch, set;
;;;1276   
;;;1277       set = (u8Capture & 4) >> 2;
000002  0744              LSLS     r4,r0,#29
;;;1278       ch = u8Capture & 0x3;
000004  0786              LSLS     r6,r0,#30
000006  0fe4              LSRS     r4,r4,#31             ;1277
000008  0fb6              LSRS     r6,r6,#30
;;;1279   
;;;1280   
;;;1281       assert_param(!((ch % 2) && (cas))) // cascade mode support channel 0 & 2 only
;;;1282   
;;;1283   	base = (set == 0) ? PWM0 : PWM1;
00000a  2c00              CMP      r4,#0
00000c  d009              BEQ      |L23.34|
00000e  4c14              LDR      r4,|L23.96|
                  |L23.16|
000010  0785              LSLS     r5,r0,#30             ;1278
;;;1284   
;;;1285   
;;;1286   	if(inv)
;;;1287   		base->CAPCTL |= 1 << (8 * ch);
000012  2701              MOVS     r7,#1
000014  0eed              LSRS     r5,r5,#27
000016  40af              LSLS     r7,r7,r5
000018  2900              CMP      r1,#0                 ;1286
;;;1288   	else
;;;1289   		base->CAPCTL &= ~(1 << (8 * ch));	
00001a  6d61              LDR      r1,[r4,#0x54]
00001c  d003              BEQ      |L23.38|
00001e  4339              ORRS     r1,r1,r7              ;1287
000020  e002              B        |L23.40|
                  |L23.34|
000022  4c10              LDR      r4,|L23.100|
000024  e7f4              B        |L23.16|
                  |L23.38|
000026  43b9              BICS     r1,r1,r7
                  |L23.40|
000028  6561              STR      r1,[r4,#0x54]
;;;1290   
;;;1291       if(cas)
;;;1292           base->CAPCTL |= 0x2000 << (8 * ch);
00002a  2101              MOVS     r1,#1
00002c  0349              LSLS     r1,r1,#13
00002e  0780              LSLS     r0,r0,#30             ;1278
000030  0ec0              LSRS     r0,r0,#27             ;1287
000032  4081              LSLS     r1,r1,r0
000034  2a00              CMP      r2,#0                 ;1291
000036  d002              BEQ      |L23.62|
000038  6d60              LDR      r0,[r4,#0x54]
00003a  4308              ORRS     r0,r0,r1
00003c  e003              B        |L23.70|
                  |L23.62|
;;;1293       else  if((ch % 2) == 0)
00003e  07f0              LSLS     r0,r6,#31
000040  d102              BNE      |L23.72|
;;;1294           base->CAPCTL &= ~(0x2000 << (8 * ch));            		
000042  6d60              LDR      r0,[r4,#0x54]
000044  4388              BICS     r0,r0,r1
                  |L23.70|
000046  6560              STR      r0,[r4,#0x54]
                  |L23.72|
;;;1295   
;;;1296       base->CAPCTL &= ~(0xc0 << (8 * ch));
000048  6d60              LDR      r0,[r4,#0x54]
00004a  21c0              MOVS     r1,#0xc0
00004c  40a9              LSLS     r1,r1,r5
00004e  4388              BICS     r0,r0,r1
000050  6560              STR      r0,[r4,#0x54]
;;;1297       base->CAPCTL |= (reload << 6) << (8 * ch);
000052  6d60              LDR      r0,[r4,#0x54]
000054  40ab              LSLS     r3,r3,r5
000056  0199              LSLS     r1,r3,#6
000058  4308              ORRS     r0,r0,r1
00005a  6560              STR      r0,[r4,#0x54]
;;;1298       
;;;1299   	return(0);
00005c  2000              MOVS     r0,#0
;;;1300   }
00005e  bdf0              POP      {r4-r7,pc}
                          ENDP

                  |L23.96|
                          DCD      0x40140000
                  |L23.100|
                          DCD      0x40040000

                          AREA ||i.DrvPWM_SetTimerClk||, CODE, READONLY, ALIGN=2

                  DrvPWM_SetTimerClk PROC
;;;799    /*---------------------------------------------------------------------------------------------------------*/
;;;800    uint32_t DrvPWM_SetTimerClk(uint8_t u8Timer, S_DRVPWM_TIME_DATA_T *sPt)
000000  b5f0              PUSH     {r4-r7,lr}
;;;801    {
000002  4607              MOV      r7,r0
000004  460c              MOV      r4,r1
;;;802    	uint32_t 	u32Frequency;
;;;803    	uint32_t	u32Freqout;
;;;804    	uint16_t	u16Duty, u16cnrData, u16cmrData;
;;;805    	uint8_t	    u8EngineClk = 0;
;;;806    		
;;;807    	
;;;808    	switch (u8Timer & 0x07)
000006  0779              LSLS     r1,r7,#29
000008  0f49              LSRS     r1,r1,#29
00000a  b089              SUB      sp,sp,#0x24           ;801
00000c  2000              MOVS     r0,#0                 ;805
;;;809    	{
;;;810    		case DRVPWM_TIMER0:
;;;811    		case DRVPWM_TIMER1:
;;;812    			u8EngineClk = CLK->CLKSEL1_BITS.PWM0_CH01_S;				
00000e  4ad1              LDR      r2,|L24.852|
000010  9103              STR      r1,[sp,#0xc]          ;808
000012  000b              MOVS     r3,r1                 ;808
000014  f7fffffe          BL       __ARM_common_switch8
000018  08050507          DCB      0x08,0x05,0x05,0x07
00001c  071b1b1e          DCB      0x07,0x1b,0x1b,0x1e
000020  1e0a              DCB      0x1e,0x0a
000022  6950              LDR      r0,[r2,#0x14]
;;;813    			break;
000024  e014              B        |L24.80|
;;;814    		case DRVPWM_TIMER2:
;;;815    		case DRVPWM_TIMER3:
;;;816    			u8EngineClk = CLK->CLKSEL1_BITS.PWM0_CH23_S;
000026  6950              LDR      r0,[r2,#0x14]
;;;817    			break;		
000028  e015              B        |L24.86|
                  |L24.42|
00002a  0f80              LSRS     r0,r0,#30             ;812
;;;818    		case DRVPWM_TIMER4:
;;;819    		case DRVPWM_TIMER5:
;;;820    			u8EngineClk = CLK->CLKSEL2_BITS.PWM1_CH01_S;			
;;;821    			break;
;;;822    		case DRVPWM_TIMER6:
;;;823    		case DRVPWM_TIMER7:
;;;824    			u8EngineClk = CLK->CLKSEL2_BITS.PWM1_CH23_S;
;;;825    			break;	
;;;826    	}
;;;827    
;;;828    
;;;829    	if (u8EngineClk == 0)		 /* external 12MHz crystal clock	*/
;;;830    	{
;;;831    		u32Freqout = __XTAL;	
00002c  49ca              LDR      r1,|L24.856|
00002e  2800              CMP      r0,#0                 ;829
000030  d003              BEQ      |L24.58|
;;;832    	}
;;;833    	else if(u8EngineClk == 1)    /* external 32KHz crystal clock */
000032  2801              CMP      r0,#1
000034  d011              BEQ      |L24.90|
;;;834    	{
;;;835    		u32Freqout = __RTC_XTAL;
;;;836    	}
;;;837    	else if(u8EngineClk == 2)	 /* HCLK clock */
000036  2802              CMP      r0,#2
000038  d012              BEQ      |L24.96|
                  |L24.58|
;;;838    	{
;;;839    		u32Freqout = SystemCoreClock;
;;;840    	}
;;;841    	else						 /* internal 22MHz oscillator clock */
;;;842    	{
;;;843    	 	u32Freqout = __IRC12M;	
00003a  9102              STR      r1,[sp,#8]
                  |L24.60|
;;;844    	}
;;;845    
;;;846    	switch (u8Timer)
;;;847    	{
;;;848    		case DRVPWM_TIMER0:
;;;849    		case DRVPWM_TIMER1:
;;;850    		case DRVPWM_TIMER2:
;;;851    		case DRVPWM_TIMER3:
;;;852                // set inverter
;;;853    			outp32(&PWM0->CTL, (inp32(&PWM0->CTL) & ~(1 << (((u8Timer ) << 3) + 2) )) |(sPt->i32Inverter?(1 << ((u8Timer << 3) + 2)):0));
00003c  00f8              LSLS     r0,r7,#3
00003e  003b              MOVS     r3,r7                 ;846
000040  f7fffffe          BL       __ARM_common_switch8
000044  08121212          DCB      0x08,0x12,0x12,0x12
000048  12232323          DCB      0x12,0x23,0x23,0x23
00004c  2318              DCB      0x23,0x18
00004e  6990              LDR      r0,[r2,#0x18]         ;820
                  |L24.80|
000050  0680              LSLS     r0,r0,#26             ;820
000052  e7ea              B        |L24.42|
000054  6990              LDR      r0,[r2,#0x18]         ;824
                  |L24.86|
000056  0600              LSLS     r0,r0,#24             ;824
000058  e7e7              B        |L24.42|
                  |L24.90|
00005a  2001              MOVS     r0,#1                 ;835
00005c  03c0              LSLS     r0,r0,#15             ;835
00005e  e001              B        |L24.100|
                  |L24.96|
000060  48be              LDR      r0,|L24.860|
000062  6800              LDR      r0,[r0,#0]            ;839  ; SystemCoreClock
                  |L24.100|
000064  9002              STR      r0,[sp,#8]            ;839
000066  e7e9              B        |L24.60|
000068  4bbd              LDR      r3,|L24.864|
00006a  689a              LDR      r2,[r3,#8]
00006c  1c80              ADDS     r0,r0,#2
00006e  e00f              B        |L24.144|
                  |L24.112|
000070  430a              ORRS     r2,r2,r1
000072  609a              STR      r2,[r3,#8]
;;;854    			break;
;;;855    		case DRVPWM_TIMER4:
;;;856    		case DRVPWM_TIMER5:
;;;857    		case DRVPWM_TIMER6:
;;;858    		case DRVPWM_TIMER7:
;;;859    			outp32(&PWM1->CTL, (inp32(&PWM1->CTL) & ~(1 << (((u8Timer-DRVPWM_TIMER4) << 3) + 2) )) |(sPt->i32Inverter?(1 << (((u8Timer-DRVPWM_TIMER4) << 3) + 2)):0));
;;;860    			break;
;;;861    	} 
;;;862    
;;;863    	switch (u8Timer & 0x07)
000074  9903              LDR      r1,[sp,#0xc]
000076  0778              LSLS     r0,r7,#29             ;808
;;;864    	{
;;;865    		case DRVPWM_TIMER0:
;;;866    		case DRVPWM_TIMER1:
;;;867    		case DRVPWM_TIMER2:
;;;868    		case DRVPWM_TIMER3:
;;;869    			outp32(&PWM0->CTL, (inp32(&PWM0->CTL) & ~(1 <<(((u8Timer & 0x07) << 3) + 3))) | ( sPt->u8Mode? (1 <<(((u8Timer & 0x07) << 3) + 3)):0));
000078  0e80              LSRS     r0,r0,#26
00007a  000b              MOVS     r3,r1                 ;863
00007c  f7fffffe          BL       __ARM_common_switch8
000080  08101010          DCB      0x08,0x10,0x10,0x10
000084  103a3a3a          DCB      0x10,0x3a,0x3a,0x3a
000088  3a16              DCB      0x3a,0x16
00008a  4bb6              LDR      r3,|L24.868|
00008c  689a              LDR      r2,[r3,#8]            ;859
00008e  381e              SUBS     r0,r0,#0x1e           ;859
                  |L24.144|
000090  2101              MOVS     r1,#1                 ;859
000092  4081              LSLS     r1,r1,r0              ;859
000094  68e0              LDR      r0,[r4,#0xc]          ;859
000096  438a              BICS     r2,r2,r1              ;859
000098  2800              CMP      r0,#0                 ;859
00009a  d1e9              BNE      |L24.112|
00009c  2100              MOVS     r1,#0                 ;859
00009e  e7e7              B        |L24.112|
0000a0  4baf              LDR      r3,|L24.864|
0000a2  689a              LDR      r2,[r3,#8]
0000a4  1cc0              ADDS     r0,r0,#3
0000a6  e028              B        |L24.250|
                  |L24.168|
0000a8  430a              ORRS     r2,r2,r1
0000aa  609a              STR      r2,[r3,#8]
;;;870    			break;
;;;871    		case DRVPWM_TIMER4:
;;;872    		case DRVPWM_TIMER5:
;;;873    		case DRVPWM_TIMER6:
;;;874    		case DRVPWM_TIMER7:
;;;875    			outp32(&PWM1->CTL, (inp32(&PWM1->CTL) & ~(1 <<((((u8Timer & 0x07)-DRVPWM_TIMER4) << 3) + 3))) | ( sPt->u8Mode? (1 <<((((u8Timer & 0x07)-DRVPWM_TIMER4) << 3) + 3)):0));			
;;;876    			break;
;;;877    	} 
;;;878    			
;;;879    	
;;;880    	if (sPt->u32Frequency == 0)
;;;881    	{	
;;;882    		uint8_t	u8Divider = 1;
;;;883    		uint32_t u32duty;
;;;884    		
;;;885    		switch (u8Timer & 0x07)
;;;886    		{
;;;887    			case DRVPWM_TIMER0:
;;;888    			case DRVPWM_TIMER1:
;;;889    				PWM0->PRES_BITS.CP01 = sPt->u8PreScale;
;;;890    				break;
;;;891    			case DRVPWM_TIMER2:
;;;892    			case DRVPWM_TIMER3:
;;;893    				PWM0->PRES_BITS.CP23 = sPt->u8PreScale;
;;;894    				break;
;;;895    			case DRVPWM_TIMER4:
;;;896    			case DRVPWM_TIMER5:
;;;897    				PWM1->PRES_BITS.CP01 = sPt->u8PreScale;
;;;898    				break;
;;;899    			case DRVPWM_TIMER6:
;;;900    			case DRVPWM_TIMER7:
;;;901    				PWM1->PRES_BITS.CP23 = sPt->u8PreScale;
;;;902    				break;
;;;903    		} 
;;;904    		
;;;905    		u32duty = sPt->u32Duty * sPt->u8HighPulseRatio / 100 - 1;
;;;906    		
;;;907    		switch (u8Timer & 0x07)
;;;908    		{
;;;909    			case DRVPWM_TIMER0:
;;;910    			case DRVPWM_TIMER1:
;;;911    			case DRVPWM_TIMER2:
;;;912    			case DRVPWM_TIMER3:
;;;913    				outp32(&PWM0->CLKSEL, (inp32(&PWM0->CLKSEL) & ~(0x7 << ((u8Timer & 0x03)<<2) )) | ((sPt->u8ClockSelector & 0x7) << ((u8Timer & 0x07)<<2)));	
0000ac  07b8              LSLS     r0,r7,#30
0000ae  2207              MOVS     r2,#7
0000b0  0f00              LSRS     r0,r0,#28
0000b2  4613              MOV      r3,r2
0000b4  4083              LSLS     r3,r3,r0
0000b6  6861              LDR      r1,[r4,#4]
0000b8  0778              LSLS     r0,r7,#29             ;808
0000ba  0ec0              LSRS     r0,r0,#27
;;;914    				//outp32(&PWM0->DUTY0 + (u8Timer & 0x07) * 3, (u32duty << 16) + (sPt->u32Duty - 1));					
;;;915                    DrvPWM_SetTimerCounter(u8Timer, sPt->u32Duty - 1, u32duty);
;;;916    				break;
;;;917    			case DRVPWM_TIMER4:
;;;918    			case DRVPWM_TIMER5:
;;;919    			case DRVPWM_TIMER6:
;;;920    			case DRVPWM_TIMER7:
;;;921    				outp32(&PWM1->CLKSEL, (inp32(&PWM1->CLKSEL) & ~(0x7 << (((u8Timer & 0x03)-DRVPWM_TIMER4)<<2) )) | ((sPt->u8ClockSelector & 0x7) << (((u8Timer & 0x07)-DRVPWM_TIMER4)<<2)));	
0000bc  9305              STR      r3,[sp,#0x14]
0000be  9004              STR      r0,[sp,#0x10]
0000c0  2303              MOVS     r3,#3
0000c2  43db              MVNS     r3,r3
0000c4  4638              MOV      r0,r7                 ;801
0000c6  4318              ORRS     r0,r0,r3
0000c8  0080              LSLS     r0,r0,#2
0000ca  4082              LSLS     r2,r2,r0
0000cc  9804              LDR      r0,[sp,#0x10]
0000ce  9206              STR      r2,[sp,#0x18]
0000d0  3810              SUBS     r0,r0,#0x10
0000d2  9007              STR      r0,[sp,#0x1c]         ;880
0000d4  2900              CMP      r1,#0                 ;880
0000d6  d018              BEQ      |L24.266|
;;;922    				//outp32(&PWM1->DUTY0 + ((u8Timer & 0x07)-DRVPWM_TIMER4) * 3, (u32duty << 16) + (sPt->u32Duty - 1));	
;;;923                    DrvPWM_SetTimerCounter(u8Timer, sPt->u32Duty - 1, u32duty);			
;;;924    				break;
;;;925    		}
;;;926    				
;;;927    		switch (sPt->u8ClockSelector)
;;;928    		{
;;;929    			case DRVPWM_CLOCK_DIV_1:
;;;930    				u8Divider = 1;
;;;931    				break;
;;;932    			case DRVPWM_CLOCK_DIV_2:
;;;933    				u8Divider = 2;			
;;;934    				break;			
;;;935    			case DRVPWM_CLOCK_DIV_4:
;;;936    				u8Divider = 4;			
;;;937    				break;			
;;;938    			case DRVPWM_CLOCK_DIV_8:
;;;939    				u8Divider = 8;			
;;;940    				break;			
;;;941    			case DRVPWM_CLOCK_DIV_16: 
;;;942    				u8Divider = 16;			
;;;943    				break;		
;;;944    		}		
;;;945    		
;;;946    		u32Frequency = u32Freqout / (sPt->u8PreScale + 1) / u8Divider / sPt->u32Duty;
;;;947    	}
;;;948    	else
;;;949    	{
;;;950    		uint8_t	 u8Divider;
;;;951    		uint16_t u16PreScale;
;;;952    		
;;;953    		u32Frequency =  u32Freqout / sPt->u32Frequency;		
0000d8  9802              LDR      r0,[sp,#8]
0000da  f7fffffe          BL       __aeabi_uidivmod
;;;954    		
;;;955    		if (u32Frequency > 0x10000000)
0000de  2101              MOVS     r1,#1
0000e0  0709              LSLS     r1,r1,#28
0000e2  9001              STR      r0,[sp,#4]
0000e4  4288              CMP      r0,r1
0000e6  d874              BHI      |L24.466|
;;;956    			return 0;
;;;957    			
;;;958    		u8Divider = 1;			
0000e8  2501              MOVS     r5,#1
;;;959    			
;;;960    		if (u32Frequency < 0x20000)
0000ea  12c9              ASRS     r1,r1,#11
0000ec  4288              CMP      r0,r1
0000ee  d272              BCS      |L24.470|
;;;961    			u16PreScale = 2;	
0000f0  2602              MOVS     r6,#2
0000f2  e0a6              B        |L24.578|
0000f4  4b9b              LDR      r3,|L24.868|
0000f6  689a              LDR      r2,[r3,#8]            ;875
0000f8  381d              SUBS     r0,r0,#0x1d           ;875
                  |L24.250|
0000fa  2101              MOVS     r1,#1                 ;875
0000fc  4081              LSLS     r1,r1,r0              ;875
0000fe  7820              LDRB     r0,[r4,#0]            ;875
000100  438a              BICS     r2,r2,r1              ;875
000102  2800              CMP      r0,#0                 ;875
000104  d1d0              BNE      |L24.168|
000106  2100              MOVS     r1,#0                 ;875
000108  e7ce              B        |L24.168|
                  |L24.266|
00010a  9803              LDR      r0,[sp,#0xc]          ;885
00010c  2501              MOVS     r5,#1                 ;882
00010e  0003              MOVS     r3,r0                 ;885
000110  f7fffffe          BL       __ARM_common_switch8
000114  08050507          DCB      0x08,0x05,0x05,0x07
000118  071b1b21          DCB      0x07,0x1b,0x1b,0x21
00011c  210b              DCB      0x21,0x0b
00011e  4890              LDR      r0,|L24.864|
000120  e014              B        |L24.332|
000122  488f              LDR      r0,|L24.864|
000124  e018              B        |L24.344|
                  |L24.294|
000126  4311              ORRS     r1,r1,r2              ;889
000128  6001              STR      r1,[r0,#0]            ;889
00012a  7861              LDRB     r1,[r4,#1]            ;905
00012c  68a0              LDR      r0,[r4,#8]            ;905
00012e  4348              MULS     r0,r1,r0              ;905
000130  2164              MOVS     r1,#0x64              ;905
000132  f7fffffe          BL       __aeabi_uidivmod
000136  9903              LDR      r1,[sp,#0xc]          ;907
000138  1e40              SUBS     r0,r0,#1              ;905
00013a  000b              MOVS     r3,r1                 ;907
00013c  f7fffffe          BL       __ARM_common_switch8
000140  08131313          DCB      0x08,0x13,0x13,0x13
000144  131f1f1f          DCB      0x13,0x1f,0x1f,0x1f
000148  1f30              DCB      0x1f,0x30
00014a  4886              LDR      r0,|L24.868|
                  |L24.332|
00014c  6801              LDR      r1,[r0,#0]            ;897
00014e  78e2              LDRB     r2,[r4,#3]            ;897
000150  0a09              LSRS     r1,r1,#8              ;897
000152  0209              LSLS     r1,r1,#8              ;897
000154  e7e7              B        |L24.294|
000156  4883              LDR      r0,|L24.868|
                  |L24.344|
000158  6801              LDR      r1,[r0,#0]            ;901
00015a  22ff              MOVS     r2,#0xff              ;901
00015c  0212              LSLS     r2,r2,#8              ;901
00015e  4391              BICS     r1,r1,r2              ;901
000160  78e2              LDRB     r2,[r4,#3]            ;901
000162  0212              LSLS     r2,r2,#8              ;901
000164  e7df              B        |L24.294|
000166  4b7e              LDR      r3,|L24.864|
000168  6859              LDR      r1,[r3,#4]            ;913
00016a  9a05              LDR      r2,[sp,#0x14]         ;913
00016c  9e04              LDR      r6,[sp,#0x10]         ;913
00016e  4391              BICS     r1,r1,r2              ;913
000170  78a2              LDRB     r2,[r4,#2]            ;913
000172  0752              LSLS     r2,r2,#29             ;913
000174  0f52              LSRS     r2,r2,#29             ;913
000176  40b2              LSLS     r2,r2,r6              ;913
000178  4311              ORRS     r1,r1,r2              ;913
00017a  6059              STR      r1,[r3,#4]            ;913
00017c  e00a              B        |L24.404|
00017e  4e79              LDR      r6,|L24.868|
000180  6871              LDR      r1,[r6,#4]            ;921
000182  9a06              LDR      r2,[sp,#0x18]         ;921
000184  78a3              LDRB     r3,[r4,#2]            ;921
000186  4391              BICS     r1,r1,r2              ;921
000188  075b              LSLS     r3,r3,#29             ;921
00018a  9a07              LDR      r2,[sp,#0x1c]         ;921
00018c  0f5b              LSRS     r3,r3,#29             ;921
00018e  4093              LSLS     r3,r3,r2              ;921
000190  4319              ORRS     r1,r1,r3              ;921
000192  6071              STR      r1,[r6,#4]            ;921
                  |L24.404|
000194  68a1              LDR      r1,[r4,#8]            ;915
000196  b282              UXTH     r2,r0                 ;915
000198  1e49              SUBS     r1,r1,#1              ;915
00019a  4638              MOV      r0,r7                 ;915
00019c  f7fffffe          BL       DrvPWM_SetTimerCounter
0001a0  78a0              LDRB     r0,[r4,#2]            ;927
0001a2  0003              MOVS     r3,r0                 ;927
0001a4  f7fffffe          BL       __ARM_common_switch8
0001a8  04030507          DCB      0x04,0x03,0x05,0x07
0001ac  090a              DCB      0x09,0x0a
0001ae  2502              MOVS     r5,#2                 ;933
0001b0  e004              B        |L24.444|
0001b2  2504              MOVS     r5,#4                 ;936
0001b4  e002              B        |L24.444|
0001b6  2508              MOVS     r5,#8                 ;939
0001b8  e000              B        |L24.444|
0001ba  2510              MOVS     r5,#0x10              ;942
                  |L24.444|
0001bc  78e1              LDRB     r1,[r4,#3]            ;946
0001be  9802              LDR      r0,[sp,#8]            ;946
0001c0  1c49              ADDS     r1,r1,#1              ;946
0001c2  4369              MULS     r1,r5,r1              ;946
0001c4  f7fffffe          BL       __aeabi_uidivmod
0001c8  68a1              LDR      r1,[r4,#8]            ;946
0001ca  f7fffffe          BL       __aeabi_uidivmod
0001ce  9001              STR      r0,[sp,#4]            ;947
0001d0  e0bd              B        |L24.846|
                  |L24.466|
0001d2  e030              B        |L24.566|
0001d4  e7ff              B        |L24.470|
                  |L24.470|
;;;962    		else
;;;963    		{
;;;964    			u16PreScale = u32Frequency / 65536;	
0001d6  0c06              LSRS     r6,r0,#16
;;;965    							
;;;966    			if (u32Frequency / u16PreScale > 65536)
0001d8  4631              MOV      r1,r6
0001da  f7fffffe          BL       __aeabi_uidivmod
0001de  4601              MOV      r1,r0
0001e0  2001              MOVS     r0,#1
0001e2  0400              LSLS     r0,r0,#16
0001e4  4281              CMP      r1,r0
0001e6  d901              BLS      |L24.492|
;;;967    				u16PreScale++;
0001e8  1c76              ADDS     r6,r6,#1
0001ea  b2b6              UXTH     r6,r6
                  |L24.492|
;;;968    			
;;;969    			if (u16PreScale > 256)
0001ec  20ff              MOVS     r0,#0xff
0001ee  3001              ADDS     r0,#1
0001f0  4286              CMP      r6,r0
0001f2  d926              BLS      |L24.578|
;;;970    			{
;;;971    				uint8_t u8i = 0;
;;;972    				
;;;973    				u16PreScale = 256;
0001f4  4606              MOV      r6,r0
;;;974    				u32Frequency = u32Frequency / u16PreScale;
0001f6  9801              LDR      r0,[sp,#4]
0001f8  2500              MOVS     r5,#0                 ;971
0001fa  0a00              LSRS     r0,r0,#8
;;;975    				
;;;976    				u8Divider = u32Frequency / 65536;				
0001fc  9001              STR      r0,[sp,#4]
0001fe  0c00              LSRS     r0,r0,#16
;;;977    				
;;;978    				if(u32Frequency / u8Divider > 65536)
000200  4601              MOV      r1,r0
000202  9000              STR      r0,[sp,#0]
000204  9801              LDR      r0,[sp,#4]
000206  f7fffffe          BL       __aeabi_uidivmod
00020a  4601              MOV      r1,r0
00020c  2001              MOVS     r0,#1
00020e  0400              LSLS     r0,r0,#16
000210  4281              CMP      r1,r0
000212  d903              BLS      |L24.540|
;;;979    					u8Divider++;				
000214  9800              LDR      r0,[sp,#0]
000216  1c40              ADDS     r0,r0,#1
000218  b2c0              UXTB     r0,r0
00021a  9000              STR      r0,[sp,#0]
                  |L24.540|
00021c  2101              MOVS     r1,#1                 ;805
                  |L24.542|
;;;980    				
;;;981    				while(1)	
;;;982    				{
;;;983    					if((1 << u8i++) > u8Divider)
00021e  4608              MOV      r0,r1
000220  40a8              LSLS     r0,r0,r5
000222  1c6d              ADDS     r5,r5,#1
000224  9a00              LDR      r2,[sp,#0]
000226  b2ed              UXTB     r5,r5
000228  4290              CMP      r0,r2
00022a  ddf8              BLE      |L24.542|
;;;984    						break;
;;;985    				}
;;;986    				
;;;987    				u8Divider = 1 << (u8i - 1);
00022c  1e6d              SUBS     r5,r5,#1
00022e  40a9              LSLS     r1,r1,r5
000230  b2cd              UXTB     r5,r1
;;;988    				
;;;989    				if (u8Divider > 16)
000232  2d10              CMP      r5,#0x10
000234  d902              BLS      |L24.572|
                  |L24.566|
;;;990    					return 0;	
000236  2000              MOVS     r0,#0
                  |L24.568|
;;;991    					
;;;992    				u32Frequency = u32Frequency * u16PreScale;						
;;;993    			}		
;;;994    					
;;;995    		}
;;;996    		u16Duty = (uint16_t )(u32Frequency/u16PreScale/u8Divider);
;;;997    		
;;;998    		u32Frequency = (u32Freqout / u16PreScale / u8Divider) / u16Duty;	
;;;999    				
;;;1000   		switch (u8Timer & 0x07)
;;;1001   		{
;;;1002   			case DRVPWM_TIMER0:
;;;1003   			case DRVPWM_TIMER1:
;;;1004   				PWM0->PRES_BITS.CP01 = u16PreScale - 1;
;;;1005   				break;
;;;1006   			case DRVPWM_TIMER2:
;;;1007   			case DRVPWM_TIMER3:
;;;1008   				PWM0->PRES_BITS.CP23 = u16PreScale - 1;
;;;1009   				break;
;;;1010   			case DRVPWM_TIMER4:
;;;1011   			case DRVPWM_TIMER5:
;;;1012   				PWM1->PRES_BITS.CP01 = u16PreScale - 1;
;;;1013   				break;
;;;1014   			case DRVPWM_TIMER6:
;;;1015   			case DRVPWM_TIMER7:
;;;1016   				PWM1->PRES_BITS.CP23 = u16PreScale - 1;
;;;1017   				break;
;;;1018   		}
;;;1019   		
;;;1020   		switch(u8Divider)
;;;1021   		{
;;;1022   			case 1:
;;;1023   				u8Divider = DRVPWM_CLOCK_DIV_1;
;;;1024   				break;
;;;1025   			case 2:
;;;1026   				u8Divider = DRVPWM_CLOCK_DIV_2;			
;;;1027   				break;			
;;;1028   			case 4:
;;;1029   				u8Divider = DRVPWM_CLOCK_DIV_4;			
;;;1030   				break;			
;;;1031   			case 8:
;;;1032   				u8Divider = DRVPWM_CLOCK_DIV_8;			
;;;1033   				break;			
;;;1034   			case 16:
;;;1035   				u8Divider = DRVPWM_CLOCK_DIV_16;			
;;;1036   				break;		
;;;1037   		}				
;;;1038   					
;;;1039   		if (u8Timer & 0x10)
;;;1040   		{
;;;1041   			u16cnrData = sPt->u32Duty - 1; 
;;;1042   			u16cmrData = sPt->u32Duty * sPt->u8HighPulseRatio / 100 - 1;		
;;;1043   		}
;;;1044   		else
;;;1045   		{
;;;1046   		 	u16cnrData = u16Duty - 1;
;;;1047   			u16cmrData = u16Duty * sPt->u8HighPulseRatio / 100 - 1;
;;;1048   		}
;;;1049   		
;;;1050   		switch (u8Timer & 0x07)
;;;1051   		{
;;;1052   			case DRVPWM_TIMER0:
;;;1053   			case DRVPWM_TIMER1:
;;;1054   			case DRVPWM_TIMER2:
;;;1055   			case DRVPWM_TIMER3:
;;;1056   		        outp32(&PWM0->CLKSEL, (inp32(&PWM0->CLKSEL) & ~(0x7 << ((u8Timer & 0x03)<<2) )) | ((u8Divider & 0x7) << ((u8Timer & 0x07)<<2)));	
;;;1057                   //outp32(&PWM0->DUTY0 + (u8Timer & 0x07) * 3, (u16cmrData << 16) + u16cnrData);				
;;;1058                   DrvPWM_SetTimerCounter(u8Timer, u16cnrData, u16cmrData);
;;;1059   				break;
;;;1060   			case DRVPWM_TIMER4:
;;;1061   			case DRVPWM_TIMER5:
;;;1062   			case DRVPWM_TIMER6:
;;;1063   			case DRVPWM_TIMER7:
;;;1064   		        outp32(&PWM1->CLKSEL, (inp32(&PWM1->CLKSEL) & ~(0x7 << (((u8Timer & 0x03)-DRVPWM_TIMER4)<<2) )) | ((u8Divider & 0x7) << (((u8Timer & 0x07)-DRVPWM_TIMER4)<<2)));	
;;;1065   			    DrvPWM_SetTimerCounter(u8Timer, u16cnrData, u16cmrData);								
;;;1066   				break;
;;;1067   		}
;;;1068   	}
;;;1069   	
;;;1070   	return u32Frequency;
;;;1071   }
000238  b009              ADD      sp,sp,#0x24
00023a  bdf0              POP      {r4-r7,pc}
                  |L24.572|
00023c  9801              LDR      r0,[sp,#4]            ;992
00023e  4370              MULS     r0,r6,r0              ;992
000240  9001              STR      r0,[sp,#4]            ;992
                  |L24.578|
000242  4631              MOV      r1,r6                 ;996
000244  4369              MULS     r1,r5,r1              ;996
000246  9801              LDR      r0,[sp,#4]            ;996
000248  f7fffffe          BL       __aeabi_uidivmod
00024c  b282              UXTH     r2,r0                 ;996
00024e  4631              MOV      r1,r6                 ;998
000250  9200              STR      r2,[sp,#0]            ;998
000252  9802              LDR      r0,[sp,#8]            ;998
000254  f7fffffe          BL       __aeabi_uidivmod
000258  9a00              LDR      r2,[sp,#0]            ;998
00025a  4629              MOV      r1,r5                 ;998
00025c  4351              MULS     r1,r2,r1              ;998
00025e  f7fffffe          BL       __aeabi_uidivmod
000262  9001              STR      r0,[sp,#4]            ;998
000264  9803              LDR      r0,[sp,#0xc]          ;1000
000266  0003              MOVS     r3,r0                 ;1000
000268  f7fffffe          BL       __ARM_common_switch8
00026c  08050507          DCB      0x08,0x05,0x05,0x07
000270  0713131c          DCB      0x07,0x13,0x13,0x1c
000274  1c27              DCB      0x1c,0x27
000276  493a              LDR      r1,|L24.864|
000278  e00c              B        |L24.660|
00027a  0230              LSLS     r0,r6,#8              ;1008
00027c  4b38              LDR      r3,|L24.864|
00027e  38ff              SUBS     r0,r0,#0xff           ;1008
000280  3801              SUBS     r0,#1                 ;1008
000282  6819              LDR      r1,[r3,#0]            ;1008
000284  b282              UXTH     r2,r0                 ;1008
000286  20ff              MOVS     r0,#0xff              ;1008
000288  0200              LSLS     r0,r0,#8              ;1008
00028a  4381              BICS     r1,r1,r0              ;1008
00028c  430a              ORRS     r2,r2,r1              ;1008
00028e  601a              STR      r2,[r3,#0]            ;1008
000290  e013              B        |L24.698|
000292  4934              LDR      r1,|L24.868|
                  |L24.660|
000294  6808              LDR      r0,[r1,#0]            ;1004
000296  0a00              LSRS     r0,r0,#8              ;1004
000298  0200              LSLS     r0,r0,#8              ;1004
00029a  1e76              SUBS     r6,r6,#1              ;1004
00029c  b2f2              UXTB     r2,r6                 ;1004
00029e  4310              ORRS     r0,r0,r2              ;1004
0002a0  6008              STR      r0,[r1,#0]            ;1004
0002a2  e00a              B        |L24.698|
0002a4  0230              LSLS     r0,r6,#8              ;1016
0002a6  4b2f              LDR      r3,|L24.868|
0002a8  38ff              SUBS     r0,r0,#0xff           ;1016
0002aa  3801              SUBS     r0,#1                 ;1016
0002ac  681a              LDR      r2,[r3,#0]            ;1016
0002ae  b281              UXTH     r1,r0                 ;1016
0002b0  20ff              MOVS     r0,#0xff              ;1016
0002b2  0200              LSLS     r0,r0,#8              ;1016
0002b4  4382              BICS     r2,r2,r0              ;1016
0002b6  4311              ORRS     r1,r1,r2              ;1016
0002b8  6019              STR      r1,[r3,#0]            ;1016
                  |L24.698|
0002ba  2d04              CMP      r5,#4                 ;1020
0002bc  d00e              BEQ      |L24.732|
0002be  dc04              BGT      |L24.714|
0002c0  2d01              CMP      r5,#1                 ;1020
0002c2  d007              BEQ      |L24.724|
0002c4  2d02              CMP      r5,#2                 ;1020
0002c6  d10e              BNE      |L24.742|
0002c8  e006              B        |L24.728|
                  |L24.714|
0002ca  2d08              CMP      r5,#8                 ;1020
0002cc  d008              BEQ      |L24.736|
0002ce  2d10              CMP      r5,#0x10              ;1020
0002d0  d109              BNE      |L24.742|
0002d2  e007              B        |L24.740|
                  |L24.724|
0002d4  2504              MOVS     r5,#4                 ;1023
0002d6  e006              B        |L24.742|
                  |L24.728|
0002d8  2500              MOVS     r5,#0                 ;1026
0002da  e004              B        |L24.742|
                  |L24.732|
0002dc  2501              MOVS     r5,#1                 ;1029
0002de  e002              B        |L24.742|
                  |L24.736|
0002e0  2502              MOVS     r5,#2                 ;1032
0002e2  e000              B        |L24.742|
                  |L24.740|
0002e4  2503              MOVS     r5,#3                 ;1035
                  |L24.742|
0002e6  06f8              LSLS     r0,r7,#27             ;1039
0002e8  d504              BPL      |L24.756|
0002ea  68a0              LDR      r0,[r4,#8]            ;1041
0002ec  1e41              SUBS     r1,r0,#1              ;1041
0002ee  b28e              UXTH     r6,r1                 ;1041
0002f0  7861              LDRB     r1,[r4,#1]            ;1042
0002f2  e004              B        |L24.766|
                  |L24.756|
0002f4  9800              LDR      r0,[sp,#0]            ;1046
0002f6  9900              LDR      r1,[sp,#0]            ;1047
0002f8  1e40              SUBS     r0,r0,#1              ;1046
0002fa  b286              UXTH     r6,r0                 ;1046
0002fc  7860              LDRB     r0,[r4,#1]            ;1047
                  |L24.766|
0002fe  4348              MULS     r0,r1,r0              ;1047
000300  2164              MOVS     r1,#0x64              ;1047
000302  f7fffffe          BL       __aeabi_uidivmod
000306  1e40              SUBS     r0,r0,#1              ;1047
000308  b282              UXTH     r2,r0                 ;1047
00030a  9803              LDR      r0,[sp,#0xc]          ;1050
00030c  0003              MOVS     r3,r0                 ;1050
00030e  f7fffffe          BL       __ARM_common_switch8
000312  0805              DCB      0x08,0x05
000314  05050510          DCB      0x05,0x05,0x05,0x10
000318  1010101e          DCB      0x10,0x10,0x10,0x1e
00031c  4b10              LDR      r3,|L24.864|
00031e  6858              LDR      r0,[r3,#4]            ;1056
000320  9905              LDR      r1,[sp,#0x14]         ;1056
000322  076c              LSLS     r4,r5,#29             ;1056
000324  4388              BICS     r0,r0,r1              ;1056
000326  9904              LDR      r1,[sp,#0x10]         ;1056
000328  0f64              LSRS     r4,r4,#29             ;1056
00032a  408c              LSLS     r4,r4,r1              ;1056
00032c  4320              ORRS     r0,r0,r4              ;1056
00032e  6058              STR      r0,[r3,#4]            ;1056
000330  e009              B        |L24.838|
000332  4c0c              LDR      r4,|L24.868|
000334  6860              LDR      r0,[r4,#4]            ;1064
000336  9906              LDR      r1,[sp,#0x18]         ;1064
000338  9b07              LDR      r3,[sp,#0x1c]         ;1064
00033a  4388              BICS     r0,r0,r1              ;1064
00033c  0769              LSLS     r1,r5,#29             ;1064
00033e  0f49              LSRS     r1,r1,#29             ;1064
000340  4099              LSLS     r1,r1,r3              ;1064
000342  4308              ORRS     r0,r0,r1              ;1064
000344  6060              STR      r0,[r4,#4]            ;1064
                  |L24.838|
000346  4631              MOV      r1,r6                 ;1058
000348  4638              MOV      r0,r7                 ;1058
00034a  f7fffffe          BL       DrvPWM_SetTimerCounter
                  |L24.846|
00034e  9801              LDR      r0,[sp,#4]            ;1070
000350  e772              B        |L24.568|
;;;1072   
                          ENDP

000352  0000              DCW      0x0000
                  |L24.852|
                          DCD      0x50000200
                  |L24.856|
                          DCD      0x00b71b00
                  |L24.860|
                          DCD      SystemCoreClock
                  |L24.864|
                          DCD      0x40040000
                  |L24.868|
                          DCD      0x40140000

                          AREA ||i.DrvPWM_SetTimerCounter||, CODE, READONLY, ALIGN=2

                  DrvPWM_SetTimerCounter PROC
;;;182    /*---------------------------------------------------------------------------------------------------------*/
;;;183    void DrvPWM_SetTimerCounter(uint8_t u8Timer, uint32_t cn, uint16_t cm)
000000  0700              LSLS     r0,r0,#28
;;;184    {	
;;;185    	u8Timer &= 0x0F;
;;;186    	
;;;187    	if (u8Timer >= DRVPWM_TIMER4)
;;;188    	{
;;;189    		*(__IO uint32_t *) (&PWM1->DUTY0 + 0x3 * (u8Timer - 4)) = ((cm << 16) | cn);
000002  0412              LSLS     r2,r2,#16
000004  0f00              LSRS     r0,r0,#28             ;185
000006  430a              ORRS     r2,r2,r1
000008  2804              CMP      r0,#4                 ;187
00000a  d305              BCC      |L25.24|
00000c  210c              MOVS     r1,#0xc
00000e  4348              MULS     r0,r1,r0
000010  4904              LDR      r1,|L25.36|
000012  1840              ADDS     r0,r0,r1
000014  62c2              STR      r2,[r0,#0x2c]
;;;190    	}
;;;191    	else
;;;192    	{
;;;193    		*(__IO uint32_t *) (&PWM0->DUTY0 + 0x3 * u8Timer) = ((cm << 16) | cn);
;;;194    	}
;;;195    }
000016  4770              BX       lr
                  |L25.24|
000018  210c              MOVS     r1,#0xc               ;193
00001a  4348              MULS     r0,r1,r0              ;193
00001c  4902              LDR      r1,|L25.40|
00001e  1840              ADDS     r0,r0,r1              ;193
000020  61c2              STR      r2,[r0,#0x1c]         ;193
000022  4770              BX       lr
;;;196    
                          ENDP

                  |L25.36|
                          DCD      0x4013ffc0
                  |L25.40|
                          DCD      0x40040000

                          AREA ||i.DrvPWM_SetTimerIO||, CODE, READONLY, ALIGN=2

                  DrvPWM_SetTimerIO PROC
;;;1088   /*---------------------------------------------------------------------------------------------------------*/
;;;1089   void DrvPWM_SetTimerIO(uint8_t u8Timer, int32_t i32Enable)
000000  b530              PUSH     {r4,r5,lr}
;;;1090   {
;;;1091   	PWM_TypeDef *base = ((u8Timer & 7) < 4) ? PWM0 : PWM1;
000002  0742              LSLS     r2,r0,#29
000004  0f52              LSRS     r2,r2,#29
000006  2a04              CMP      r2,#4
000008  d201              BCS      |L26.14|
00000a  4a0f              LDR      r2,|L26.72|
00000c  e000              B        |L26.16|
                  |L26.14|
00000e  4a0f              LDR      r2,|L26.76|
                  |L26.16|
;;;1092   	uint8_t ch = u8Timer & 0x3;
000010  0785              LSLS     r5,r0,#30
000012  0fad              LSRS     r5,r5,#30
;;;1093   	if (i32Enable)
;;;1094   	{
;;;1095   		if(u8Timer & 0x10) // capture
;;;1096   			base->CAPCTL |= 0x4 << (8 * ch);		
000014  00ec              LSLS     r4,r5,#3
000016  2304              MOVS     r3,#4
000018  40a3              LSLS     r3,r3,r4
;;;1097   		else
;;;1098   			base->OE |= (1 << ch);
00001a  2401              MOVS     r4,#1
00001c  40ac              LSLS     r4,r4,r5
00001e  2900              CMP      r1,#0                 ;1093
000020  d007              BEQ      |L26.50|
000022  06c0              LSLS     r0,r0,#27             ;1095
000024  d502              BPL      |L26.44|
000026  6d50              LDR      r0,[r2,#0x54]         ;1096
000028  4318              ORRS     r0,r0,r3              ;1096
00002a  e006              B        |L26.58|
                  |L26.44|
00002c  6950              LDR      r0,[r2,#0x14]
00002e  4320              ORRS     r0,r0,r4
000030  e007              B        |L26.66|
                  |L26.50|
;;;1099   	}
;;;1100   	else
;;;1101   	{
;;;1102   		if(u8Timer & 0x10) // capture
000032  06c0              LSLS     r0,r0,#27
000034  d503              BPL      |L26.62|
;;;1103   			base->CAPCTL &= ~(0x4 << (8 * ch));		
000036  6d50              LDR      r0,[r2,#0x54]
000038  4398              BICS     r0,r0,r3
                  |L26.58|
00003a  6550              STR      r0,[r2,#0x54]         ;1096
;;;1104   		else
;;;1105   			base->OE &= ~(1 << ch);
;;;1106   	}
;;;1107   }
00003c  bd30              POP      {r4,r5,pc}
                  |L26.62|
00003e  6950              LDR      r0,[r2,#0x14]         ;1105
000040  43a0              BICS     r0,r0,r4              ;1105
                  |L26.66|
000042  6150              STR      r0,[r2,#0x14]         ;1098
000044  bd30              POP      {r4,r5,pc}
;;;1108   
                          ENDP

000046  0000              DCW      0x0000
                  |L26.72|
                          DCD      0x40040000
                  |L26.76|
                          DCD      0x40140000

                          AREA ||i.PWM0_IRQHandler||, CODE, READONLY, ALIGN=2

                  PWM0_IRQHandler PROC
;;;49     /*---------------------------------------------------------------------------------------------------------*/
;;;50     void PWM0_IRQHandler(void)
000000  b5f8              PUSH     {r3-r7,lr}
;;;51     {    
;;;52         uint8_t ch;
;;;53     	uint32_t reg;
;;;54     	
;;;55     	// gen
;;;56     	reg = PWM0->INTSTS;
000002  4815              LDR      r0,|L27.88|
000004  6907              LDR      r7,[r0,#0x10]
;;;57     	for(ch = 0; ch <= PWM_MAX_CH; ch++) {
000006  2400              MOVS     r4,#0
;;;58     		if(reg & (0x1 << ch)) {
;;;59     			if (g_sDrvPWM0Handler.pfnPWMCallBack[ch] != NULL)
000008  4e14              LDR      r6,|L27.92|
00000a  2501              MOVS     r5,#1                 ;58
                  |L27.12|
00000c  4628              MOV      r0,r5                 ;58
00000e  40a0              LSLS     r0,r0,r4              ;58
000010  4238              TST      r0,r7                 ;58
000012  d004              BEQ      |L27.30|
000014  00a0              LSLS     r0,r4,#2
000016  5830              LDR      r0,[r6,r0]
000018  2800              CMP      r0,#0
00001a  d000              BEQ      |L27.30|
;;;60     			{                           
;;;61     				g_sDrvPWM0Handler.pfnPWMCallBack[ch]();
00001c  4780              BLX      r0
                  |L27.30|
00001e  1c64              ADDS     r4,r4,#1              ;57
000020  b2e4              UXTB     r4,r4                 ;57
000022  2c03              CMP      r4,#3                 ;57
000024  d9f2              BLS      |L27.12|
;;;62     			}				
;;;63     		}
;;;64     	}
;;;65     	
;;;66     	
;;;67     	PWM0->INTSTS = reg;
000026  480c              LDR      r0,|L27.88|
000028  6107              STR      r7,[r0,#0x10]
;;;68     	// cap
;;;69     	reg = PWM0->CAPINTSTS;
00002a  480b              LDR      r0,|L27.88|
00002c  3040              ADDS     r0,r0,#0x40
00002e  69c7              LDR      r7,[r0,#0x1c]
;;;70     	
;;;71     	for(ch = 0; ch <= PWM_MAX_CH; ch++) {
000030  2400              MOVS     r4,#0
                  |L27.50|
;;;72     		if(reg & (1 << (8 * ch)))	 {
000032  00e1              LSLS     r1,r4,#3
000034  4628              MOV      r0,r5
000036  4088              LSLS     r0,r0,r1
000038  4238              TST      r0,r7
00003a  d005              BEQ      |L27.72|
;;;73     			if (g_sDrvPWM0Handler.pfnCAPCallBack[ch] != NULL)
00003c  00a0              LSLS     r0,r4,#2
00003e  1980              ADDS     r0,r0,r6
000040  6900              LDR      r0,[r0,#0x10]
000042  2800              CMP      r0,#0
000044  d000              BEQ      |L27.72|
;;;74     			{
;;;75     				g_sDrvPWM0Handler.pfnCAPCallBack[ch]();
000046  4780              BLX      r0
                  |L27.72|
000048  1c64              ADDS     r4,r4,#1              ;71
00004a  b2e4              UXTB     r4,r4                 ;71
00004c  2c03              CMP      r4,#3                 ;71
00004e  d9f0              BLS      |L27.50|
;;;76     			}					
;;;77     		}
;;;78     	}
;;;79     	
;;;80     	PWM0->CAPINTSTS = reg;//(reg & 0x01010101);
000050  4801              LDR      r0,|L27.88|
000052  3040              ADDS     r0,r0,#0x40
000054  61c7              STR      r7,[r0,#0x1c]
;;;81     
;;;82     	return;
;;;83     }
000056  bdf8              POP      {r3-r7,pc}
;;;84     
                          ENDP

                  |L27.88|
                          DCD      0x40040000
                  |L27.92|
                          DCD      ||.bss||

                          AREA ||i.PWM1_IRQHandler||, CODE, READONLY, ALIGN=2

                  PWM1_IRQHandler PROC
;;;95     /*---------------------------------------------------------------------------------------------------------*/
;;;96     void PWM1_IRQHandler(void)
000000  b5f8              PUSH     {r3-r7,lr}
;;;97     {    
;;;98         uint8_t ch;
;;;99     	uint32_t reg;
;;;100    	
;;;101    	// gen
;;;102    	reg = PWM1->INTSTS;
000002  4815              LDR      r0,|L28.88|
000004  6907              LDR      r7,[r0,#0x10]
;;;103    	for(ch = 0; ch <= PWM_MAX_CH; ch++) {
000006  2400              MOVS     r4,#0
;;;104    		if(reg & (0x1 << ch)) {
;;;105    			if (g_sDrvPWM1Handler.pfnPWMCallBack[ch] != NULL)
000008  4e14              LDR      r6,|L28.92|
00000a  2501              MOVS     r5,#1                 ;104
                  |L28.12|
00000c  4628              MOV      r0,r5                 ;104
00000e  40a0              LSLS     r0,r0,r4              ;104
000010  4238              TST      r0,r7                 ;104
000012  d004              BEQ      |L28.30|
000014  00a0              LSLS     r0,r4,#2
000016  5830              LDR      r0,[r6,r0]
000018  2800              CMP      r0,#0
00001a  d000              BEQ      |L28.30|
;;;106    			{                           
;;;107    				g_sDrvPWM1Handler.pfnPWMCallBack[ch]();
00001c  4780              BLX      r0
                  |L28.30|
00001e  1c64              ADDS     r4,r4,#1              ;103
000020  b2e4              UXTB     r4,r4                 ;103
000022  2c03              CMP      r4,#3                 ;103
000024  d9f2              BLS      |L28.12|
;;;108    			}				
;;;109    		}
;;;110    	}
;;;111    
;;;112    	PWM1->INTSTS = reg;
000026  480c              LDR      r0,|L28.88|
000028  6107              STR      r7,[r0,#0x10]
;;;113    	// cap
;;;114    	reg = PWM1->CAPINTSTS;
00002a  480b              LDR      r0,|L28.88|
00002c  3040              ADDS     r0,r0,#0x40
00002e  69c7              LDR      r7,[r0,#0x1c]
;;;115    	for(ch = 0; ch <= PWM_MAX_CH; ch++) {
000030  2400              MOVS     r4,#0
                  |L28.50|
;;;116    		if(reg & (1 << (8 * ch)))	 {
000032  00e1              LSLS     r1,r4,#3
000034  4628              MOV      r0,r5
000036  4088              LSLS     r0,r0,r1
000038  4238              TST      r0,r7
00003a  d005              BEQ      |L28.72|
;;;117    			if (g_sDrvPWM1Handler.pfnCAPCallBack[ch] != NULL)
00003c  00a0              LSLS     r0,r4,#2
00003e  1980              ADDS     r0,r0,r6
000040  6900              LDR      r0,[r0,#0x10]
000042  2800              CMP      r0,#0
000044  d000              BEQ      |L28.72|
;;;118    			{
;;;119    				g_sDrvPWM1Handler.pfnCAPCallBack[ch]();
000046  4780              BLX      r0
                  |L28.72|
000048  1c64              ADDS     r4,r4,#1              ;115
00004a  b2e4              UXTB     r4,r4                 ;115
00004c  2c03              CMP      r4,#3                 ;115
00004e  d9f0              BLS      |L28.50|
;;;120    			}					
;;;121    		}
;;;122    	}
;;;123    	
;;;124    
;;;125    	
;;;126    	PWM1->CAPINTSTS = reg;//(reg & 0x01010101);
000050  4801              LDR      r0,|L28.88|
000052  3040              ADDS     r0,r0,#0x40
000054  61c7              STR      r7,[r0,#0x1c]
;;;127    
;;;128    	return;
;;;129    }
000056  bdf8              POP      {r3-r7,pc}
;;;130    
                          ENDP

                  |L28.88|
                          DCD      0x40140000
                  |L28.92|
                          DCD      ||.bss||+0x20

                          AREA ||.bss||, DATA, NOINIT, ALIGN=2

                  g_sDrvPWM0Handler
                          %        32
                  g_sDrvPWM1Handler
                          %        32

                          AREA ||i.__ARM_common_switch8||, COMGROUP=__ARM_common_switch8, CODE, READONLY, ALIGN=1

                  __ARM_common_switch8 PROC
000000  b430              PUSH     {r4,r5}
000002  4674              MOV      r4,lr
000004  1e64              SUBS     r4,r4,#1
000006  7825              LDRB     r5,[r4,#0]
000008  1c64              ADDS     r4,r4,#1
00000a  42ab              CMP      r3,r5
00000c  d200              BCS      |L176.16|
00000e  461d              MOV      r5,r3
                  |L176.16|
000010  5d63              LDRB     r3,[r4,r5]
000012  005b              LSLS     r3,r3,#1
000014  18e3              ADDS     r3,r4,r3
000016  bc30              POP      {r4,r5}
000018  4718              BX       r3
                          ENDP

