; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\drvsys.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvsys.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvsys.crf ..\bsp\Driver\DrvSYS.c]
                          THUMB

                          AREA ||i.BOD_IRQHandler||, CODE, READONLY, ALIGN=2

                  BOD_IRQHandler PROC
;;;443    /*---------------------------------------------------------------------------------------------------------*/
;;;444    void BOD_IRQHandler(void)
000000  4802              LDR      r0,|L1.12|
;;;445    {
;;;446    	if (BOD_callbackFn != NULL)
000002  6800              LDR      r0,[r0,#0]  ; BOD_callbackFn
000004  2800              CMP      r0,#0
000006  d000              BEQ      |L1.10|
;;;447    		BOD_callbackFn();
000008  4700              BX       r0
                  |L1.10|
;;;448    }
00000a  4770              BX       lr
;;;449    
                          ENDP

                  |L1.12|
                          DCD      ||.data||

                          AREA ||i.DrvSYS_ClearClockSwitchStatus||, CODE, READONLY, ALIGN=2

                  DrvSYS_ClearClockSwitchStatus PROC
;;;1343   /*---------------------------------------------------------------------------------------------------------*/
;;;1344   void DrvSYS_ClearClockSwitchStatus(void)
000000  4802              LDR      r0,|L2.12|
;;;1345   {
;;;1346   	 CLK->CLKSTATUS_BITS.CLK_SW_FAIL = 1;
000002  68c1              LDR      r1,[r0,#0xc]
000004  2280              MOVS     r2,#0x80
000006  4311              ORRS     r1,r1,r2
000008  60c1              STR      r1,[r0,#0xc]
;;;1347   }
00000a  4770              BX       lr
;;;1348   
                          ENDP

                  |L2.12|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_ClearResetSource||, CODE, READONLY, ALIGN=1

                  DrvSYS_ClearResetSource PROC
;;;186    /*---------------------------------------------------------------------------------------------------------*/
;;;187    uint32_t DrvSYS_ClearResetSource(uint32_t u32Src)
000000  2105              MOVS     r1,#5
;;;188    {
;;;189    	GCR->RST_SRC = u32Src;
000002  0709              LSLS     r1,r1,#28
000004  6048              STR      r0,[r1,#4]
;;;190    	return 0;
000006  2000              MOVS     r0,#0
;;;191    }
000008  4770              BX       lr
;;;192    
                          ENDP


                          AREA ||i.DrvSYS_Delay||, CODE, READONLY, ALIGN=2

                  DrvSYS_Delay PROC
;;;1258   /*---------------------------------------------------------------------------------------------------------*/
;;;1259   void DrvSYS_Delay(uint32_t us)
000000  b510              PUSH     {r4,lr}
;;;1260   {
000002  4604              MOV      r4,r0
;;;1261   	SysTick->LOAD = (us * ((SystemCoreClock + 500000) / 1000000));
000004  480a              LDR      r0,|L4.48|
000006  4909              LDR      r1,|L4.44|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00000a  104a              ASRS     r2,r1,#1
00000c  1880              ADDS     r0,r0,r2
00000e  f7fffffe          BL       __aeabi_uidivmod
000012  4601              MOV      r1,r0
000014  4807              LDR      r0,|L4.52|
000016  4361              MULS     r1,r4,r1
000018  6141              STR      r1,[r0,#0x14]
;;;1262   	SysTick->VAL  = (0x00);
00001a  2100              MOVS     r1,#0
00001c  6181              STR      r1,[r0,#0x18]
;;;1263         SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
00001e  2105              MOVS     r1,#5
000020  6101              STR      r1,[r0,#0x10]
                  |L4.34|
;;;1264   
;;;1265       /* Waiting for down-count to zero */
;;;1266       while((SysTick->CTRL & (1 << 16)) == 0);
000022  6901              LDR      r1,[r0,#0x10]
000024  03c9              LSLS     r1,r1,#15
000026  d5fc              BPL      |L4.34|
;;;1267   }
000028  bd10              POP      {r4,pc}
;;;1268   
                          ENDP

00002a  0000              DCW      0x0000
                  |L4.44|
                          DCD      0x000f4240
                  |L4.48|
                          DCD      SystemCoreClock
                  |L4.52|
                          DCD      0xe000e000

                          AREA ||i.DrvSYS_DisableAutoTrim||, CODE, READONLY, ALIGN=2

                  DrvSYS_DisableAutoTrim PROC
;;;1396   /*---------------------------------------------------------------------------------------------------------*/
;;;1397   void DrvSYS_DisableAutoTrim(void)
000000  4806              LDR      r0,|L5.28|
;;;1398   {
;;;1399   	GCR->IRCTRIMCTL_BITS.TRIM_SEL = 0;
000002  6801              LDR      r1,[r0,#0]
000004  0889              LSRS     r1,r1,#2
000006  0089              LSLS     r1,r1,#2
000008  6001              STR      r1,[r0,#0]
;;;1400   	GCR->IRCTRIMIER = 0; /* disable trim-fail and 32K-error interrupt */
00000a  2100              MOVS     r1,#0
00000c  6041              STR      r1,[r0,#4]
;;;1401   	_pfIrcCallback = NULL;
00000e  4804              LDR      r0,|L5.32|
000010  6081              STR      r1,[r0,#8]  ; _pfIrcCallback
000012  2001              MOVS     r0,#1
000014  4903              LDR      r1,|L5.36|
000016  0440              LSLS     r0,r0,#17
000018  6008              STR      r0,[r1,#0]
;;;1402   	NVIC_DisableIRQ(HIRC_IRQn);
;;;1403   }
00001a  4770              BX       lr
;;;1404   
                          ENDP

                  |L5.28|
                          DCD      0x50000080
                  |L5.32|
                          DCD      ||.data||
                  |L5.36|
                          DCD      0xe000e180

                          AREA ||i.DrvSYS_DisablePOR||, CODE, READONLY, ALIGN=2

                  DrvSYS_DisablePOR PROC
;;;419    /*---------------------------------------------------------------------------------------------------------*/
;;;420    void DrvSYS_DisablePOR(void)
000000  490a              LDR      r1,|L6.44|
;;;421    {
;;;422    	uint32_t lock_sts = 0;
;;;423    
;;;424    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  6808              LDR      r0,[r1,#0]
000004  07c0              LSLS     r0,r0,#31
000006  17c0              ASRS     r0,r0,#31
000008  1c40              ADDS     r0,r0,#1
;;;425    	
;;;426    	if (lock_sts)	UNLOCKREG();
00000a  d001              BEQ      |L6.16|
00000c  2259              MOVS     r2,#0x59
00000e  600a              STR      r2,[r1,#0]
                  |L6.16|
000010  2216              MOVS     r2,#0x16
000012  600a              STR      r2,[r1,#0]
000014  2288              MOVS     r2,#0x88
000016  600a              STR      r2,[r1,#0]
;;;427    	GCR->PORCTL = 0x5AA5;
000018  4b04              LDR      r3,|L6.44|
00001a  4a05              LDR      r2,|L6.48|
00001c  3bc0              SUBS     r3,r3,#0xc0
00001e  621a              STR      r2,[r3,#0x20]
;;;428    	if (lock_sts)	LOCKREG();
000020  2800              CMP      r0,#0
000022  d001              BEQ      |L6.40|
000024  2000              MOVS     r0,#0
000026  6008              STR      r0,[r1,#0]
                  |L6.40|
;;;429    }
000028  4770              BX       lr
;;;430    
                          ENDP

00002a  0000              DCW      0x0000
                  |L6.44|
                          DCD      0x50000100
                  |L6.48|
                          DCD      0x00005aa5

                          AREA ||i.DrvSYS_EnableAutoTrim||, CODE, READONLY, ALIGN=2

                  DrvSYS_EnableAutoTrim PROC
;;;1365   /*---------------------------------------------------------------------------------------------------------*/
;;;1366   int32_t DrvSYS_EnableAutoTrim(E_SYS_IRC_CLKSEL eTrimClk, DRVSYS_IRC_CALLBACK pfncallback)
000000  b530              PUSH     {r4,r5,lr}
;;;1367   {
;;;1368   	if (CLK->PWRCTL_BITS.LXT_EN != 1)	/* Not enable the 32K */
000002  4a0e              LDR      r2,|L7.60|
000004  6812              LDR      r2,[r2,#0]
000006  0792              LSLS     r2,r2,#30
000008  d401              BMI      |L7.14|
;;;1369   		return E_DRVSYS_ERR_32K_CLK_FAIL;
00000a  480d              LDR      r0,|L7.64|
;;;1370   
;;;1371   	g_trimClk = eTrimClk;
;;;1372   
;;;1373   	GCR->IRCTRIMCTL_BITS.TRIM_LOOP = 3;
;;;1374   
;;;1375   	_pfIrcCallback = (void (*)(uint32_t))pfncallback;
;;;1376   
;;;1377   	GCR->IRCTRIMIER = 0x6; /* enable trim-fail and 32K-error interrupt */
;;;1378   	NVIC_EnableIRQ(HIRC_IRQn);
;;;1379   
;;;1380   	GCR->IRCTRIMCTL_BITS.TRIM_SEL = eTrimClk;
;;;1381   
;;;1382   	return E_SUCCESS;
;;;1383   }
00000c  bd30              POP      {r4,r5,pc}
                  |L7.14|
00000e  4c0d              LDR      r4,|L7.68|
000010  4a0d              LDR      r2,|L7.72|
000012  60e0              STR      r0,[r4,#0xc]          ;1373  ; g_trimClk
000014  6813              LDR      r3,[r2,#0]            ;1373
000016  2530              MOVS     r5,#0x30              ;1373
000018  432b              ORRS     r3,r3,r5              ;1373
00001a  6013              STR      r3,[r2,#0]            ;1373
00001c  60a1              STR      r1,[r4,#8]            ;1377  ; _pfIrcCallback
00001e  2106              MOVS     r1,#6                 ;1377
000020  6051              STR      r1,[r2,#4]            ;1377
000022  4b0a              LDR      r3,|L7.76|
000024  0291              LSLS     r1,r2,#10             ;1377
000026  6019              STR      r1,[r3,#0]            ;1377
000028  6811              LDR      r1,[r2,#0]            ;1380
00002a  0780              LSLS     r0,r0,#30             ;1380
00002c  0889              LSRS     r1,r1,#2              ;1380
00002e  0089              LSLS     r1,r1,#2              ;1380
000030  0f80              LSRS     r0,r0,#30             ;1380
000032  4301              ORRS     r1,r1,r0              ;1380
000034  6011              STR      r1,[r2,#0]            ;1380
000036  2000              MOVS     r0,#0                 ;1382
000038  bd30              POP      {r4,r5,pc}
;;;1384   
                          ENDP

00003a  0000              DCW      0x0000
                  |L7.60|
                          DCD      0x50000200
                  |L7.64|
                          DCD      0xffff960b
                  |L7.68|
                          DCD      ||.data||
                  |L7.72|
                          DCD      0x50000080
                  |L7.76|
                          DCD      0xe000e100

                          AREA ||i.DrvSYS_EnablePOR||, CODE, READONLY, ALIGN=2

                  DrvSYS_EnablePOR PROC
;;;397    /*---------------------------------------------------------------------------------------------------------*/
;;;398    void DrvSYS_EnablePOR(void)
000000  4909              LDR      r1,|L8.40|
;;;399    {
;;;400    	uint32_t lock_sts = 0;
;;;401    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  6808              LDR      r0,[r1,#0]
000004  07c0              LSLS     r0,r0,#31
000006  17c0              ASRS     r0,r0,#31
000008  1c40              ADDS     r0,r0,#1
;;;402    
;;;403    	if (lock_sts)	UNLOCKREG();
00000a  d001              BEQ      |L8.16|
00000c  2259              MOVS     r2,#0x59
00000e  600a              STR      r2,[r1,#0]
                  |L8.16|
000010  2216              MOVS     r2,#0x16
000012  600a              STR      r2,[r1,#0]
000014  2288              MOVS     r2,#0x88
000016  600a              STR      r2,[r1,#0]
;;;404    	GCR->PORCTL = 0;
000018  4b03              LDR      r3,|L8.40|
00001a  2200              MOVS     r2,#0
00001c  3bc0              SUBS     r3,r3,#0xc0
00001e  621a              STR      r2,[r3,#0x20]
;;;405    	if (lock_sts)	LOCKREG();
000020  2800              CMP      r0,#0
000022  d000              BEQ      |L8.38|
000024  600a              STR      r2,[r1,#0]
                  |L8.38|
;;;406    }
000026  4770              BX       lr
;;;407    
                          ENDP

                  |L8.40|
                          DCD      0x50000100

                          AREA ||i.DrvSYS_EnterPowerDown||, CODE, READONLY, ALIGN=2

                  DrvSYS_EnterPowerDown PROC
;;;747    /*---------------------------------------------------------------------------------------------------------*/
;;;748    void DrvSYS_EnterPowerDown(void)
000000  b510              PUSH     {r4,lr}
;;;749    {	
;;;750    	uint32_t lock_sts = 0;
;;;751    	
;;;752    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  490b              LDR      r1,|L9.48|
000004  6808              LDR      r0,[r1,#0]
000006  07c0              LSLS     r0,r0,#31
000008  17c0              ASRS     r0,r0,#31
00000a  1c40              ADDS     r0,r0,#1
;;;753    	
;;;754    	if (lock_sts)	UNLOCKREG();
00000c  d001              BEQ      |L9.18|
00000e  2259              MOVS     r2,#0x59
000010  600a              STR      r2,[r1,#0]
                  |L9.18|
000012  2216              MOVS     r2,#0x16
000014  600a              STR      r2,[r1,#0]
000016  2288              MOVS     r2,#0x88
000018  600a              STR      r2,[r1,#0]
;;;755    	CLK->PWRCTL_BITS.PD_EN = 1;
00001a  4b06              LDR      r3,|L9.52|
00001c  681a              LDR      r2,[r3,#0]
00001e  2440              MOVS     r4,#0x40
000020  4322              ORRS     r2,r2,r4
000022  601a              STR      r2,[r3,#0]
;;;756    	if (lock_sts)	LOCKREG();	
000024  2800              CMP      r0,#0
000026  d001              BEQ      |L9.44|
000028  2000              MOVS     r0,#0
00002a  6008              STR      r0,[r1,#0]
                  |L9.44|
;;;757    }
00002c  bd10              POP      {r4,pc}
;;;758    
                          ENDP

00002e  0000              DCW      0x0000
                  |L9.48|
                          DCD      0x50000100
                  |L9.52|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_GetBODState||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetBODState PROC
;;;375    /*---------------------------------------------------------------------------------------------------------*/
;;;376    uint32_t DrvSYS_GetBODState(void)
000000  4806              LDR      r0,|L10.28|
;;;377    {
;;;378    	if (GCR->BODSTS & 0x00000001)  {
000002  6a81              LDR      r1,[r0,#0x28]
000004  07c9              LSLS     r1,r1,#31
000006  d007              BEQ      |L10.24|
;;;379    		GCR->BODSTS_BITS.BOD_INT = 1; /* clear interrupt status */
000008  6a81              LDR      r1,[r0,#0x28]
00000a  2201              MOVS     r2,#1
00000c  4311              ORRS     r1,r1,r2
00000e  6281              STR      r1,[r0,#0x28]
;;;380    		return (GCR->BODSTS & 0x0000007E);
000010  6a80              LDR      r0,[r0,#0x28]
000012  217e              MOVS     r1,#0x7e
000014  4008              ANDS     r0,r0,r1
;;;381    	}
;;;382    	else
;;;383    		return 0;
;;;384    }
000016  4770              BX       lr
                  |L10.24|
000018  2000              MOVS     r0,#0                 ;383
00001a  4770              BX       lr
;;;385    
                          ENDP

                  |L10.28|
                          DCD      0x50000040

                          AREA ||i.DrvSYS_GetChipClockSourceStatus||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetChipClockSourceStatus PROC
;;;1283   /*---------------------------------------------------------------------------------------------------------*/
;;;1284   int32_t DrvSYS_GetChipClockSourceStatus(E_SYS_CHIP_CLKSRC eClkSrc)
000000  490f              LDR      r1,|L11.64|
;;;1285   {
;;;1286   	int32_t status;
;;;1287   
;;;1288   	switch(eClkSrc)
000002  2804              CMP      r0,#4
000004  d012              BEQ      |L11.44|
000006  dc04              BGT      |L11.18|
000008  2801              CMP      r0,#1
00000a  d008              BEQ      |L11.30|
00000c  2802              CMP      r0,#2
00000e  d104              BNE      |L11.26|
000010  e009              B        |L11.38|
                  |L11.18|
000012  2808              CMP      r0,#8
000014  d00d              BEQ      |L11.50|
000016  2810              CMP      r0,#0x10
000018  d00e              BEQ      |L11.56|
                  |L11.26|
;;;1289   	{
;;;1290   		case E_SYS_HXT:  
;;;1291   			status = CLK->CLKSTATUS_BITS.HXT_STB;
;;;1292   			break;
;;;1293   		case E_SYS_LXT:
;;;1294   			status = CLK->CLKSTATUS_BITS.LXT_STB;
;;;1295   			break;
;;;1296   		case E_SYS_HIRC:
;;;1297   			status = CLK->CLKSTATUS_BITS.HIRC_STB;
;;;1298   			break;
;;;1299   		case E_SYS_LIRC:
;;;1300   			status = CLK->CLKSTATUS_BITS.LIRC_STB;
;;;1301   			break;				
;;;1302   		case E_SYS_PLL:
;;;1303   			status = CLK->CLKSTATUS_BITS.PLL_STB;
;;;1304   			break;
;;;1305   		default:
;;;1306   			return E_DRVSYS_ERR_ARGUMENT;
00001a  480a              LDR      r0,|L11.68|
;;;1307   	}
;;;1308   
;;;1309   	return status;		
;;;1310   }
00001c  4770              BX       lr
                  |L11.30|
00001e  68c8              LDR      r0,[r1,#0xc]          ;1291
000020  07c0              LSLS     r0,r0,#31             ;1291
000022  0fc0              LSRS     r0,r0,#31             ;1291
000024  4770              BX       lr
                  |L11.38|
000026  68c8              LDR      r0,[r1,#0xc]          ;1294
000028  0780              LSLS     r0,r0,#30             ;1294
00002a  e007              B        |L11.60|
                  |L11.44|
00002c  68c8              LDR      r0,[r1,#0xc]          ;1297
00002e  06c0              LSLS     r0,r0,#27             ;1297
000030  e004              B        |L11.60|
                  |L11.50|
000032  68c8              LDR      r0,[r1,#0xc]          ;1300
000034  0700              LSLS     r0,r0,#28             ;1300
000036  e001              B        |L11.60|
                  |L11.56|
000038  68c8              LDR      r0,[r1,#0xc]          ;1303
00003a  0740              LSLS     r0,r0,#29             ;1303
                  |L11.60|
00003c  0fc0              LSRS     r0,r0,#31             ;1303
00003e  4770              BX       lr
;;;1311   
                          ENDP

                  |L11.64|
                          DCD      0x50000200
                  |L11.68|
                          DCD      0xffff9603

                          AREA ||i.DrvSYS_GetClockSwitchStatus||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetClockSwitchStatus PROC
;;;1326   /*---------------------------------------------------------------------------------------------------------*/
;;;1327   uint32_t DrvSYS_GetClockSwitchStatus(void)
000000  4802              LDR      r0,|L12.12|
;;;1328   {	
;;;1329   	return CLK->CLKSTATUS_BITS.CLK_SW_FAIL;
000002  68c0              LDR      r0,[r0,#0xc]
000004  0600              LSLS     r0,r0,#24
000006  0fc0              LSRS     r0,r0,#31
;;;1330   }
000008  4770              BX       lr
;;;1331   
                          ENDP

00000a  0000              DCW      0x0000
                  |L12.12|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_GetExtClockFreq||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetExtClockFreq PROC
;;;806    /*---------------------------------------------------------------------------------------------------------*/
;;;807    uint32_t DrvSYS_GetExtClockFreq(void)
000000  4800              LDR      r0,|L13.4|
;;;808    {	
;;;809    	return __XTAL;
;;;810    }
000002  4770              BX       lr
;;;811    
                          ENDP

                  |L13.4|
                          DCD      0x00b71b00

                          AREA ||i.DrvSYS_GetHCLKFreq||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetHCLKFreq PROC
;;;972    /*---------------------------------------------------------------------------------------------------------*/
;;;973    uint32_t DrvSYS_GetHCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;974    {
;;;975    	
;;;976    	uint32_t u32Freqout = 0, u32AHBDivider, u32ClkSel;
;;;977    
;;;978    	u32ClkSel = CLK->CLKSEL0 & 0x07;
000002  4c0d              LDR      r4,|L14.56|
000004  6920              LDR      r0,[r4,#0x10]
000006  0741              LSLS     r1,r0,#29
;;;979    
;;;980    	if (u32ClkSel == 0)			/* external 12MHz crystal clock */
;;;981    	{
;;;982    		u32Freqout = __XTAL;	
000008  480c              LDR      r0,|L14.60|
00000a  0f49              LSRS     r1,r1,#29             ;978
00000c  d00d              BEQ      |L14.42|
;;;983    	}
;;;984    	else if(u32ClkSel == 1)		/* external 32KHz crystal clock */ 
00000e  2901              CMP      r1,#1
000010  d004              BEQ      |L14.28|
;;;985    	{
;;;986    		u32Freqout = __RTC_XTAL;
;;;987    	}
;;;988    	else if(u32ClkSel == 2)		/* PLL clock */
000012  2902              CMP      r1,#2
000014  d005              BEQ      |L14.34|
;;;989    	{
;;;990    		u32Freqout = DrvSYS_GetPLLClockFreq();
;;;991    	}
;;;992    	else if(u32ClkSel == 3)	/* internal 10KHz oscillator clock */
000016  2903              CMP      r1,#3
000018  d006              BEQ      |L14.40|
00001a  e006              B        |L14.42|
                  |L14.28|
00001c  2001              MOVS     r0,#1                 ;986
00001e  03c0              LSLS     r0,r0,#15             ;986
000020  e003              B        |L14.42|
                  |L14.34|
000022  f7fffffe          BL       DrvSYS_GetPLLClockFreq
000026  e000              B        |L14.42|
                  |L14.40|
;;;993    	{
;;;994    	 	u32Freqout = __IRC10K;
000028  4805              LDR      r0,|L14.64|
                  |L14.42|
;;;995    	}
;;;996    	else									/* internal 12MHz oscillator clock */
;;;997    	{
;;;998    	 	u32Freqout = __IRC12M;
;;;999    	
;;;1000   	}
;;;1001   	u32AHBDivider = CLK->CLKDIV0_BITS.HCLK_N + 1 ;
00002a  69e1              LDR      r1,[r4,#0x1c]
00002c  0709              LSLS     r1,r1,#28
00002e  0f09              LSRS     r1,r1,#28
000030  1c49              ADDS     r1,r1,#1
;;;1002   	
;;;1003   	return (u32Freqout/u32AHBDivider);	
000032  f7fffffe          BL       __aeabi_uidivmod
;;;1004   }
000036  bd10              POP      {r4,pc}
;;;1005   
                          ENDP

                  |L14.56|
                          DCD      0x50000200
                  |L14.60|
                          DCD      0x00b71b00
                  |L14.64|
                          DCD      0x00002710

                          AREA ||i.DrvSYS_GetPLLClockFreq||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetPLLClockFreq PROC
;;;925    /*---------------------------------------------------------------------------------------------------------*/
;;;926    uint32_t DrvSYS_GetPLLClockFreq(void)
000000  b510              PUSH     {r4,lr}
;;;927    {
;;;928    	uint32_t u32Freq =0, u32PLLSrc;
;;;929        uint32_t u32NO, u32NR;
;;;930    
;;;931    	if (CLK->PLLCTL_BITS.PLL_SRC == 1)
000002  4a16              LDR      r2,|L15.92|
000004  2000              MOVS     r0,#0                 ;928
000006  6a51              LDR      r1,[r2,#0x24]
;;;932    	{
;;;933    		u32PLLSrc = __IRC12M;
;;;934    	}
;;;935    	else
;;;936    	{
;;;937    		u32PLLSrc = __XTAL;
;;;938    	}
;;;939    
;;;940        u32NO = ((CLK->PLLCTL_BITS.OUT_DV)? 2: 1);
000008  6a51              LDR      r1,[r2,#0x24]
00000a  04c9              LSLS     r1,r1,#19
00000c  d501              BPL      |L15.18|
00000e  2402              MOVS     r4,#2
000010  e000              B        |L15.20|
                  |L15.18|
000012  2401              MOVS     r4,#1
                  |L15.20|
;;;941    
;;;942    	if (CLK->PLLCTL_BITS.IN_DV == 0)
000014  6a51              LDR      r1,[r2,#0x24]
000016  0589              LSLS     r1,r1,#22
000018  0f89              LSRS     r1,r1,#30
00001a  d019              BEQ      |L15.80|
;;;943    		u32NR = 2;
;;;944    	else if (CLK->PLLCTL_BITS.IN_DV == 1)
00001c  6a51              LDR      r1,[r2,#0x24]
00001e  0589              LSLS     r1,r1,#22
000020  0f89              LSRS     r1,r1,#30
000022  2901              CMP      r1,#1
000024  d016              BEQ      |L15.84|
;;;945    		u32NR = 4;
;;;946    	else if (CLK->PLLCTL_BITS.IN_DV == 2)
000026  6a51              LDR      r1,[r2,#0x24]
000028  0589              LSLS     r1,r1,#22
00002a  0f89              LSRS     r1,r1,#30
00002c  2902              CMP      r1,#2
00002e  d013              BEQ      |L15.88|
;;;947    		u32NR = 8;
;;;948    	else
;;;949    		u32NR = 16;
000030  2110              MOVS     r1,#0x10
                  |L15.50|
;;;950    
;;;951    	if (CLK->PLLCTL_BITS.PD == 1)
000032  6a53              LDR      r3,[r2,#0x24]
000034  03db              LSLS     r3,r3,#15
000036  d40a              BMI      |L15.78|
;;;952    		u32Freq = 0;	
;;;953    	else		
;;;954    		u32Freq = u32PLLSrc * (CLK->PLLCTL_BITS.FB_DV+32) / u32NR / u32NO;
000038  6a50              LDR      r0,[r2,#0x24]
00003a  4a09              LDR      r2,|L15.96|
00003c  0680              LSLS     r0,r0,#26
00003e  0e80              LSRS     r0,r0,#26
000040  3020              ADDS     r0,r0,#0x20
000042  4350              MULS     r0,r2,r0
000044  f7fffffe          BL       __aeabi_uidivmod
000048  4621              MOV      r1,r4
00004a  f7fffffe          BL       __aeabi_uidivmod
                  |L15.78|
;;;955    
;;;956    	return u32Freq;
;;;957    }
00004e  bd10              POP      {r4,pc}
                  |L15.80|
000050  2102              MOVS     r1,#2                 ;943
000052  e7ee              B        |L15.50|
                  |L15.84|
000054  2104              MOVS     r1,#4                 ;945
000056  e7ec              B        |L15.50|
                  |L15.88|
000058  2108              MOVS     r1,#8                 ;947
00005a  e7ea              B        |L15.50|
;;;958    
                          ENDP

                  |L15.92|
                          DCD      0x50000200
                  |L15.96|
                          DCD      0x00b71b00

                          AREA ||i.DrvSYS_GetPLLContent||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetPLLContent PROC
;;;828    /*---------------------------------------------------------------------------------------------------------*/
;;;829    uint32_t DrvSYS_GetPLLContent(E_SYS_PLL_CLKSRC ePllSrc, uint32_t u32PllClk)
000000  b5f3              PUSH     {r0,r1,r4-r7,lr}
;;;830    {
000002  4607              MOV      r7,r0
000004  4608              MOV      r0,r1
;;;831       uint32_t u32PllSrcClk, u32Register, u32Factor;
;;;832       uint32_t u32NR, u32NF, u32NO, u32IN_DV;
;;;833      	
;;;834       u32PllSrcClk = 0;
;;;835       u32Register=0;
;;;836    
;;;837        if (u32PllClk > FREQ_120MHZ)  
000006  4926              LDR      r1,|L16.160|
000008  2400              MOVS     r4,#0                 ;834
00000a  b081              SUB      sp,sp,#4              ;830
00000c  4288              CMP      r0,r1
00000e  d901              BLS      |L16.20|
;;;838    		return 0x31120;
000010  4824              LDR      r0,|L16.164|
                  |L16.18|
;;;839    
;;;840        if (ePllSrc == E_SYS_EXTERNAL_HXT)
;;;841    		u32PllSrcClk = __XTAL;
;;;842        else if (ePllSrc == E_SYS_INTERNAL_HIRC)
;;;843    		u32PllSrcClk =  __IRC12M;	
;;;844     
;;;845        u32PllClk    /= 1000000;
;;;846        u32PllSrcClk /= 1000000;
;;;847        
;;;848        u32Factor = u32PllClk / u32PllSrcClk;
;;;849            
;;;850        if (u32Factor < 2)  {
;;;851    		u32NO = 2; 
;;;852    		u32NR = 16;
;;;853    		u32IN_DV = 3;
;;;854        }
;;;855        else {
;;;856    		u32NO = 1;
;;;857    
;;;858    		if (u32Factor < 4)  {
;;;859    			u32NR = 16;
;;;860    			u32IN_DV = 3;
;;;861    		}
;;;862    		else if (u32Factor < 8) {
;;;863    			u32NR = 8;
;;;864    			u32IN_DV = 2;
;;;865    		}
;;;866    		else if (u32Factor < 16)  {
;;;867    			u32NR = 4;
;;;868    			u32IN_DV = 1;
;;;869    		}
;;;870    		else  {
;;;871    			u32NR = 2;
;;;872    			u32IN_DV = 0;
;;;873    		}
;;;874        }
;;;875    
;;;876        u32NF = ((u32PllClk * 100) / u32PllSrcClk) * u32NR * u32NO;
;;;877        if ((u32NF % 100) >= 50)
;;;878    		u32NF = (u32NF / 100) + 1;
;;;879        else
;;;880    		u32NF = (u32NF / 100);
;;;881    
;;;882        u32Register = ((u32NO -1 ) <<12) | (u32IN_DV << 8) | (u32NF - 32);
;;;883    
;;;884        if (ePllSrc == E_SYS_INTERNAL_HIRC)
;;;885    		u32Register |= 0x00020000;
;;;886    
;;;887        /* Return the nearest value */
;;;888        return u32Register;
;;;889    	
;;;890    }
000012  bdfe              POP      {r1-r7,pc}
                  |L16.20|
000014  4924              LDR      r1,|L16.168|
000016  2f00              CMP      r7,#0                 ;840
000018  d001              BEQ      |L16.30|
00001a  2f01              CMP      r7,#1                 ;842
00001c  d100              BNE      |L16.32|
                  |L16.30|
00001e  460c              MOV      r4,r1                 ;843
                  |L16.32|
000020  4d22              LDR      r5,|L16.172|
000022  4629              MOV      r1,r5                 ;845
000024  f7fffffe          BL       __aeabi_uidivmod
000028  9002              STR      r0,[sp,#8]            ;846
00002a  4629              MOV      r1,r5                 ;846
00002c  4620              MOV      r0,r4                 ;846
00002e  f7fffffe          BL       __aeabi_uidivmod
000032  4601              MOV      r1,r0                 ;848
000034  9000              STR      r0,[sp,#0]            ;848
000036  9802              LDR      r0,[sp,#8]            ;848
000038  f7fffffe          BL       __aeabi_uidivmod
00003c  2802              CMP      r0,#2                 ;850
00003e  d201              BCS      |L16.68|
000040  2602              MOVS     r6,#2                 ;851
000042  e002              B        |L16.74|
                  |L16.68|
000044  2601              MOVS     r6,#1                 ;856
000046  2804              CMP      r0,#4                 ;858
000048  d202              BCS      |L16.80|
                  |L16.74|
00004a  2410              MOVS     r4,#0x10              ;859
00004c  2503              MOVS     r5,#3                 ;860
00004e  e00b              B        |L16.104|
                  |L16.80|
000050  2808              CMP      r0,#8                 ;862
000052  d202              BCS      |L16.90|
000054  2408              MOVS     r4,#8                 ;863
000056  2502              MOVS     r5,#2                 ;864
000058  e006              B        |L16.104|
                  |L16.90|
00005a  2810              CMP      r0,#0x10              ;866
00005c  d202              BCS      |L16.100|
00005e  2404              MOVS     r4,#4                 ;867
000060  2501              MOVS     r5,#1                 ;868
000062  e001              B        |L16.104|
                  |L16.100|
000064  2402              MOVS     r4,#2                 ;871
000066  2500              MOVS     r5,#0                 ;872
                  |L16.104|
000068  9802              LDR      r0,[sp,#8]            ;876
00006a  2164              MOVS     r1,#0x64              ;876
00006c  4348              MULS     r0,r1,r0              ;876
00006e  9900              LDR      r1,[sp,#0]            ;876
000070  f7fffffe          BL       __aeabi_uidivmod
000074  4360              MULS     r0,r4,r0              ;876
000076  4370              MULS     r0,r6,r0              ;876
000078  2164              MOVS     r1,#0x64              ;877
00007a  f7fffffe          BL       __aeabi_uidivmod
00007e  2932              CMP      r1,#0x32              ;877
000080  d300              BCC      |L16.132|
000082  1c40              ADDS     r0,r0,#1              ;878
                  |L16.132|
000084  4601              MOV      r1,r0                 ;880
000086  4a0a              LDR      r2,|L16.176|
000088  0330              LSLS     r0,r6,#12             ;882
00008a  1880              ADDS     r0,r0,r2              ;882
00008c  022a              LSLS     r2,r5,#8              ;882
00008e  4310              ORRS     r0,r0,r2              ;882
000090  3920              SUBS     r1,r1,#0x20           ;882
000092  4308              ORRS     r0,r0,r1              ;882
000094  2f01              CMP      r7,#1                 ;884
000096  d1bc              BNE      |L16.18|
000098  0479              LSLS     r1,r7,#17             ;885
00009a  4308              ORRS     r0,r0,r1              ;885
00009c  bdfe              POP      {r1-r7,pc}
;;;891    
                          ENDP

00009e  0000              DCW      0x0000
                  |L16.160|
                          DCD      0x07270e00
                  |L16.164|
                          DCD      0x00031120
                  |L16.168|
                          DCD      0x00b71b00
                  |L16.172|
                          DCD      0x000f4240
                  |L16.176|
                          DCD      0xfffff000

                          AREA ||i.DrvSYS_GetResetSource||, CODE, READONLY, ALIGN=1

                  DrvSYS_GetResetSource PROC
;;;170    /*---------------------------------------------------------------------------------------------------------*/
;;;171    uint32_t DrvSYS_GetResetSource(void)
000000  2005              MOVS     r0,#5
;;;172    {
;;;173    	return GCR->RST_SRC;
000002  0700              LSLS     r0,r0,#28
000004  6840              LDR      r0,[r0,#4]
;;;174    }
000006  4770              BX       lr
;;;175    
                          ENDP


                          AREA ||i.DrvSYS_GetVersion||, CODE, READONLY, ALIGN=2

                  DrvSYS_GetVersion PROC
;;;73     /*---------------------------------------------------------------------------------------------------------*/
;;;74     uint32_t DrvSYS_GetVersion(void)
000000  4800              LDR      r0,|L18.4|
;;;75     {
;;;76     	return DRVSYS_VERSION_NUM;
;;;77     }
000002  4770              BX       lr
;;;78     
                          ENDP

                  |L18.4|
                          DCD      0x00010001

                          AREA ||i.DrvSYS_IsProtectedRegLocked||, CODE, READONLY, ALIGN=2

                  DrvSYS_IsProtectedRegLocked PROC
;;;153    /*---------------------------------------------------------------------------------------------------------*/
;;;154    int32_t DrvSYS_IsProtectedRegLocked(void)
000000  4802              LDR      r0,|L19.12|
;;;155    {
;;;156    	return GCR->RegLockAddr & 0x01;
000002  6800              LDR      r0,[r0,#0]
000004  07c0              LSLS     r0,r0,#31
000006  0fc0              LSRS     r0,r0,#31
;;;157    }
000008  4770              BX       lr
;;;158    
                          ENDP

00000a  0000              DCW      0x0000
                  |L19.12|
                          DCD      0x50000100

                          AREA ||i.DrvSYS_LockProtectedReg||, CODE, READONLY, ALIGN=2

                  DrvSYS_LockProtectedReg PROC
;;;131    /*---------------------------------------------------------------------------------------------------------*/
;;;132    int32_t DrvSYS_LockProtectedReg(void)
000000  4804              LDR      r0,|L20.20|
;;;133    {
;;;134    	uint32_t lockbit;
;;;135    
;;;136    	GCR->RegLockAddr = 0x00;	
000002  2100              MOVS     r1,#0
000004  6001              STR      r1,[r0,#0]
;;;137    
;;;138    	lockbit = GCR->RegLockAddr & 0x01;
000006  6800              LDR      r0,[r0,#0]
000008  07c0              LSLS     r0,r0,#31
00000a  0fc0              LSRS     r0,r0,#31
;;;139    	return (lockbit)? E_DRVSYS_ERR_LOCK_FAIL : 0;
00000c  d000              BEQ      |L20.16|
00000e  4802              LDR      r0,|L20.24|
                  |L20.16|
;;;140    }
000010  4770              BX       lr
;;;141    
                          ENDP

000012  0000              DCW      0x0000
                  |L20.20|
                          DCD      0x50000100
                  |L20.24|
                          DCD      0xffff9602

                          AREA ||i.DrvSYS_Open||, CODE, READONLY, ALIGN=2

                  DrvSYS_Open PROC
;;;1022   /*---------------------------------------------------------------------------------------------------------*/
;;;1023   int32_t DrvSYS_Open(uint32_t u32Hclk)
000000  b570              PUSH     {r4-r6,lr}
;;;1024   {
000002  4601              MOV      r1,r0
;;;1025   	uint32_t u32PllCr;	
;;;1026   	volatile uint32_t delayCnt;
;;;1027   	E_SYS_PLL_CLKSRC ePllSrc = E_SYS_EXTERNAL_HXT;
;;;1028   
;;;1029   	if (u32Hclk > FREQ_32MHZ)
000004  4a18              LDR      r2,|L21.104|
000006  2000              MOVS     r0,#0                 ;1027
000008  4291              CMP      r1,r2
00000a  d901              BLS      |L21.16|
;;;1030   	{
;;;1031   		return E_DRVSYS_ERR_OUT_OF_RANGE;
00000c  4817              LDR      r0,|L21.108|
;;;1032   	}
;;;1033   		
;;;1034   	if (CLK->PLLCTL_BITS.PLL_SRC == 0)
;;;1035   	{
;;;1036   		CLK->PWRCTL_BITS.HXT_EN = 1;
;;;1037   		ePllSrc = E_SYS_EXTERNAL_HXT;
;;;1038   	}
;;;1039   	else
;;;1040   	{
;;;1041   		CLK->PWRCTL_BITS.HIRC_EN = 1;
;;;1042   		ePllSrc = E_SYS_INTERNAL_HIRC;
;;;1043   	}
;;;1044   
;;;1045   	u32PllCr = DrvSYS_GetPLLContent(ePllSrc, u32Hclk);
;;;1046   		
;;;1047   	/*Delay for 12M stable*/
;;;1048   	for (delayCnt=0;delayCnt<10000;delayCnt++);		
;;;1049   
;;;1050   	DrvSYS_SelectHCLKSource(E_SYS_SEL0_HCLK_HIRC); /* select HIRC for HCLk temporarily */
;;;1051   	DrvSYS_SetPLLContent(u32PllCr);
;;;1052   
;;;1053   	CLK->PLLCTL_BITS.PD = 0;
;;;1054   	
;;;1055   	/*Delay for PLL stable*/
;;;1056   	for (delayCnt=0;delayCnt<10000;delayCnt++);
;;;1057   
;;;1058   	/* Change HCLK clock source to be PLL. */
;;;1059   	CLK->CLKDIV0_BITS.HCLK_N = 0;  /* HCLK is the same as PLL output */
;;;1060   	DrvSYS_SelectHCLKSource(E_SYS_SEL0_HCLK_PLL);
;;;1061   
;;;1062   	return E_SUCCESS;
;;;1063   
;;;1064   }
00000e  bd70              POP      {r4-r6,pc}
                  |L21.16|
000010  4d17              LDR      r5,|L21.112|
000012  6a6a              LDR      r2,[r5,#0x24]         ;1034
000014  0392              LSLS     r2,r2,#14             ;1034
000016  d404              BMI      |L21.34|
000018  682a              LDR      r2,[r5,#0]            ;1036
00001a  2301              MOVS     r3,#1                 ;1036
00001c  431a              ORRS     r2,r2,r3              ;1036
00001e  602a              STR      r2,[r5,#0]            ;1036
000020  e004              B        |L21.44|
                  |L21.34|
000022  6828              LDR      r0,[r5,#0]            ;1041
000024  2204              MOVS     r2,#4                 ;1041
000026  4310              ORRS     r0,r0,r2              ;1041
000028  6028              STR      r0,[r5,#0]            ;1041
00002a  2001              MOVS     r0,#1                 ;1042
                  |L21.44|
00002c  f7fffffe          BL       DrvSYS_GetPLLContent
000030  4606              MOV      r6,r0                 ;1045
000032  4c10              LDR      r4,|L21.116|
000034  2000              MOVS     r0,#0                 ;1048
                  |L21.54|
000036  1c40              ADDS     r0,r0,#1              ;1048
000038  42a0              CMP      r0,r4                 ;1048
00003a  d3fc              BCC      |L21.54|
00003c  2007              MOVS     r0,#7                 ;1050
00003e  f7fffffe          BL       DrvSYS_SelectHCLKSource
000042  626e              STR      r6,[r5,#0x24]         ;1050
000044  6a68              LDR      r0,[r5,#0x24]         ;1053
000046  2101              MOVS     r1,#1                 ;1053
000048  0409              LSLS     r1,r1,#16             ;1053
00004a  4388              BICS     r0,r0,r1              ;1053
00004c  6268              STR      r0,[r5,#0x24]         ;1053
00004e  2000              MOVS     r0,#0                 ;1056
                  |L21.80|
000050  1c40              ADDS     r0,r0,#1              ;1056
000052  42a0              CMP      r0,r4                 ;1056
000054  d3fc              BCC      |L21.80|
000056  69e8              LDR      r0,[r5,#0x1c]         ;1059
000058  0900              LSRS     r0,r0,#4              ;1059
00005a  0100              LSLS     r0,r0,#4              ;1059
00005c  61e8              STR      r0,[r5,#0x1c]         ;1059
00005e  2002              MOVS     r0,#2                 ;1060
000060  f7fffffe          BL       DrvSYS_SelectHCLKSource
000064  2000              MOVS     r0,#0                 ;1062
000066  bd70              POP      {r4-r6,pc}
;;;1065   
                          ENDP

                  |L21.104|
                          DCD      0x01e84800
                  |L21.108|
                          DCD      0xffff9606
                  |L21.112|
                          DCD      0x50000200
                  |L21.116|
                          DCD      0x00002710

                          AREA ||i.DrvSYS_OpenExt||, CODE, READONLY, ALIGN=2

                  DrvSYS_OpenExt PROC
;;;1120   /*---------------------------------------------------------------------------------------------------------*/
;;;1121   int32_t DrvSYS_OpenExt(S_SYS_CHIP_CLKCFG *sChipCfg, S_SYS_IP_CLKCFG *sIPCfg)
000000  b5f8              PUSH     {r3-r7,lr}
;;;1122   {
;;;1123   	uint32_t u32ClkEn, u32ClkStb, u32PllCtl;	
;;;1124   	volatile uint32_t delayCnt;
;;;1125   	uint32_t lock_sts = 0;
;;;1126   	
;;;1127   	assert_param(CHECK_CLK_CONFIG(sChipCfg));                      /* Check input parameter */
;;;1128   	assert_param(CHECK_HCLK_SOURCE(sChipCfg->eHClkSrc));  /* Check HCLK clock select */
;;;1129   
;;;1130   	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4a4d              LDR      r2,|L22.312|
000004  4605              MOV      r5,r0                 ;1122
000006  6810              LDR      r0,[r2,#0]
000008  460c              MOV      r4,r1                 ;1122
00000a  07c0              LSLS     r0,r0,#31
00000c  17c6              ASRS     r6,r0,#31
;;;1131   
;;;1132   	/* enable chip clock source */
;;;1133   	u32ClkEn = u32ClkStb = (sChipCfg->u8ClkEnable) & 0x0F;
00000e  7828              LDRB     r0,[r5,#0]
000010  1c76              ADDS     r6,r6,#1              ;1130
000012  0700              LSLS     r0,r0,#28
000014  0f00              LSRS     r0,r0,#28
000016  4601              MOV      r1,r0
;;;1134   
;;;1135   	if (u32ClkEn & E_SYS_HIRC) 
000018  0743              LSLS     r3,r0,#29
00001a  d503              BPL      |L22.36|
;;;1136   		u32ClkStb = (u32ClkStb & ~E_SYS_HIRC) | 0x10;
00001c  2304              MOVS     r3,#4
00001e  4399              BICS     r1,r1,r3
000020  2310              MOVS     r3,#0x10
000022  4319              ORRS     r1,r1,r3
                  |L22.36|
;;;1137   	
;;;1138   	/* Set clock enabke bits and waits for clock stable*/	
;;;1139   	if (lock_sts)	UNLOCKREG();
000024  2e00              CMP      r6,#0
000026  d001              BEQ      |L22.44|
000028  2359              MOVS     r3,#0x59
00002a  6013              STR      r3,[r2,#0]
                  |L22.44|
00002c  4a42              LDR      r2,|L22.312|
00002e  2316              MOVS     r3,#0x16
000030  6013              STR      r3,[r2,#0]
000032  2388              MOVS     r3,#0x88
000034  6013              STR      r3,[r2,#0]
;;;1140   	CLK->PWRCTL = (CLK->PWRCTL & 0xFFFFFFF0) | u32ClkEn;
000036  4f41              LDR      r7,|L22.316|
000038  683a              LDR      r2,[r7,#0]
00003a  0912              LSRS     r2,r2,#4
00003c  0112              LSLS     r2,r2,#4
00003e  4302              ORRS     r2,r2,r0
000040  603a              STR      r2,[r7,#0]
;;;1141   	if (lock_sts)	LOCKREG();
000042  2e00              CMP      r6,#0
000044  d002              BEQ      |L22.76|
000046  4a3c              LDR      r2,|L22.312|
000048  2000              MOVS     r0,#0
00004a  6010              STR      r0,[r2,#0]
                  |L22.76|
;;;1142   	
;;;1143   	for (delayCnt=0; delayCnt<100000; delayCnt++)
00004c  2000              MOVS     r0,#0
                  |L22.78|
;;;1144   		if ((CLK->CLKSTATUS & u32ClkStb) == u32ClkStb)
00004e  68fa              LDR      r2,[r7,#0xc]
000050  460b              MOV      r3,r1
000052  4393              BICS     r3,r3,r2
000054  d003              BEQ      |L22.94|
000056  4a3a              LDR      r2,|L22.320|
000058  1c40              ADDS     r0,r0,#1              ;1143
00005a  4290              CMP      r0,r2                 ;1143
00005c  d3f7              BCC      |L22.78|
                  |L22.94|
;;;1145   			break;
;;;1146   
;;;1147   	if (delayCnt == 100000)
00005e  4938              LDR      r1,|L22.320|
;;;1148   		return E_DRVSYS_ERR_CLK_UNSTABLE;
000060  4b38              LDR      r3,|L22.324|
000062  4288              CMP      r0,r1                 ;1147
000064  d020              BEQ      |L22.168|
;;;1149   
;;;1150   	/* enable PLL */
;;;1151   	if (sChipCfg->u8ClkEnable & E_SYS_PLL)  {
000066  7828              LDRB     r0,[r5,#0]
000068  06c0              LSLS     r0,r0,#27
00006a  d51f              BPL      |L22.172|
;;;1152   
;;;1153   		/* check PLL in clock freq. */
;;;1154   		assert_param(CHECK_PLLIN_CLK(sChipCfg->ePLLInFreq));
;;;1155   		assert_param(CHECK_PLLOUT_CLK(sChipCfg->ePLLOutFreq));
;;;1156   		
;;;1157   		u32PllCtl = _DrvSYS_PLL_Table[sChipCfg->ePLLInFreq][sChipCfg->ePLLOutFreq];
00006c  2004              MOVS     r0,#4
00006e  5628              LDRSB    r0,[r5,r0]
000070  220c              MOVS     r2,#0xc
000072  4350              MULS     r0,r2,r0
000074  4a34              LDR      r2,|L22.328|
000076  1880              ADDS     r0,r0,r2
000078  2205              MOVS     r2,#5
00007a  56aa              LDRSB    r2,[r5,r2]
00007c  0052              LSLS     r2,r2,#1
00007e  5a80              LDRH     r0,[r0,r2]
;;;1158   
;;;1159   		/* check pll clocl set */
;;;1160   		if (u32PllCtl == 0xFFFF)
000080  0c1a              LSRS     r2,r3,#16
000082  4290              CMP      r0,r2
000084  d101              BNE      |L22.138|
;;;1161   			return E_DRVSYS_ERR_PLL_CLK_SET;
000086  1cd8              ADDS     r0,r3,#3
;;;1162   
;;;1163   		/* select correct pll clock source */
;;;1164   		if (sChipCfg->ePLLClkSrc == E_SYS_INTERNAL_HIRC)
;;;1165   			u32PllCtl |= 0x20000;
;;;1166   
;;;1167   		/* set PLL control reg and waits for PLL clock stable */
;;;1168   		CLK->PLLCTL = u32PllCtl;
;;;1169   
;;;1170   		for (delayCnt=0; delayCnt<100000; delayCnt++)
;;;1171   			if (CLK->CLKSTATUS & 0x04)
;;;1172   				break;
;;;1173   
;;;1174   		if (delayCnt == 100000)
;;;1175   			return E_DRVSYS_ERR_CLK_UNSTABLE;		
;;;1176   	}
;;;1177   
;;;1178   	/* set HCLK divider and source */
;;;1179   	DrvSYS_SelectHCLKSource(E_SYS_SEL0_HCLK_HIRC); /* select HIRC for HCLK temporarily */	
;;;1180   	CLK->CLKDIV0_BITS.HCLK_N = sChipCfg->u8HClkDiv;
;;;1181   	DrvSYS_SelectHCLKSource(sChipCfg->eHClkSrc); /* select required clock source for HCLk */
;;;1182   
;;;1183   	if (sIPCfg != NULL)  {
;;;1184   		/* Enable AHB IP clock */
;;;1185   		CLK->AHBCLK = sIPCfg->u32AHBClkEn | 0x30; /* always turn on SRAM and systetick */
;;;1186   
;;;1187   		/* Enable APB IP clock */
;;;1188   		if (sIPCfg->u32APBClkEn & E_SYS_PEN_WDT)  {
;;;1189   			if (lock_sts)	UNLOCKREG();
;;;1190   			CLK->APBCLK = sIPCfg->u32APBClkEn;
;;;1191   			if (lock_sts)	LOCKREG();
;;;1192   		}
;;;1193   		else
;;;1194   			CLK->APBCLK = sIPCfg->u32APBClkEn;
;;;1195   
;;;1196   		/* Set clock divider 0 */
;;;1197   		CLK->CLKDIV0 |= ((sIPCfg->sClkDiv.u8USBDiv << 4) |
;;;1198    						  (sIPCfg->sClkDiv.u8UARTDiv << 8) |
;;;1199    						  (sIPCfg->sClkDiv.u8I2SDiv << 12) |
;;;1200    						  (sIPCfg->sClkDiv.u8ADCDiv << 16) |
;;;1201    						  (sIPCfg->sClkDiv.u8TKDiv << 24) |
;;;1202    						  (sIPCfg->sClkDiv.u8SC0Div << 28)) ;
;;;1203   
;;;1204   		CLK->CLKDIV1 = sIPCfg->sClkDiv.u8SC1Div;
;;;1205   
;;;1206   		/* select clock source */
;;;1207   		CLK->CLKSEL1 = sIPCfg->u32ClkSel1;
;;;1208   		CLK->CLKSEL2 = sIPCfg->u32ClkSel2;
;;;1209   
;;;1210   	}
;;;1211   
;;;1212   	return E_SUCCESS;
;;;1213   
;;;1214   }
000088  bdf8              POP      {r3-r7,pc}
                  |L22.138|
00008a  78ea              LDRB     r2,[r5,#3]            ;1164
00008c  2a01              CMP      r2,#1                 ;1164
00008e  d101              BNE      |L22.148|
000090  0452              LSLS     r2,r2,#17             ;1165
000092  4310              ORRS     r0,r0,r2              ;1165
                  |L22.148|
000094  6278              STR      r0,[r7,#0x24]         ;1168
000096  2000              MOVS     r0,#0                 ;1170
                  |L22.152|
000098  68fa              LDR      r2,[r7,#0xc]          ;1171
00009a  0752              LSLS     r2,r2,#29             ;1171
00009c  d402              BMI      |L22.164|
00009e  1c40              ADDS     r0,r0,#1              ;1170
0000a0  4288              CMP      r0,r1                 ;1170
0000a2  d3f9              BCC      |L22.152|
                  |L22.164|
0000a4  4288              CMP      r0,r1                 ;1174
0000a6  d101              BNE      |L22.172|
                  |L22.168|
0000a8  4618              MOV      r0,r3                 ;1175
0000aa  bdf8              POP      {r3-r7,pc}
                  |L22.172|
0000ac  2007              MOVS     r0,#7                 ;1179
0000ae  f7fffffe          BL       DrvSYS_SelectHCLKSource
0000b2  69f8              LDR      r0,[r7,#0x1c]         ;1180
0000b4  78a9              LDRB     r1,[r5,#2]            ;1180
0000b6  0900              LSRS     r0,r0,#4              ;1180
0000b8  0100              LSLS     r0,r0,#4              ;1180
0000ba  0709              LSLS     r1,r1,#28             ;1180
0000bc  0f09              LSRS     r1,r1,#28             ;1180
0000be  4308              ORRS     r0,r0,r1              ;1180
0000c0  61f8              STR      r0,[r7,#0x1c]         ;1180
0000c2  7868              LDRB     r0,[r5,#1]            ;1181
0000c4  f7fffffe          BL       DrvSYS_SelectHCLKSource
0000c8  2c00              CMP      r4,#0                 ;1183
0000ca  d032              BEQ      |L22.306|
0000cc  6820              LDR      r0,[r4,#0]            ;1185
0000ce  2130              MOVS     r1,#0x30              ;1185
0000d0  4308              ORRS     r0,r0,r1              ;1185
0000d2  6078              STR      r0,[r7,#4]            ;1185
0000d4  6860              LDR      r0,[r4,#4]            ;1188
0000d6  07c1              LSLS     r1,r0,#31             ;1188
0000d8  d010              BEQ      |L22.252|
0000da  2e00              CMP      r6,#0                 ;1189
0000dc  d002              BEQ      |L22.228|
0000de  4916              LDR      r1,|L22.312|
0000e0  2059              MOVS     r0,#0x59              ;1189
0000e2  6008              STR      r0,[r1,#0]            ;1189
                  |L22.228|
0000e4  4814              LDR      r0,|L22.312|
0000e6  2116              MOVS     r1,#0x16              ;1189
0000e8  6001              STR      r1,[r0,#0]            ;1189
0000ea  2188              MOVS     r1,#0x88              ;1189
0000ec  6001              STR      r1,[r0,#0]            ;1189
0000ee  6861              LDR      r1,[r4,#4]            ;1190
0000f0  60b9              STR      r1,[r7,#8]            ;1190
0000f2  2e00              CMP      r6,#0                 ;1191
0000f4  d003              BEQ      |L22.254|
0000f6  2100              MOVS     r1,#0                 ;1191
0000f8  6001              STR      r1,[r0,#0]            ;1191
0000fa  e000              B        |L22.254|
                  |L22.252|
0000fc  60b8              STR      r0,[r7,#8]            ;1194
                  |L22.254|
0000fe  7c20              LDRB     r0,[r4,#0x10]         ;1197
000100  7c61              LDRB     r1,[r4,#0x11]         ;1197
000102  0100              LSLS     r0,r0,#4              ;1197
000104  0209              LSLS     r1,r1,#8              ;1197
000106  4308              ORRS     r0,r0,r1              ;1197
000108  7ca1              LDRB     r1,[r4,#0x12]         ;1197
00010a  0309              LSLS     r1,r1,#12             ;1197
00010c  4308              ORRS     r0,r0,r1              ;1197
00010e  7ce1              LDRB     r1,[r4,#0x13]         ;1197
000110  0409              LSLS     r1,r1,#16             ;1197
000112  4308              ORRS     r0,r0,r1              ;1197
000114  7d21              LDRB     r1,[r4,#0x14]         ;1197
000116  0609              LSLS     r1,r1,#24             ;1197
000118  4308              ORRS     r0,r0,r1              ;1197
00011a  7d61              LDRB     r1,[r4,#0x15]         ;1197
00011c  0709              LSLS     r1,r1,#28             ;1197
00011e  4308              ORRS     r0,r0,r1              ;1197
000120  69f9              LDR      r1,[r7,#0x1c]         ;1197
000122  4308              ORRS     r0,r0,r1              ;1197
000124  61f8              STR      r0,[r7,#0x1c]         ;1197
000126  7da0              LDRB     r0,[r4,#0x16]         ;1204
000128  6238              STR      r0,[r7,#0x20]         ;1204
00012a  68a0              LDR      r0,[r4,#8]            ;1207
00012c  6178              STR      r0,[r7,#0x14]         ;1207
00012e  68e0              LDR      r0,[r4,#0xc]          ;1208
000130  61b8              STR      r0,[r7,#0x18]         ;1208
                  |L22.306|
000132  2000              MOVS     r0,#0                 ;1212
000134  bdf8              POP      {r3-r7,pc}
;;;1215   
                          ENDP

000136  0000              DCW      0x0000
                  |L22.312|
                          DCD      0x50000100
                  |L22.316|
                          DCD      0x50000200
                  |L22.320|
                          DCD      0x000186a0
                  |L22.324|
                          DCD      0xffff9607
                  |L22.328|
                          DCD      ||.data||+0x10

                          AREA ||i.DrvSYS_ReadProductID||, CODE, READONLY, ALIGN=1

                  DrvSYS_ReadProductID PROC
;;;89     /*---------------------------------------------------------------------------------------------------------*/
;;;90     uint32_t DrvSYS_ReadProductID(void)
000000  2005              MOVS     r0,#5
;;;91     {	
;;;92     	return GCR->PDID;
000002  0700              LSLS     r0,r0,#28
000004  6800              LDR      r0,[r0,#0]
;;;93     }
000006  4770              BX       lr
;;;94     
                          ENDP


                          AREA ||i.DrvSYS_ResetCPU||, CODE, READONLY, ALIGN=2

                  DrvSYS_ResetCPU PROC
;;;248    /*---------------------------------------------------------------------------------------------------------*/
;;;249    void DrvSYS_ResetCPU(void)
000000  b510              PUSH     {r4,lr}
;;;250    {
;;;251    	uint32_t lock_sts = 0;
;;;252    
;;;253    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  490b              LDR      r1,|L24.48|
000004  6808              LDR      r0,[r1,#0]
000006  07c0              LSLS     r0,r0,#31
000008  17c0              ASRS     r0,r0,#31
00000a  1c40              ADDS     r0,r0,#1
;;;254    	
;;;255    	if (lock_sts) 	UNLOCKREG();
00000c  d001              BEQ      |L24.18|
00000e  2259              MOVS     r2,#0x59
000010  600a              STR      r2,[r1,#0]
                  |L24.18|
000012  2216              MOVS     r2,#0x16
000014  600a              STR      r2,[r1,#0]
000016  2288              MOVS     r2,#0x88
000018  600a              STR      r2,[r1,#0]
;;;256    	GCR->IPRST_CTL1_BITS.CPU_RST = 1;
00001a  2305              MOVS     r3,#5
00001c  071b              LSLS     r3,r3,#28
00001e  689a              LDR      r2,[r3,#8]
000020  2402              MOVS     r4,#2
000022  4322              ORRS     r2,r2,r4
000024  609a              STR      r2,[r3,#8]
;;;257        if (lock_sts)	LOCKREG();
000026  2800              CMP      r0,#0
000028  d001              BEQ      |L24.46|
00002a  2000              MOVS     r0,#0
00002c  6008              STR      r0,[r1,#0]
                  |L24.46|
;;;258    }
00002e  bd10              POP      {r4,pc}
;;;259    
                          ENDP

                  |L24.48|
                          DCD      0x50000100

                          AREA ||i.DrvSYS_ResetChip||, CODE, READONLY, ALIGN=2

                  DrvSYS_ResetChip PROC
;;;271    /*---------------------------------------------------------------------------------------------------------*/
;;;272    void DrvSYS_ResetChip(void)
000000  b510              PUSH     {r4,lr}
;;;273    {
;;;274    	uint32_t lock_sts = 0;
;;;275    
;;;276    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  490b              LDR      r1,|L25.48|
000004  6808              LDR      r0,[r1,#0]
000006  07c0              LSLS     r0,r0,#31
000008  17c0              ASRS     r0,r0,#31
00000a  1c40              ADDS     r0,r0,#1
;;;277    	
;;;278    	if (lock_sts) 	UNLOCKREG();
00000c  d001              BEQ      |L25.18|
00000e  2259              MOVS     r2,#0x59
000010  600a              STR      r2,[r1,#0]
                  |L25.18|
000012  2216              MOVS     r2,#0x16
000014  600a              STR      r2,[r1,#0]
000016  2288              MOVS     r2,#0x88
000018  600a              STR      r2,[r1,#0]
;;;279    	GCR->IPRST_CTL1_BITS.CHIP_RST = 1;
00001a  2305              MOVS     r3,#5
00001c  071b              LSLS     r3,r3,#28
00001e  689a              LDR      r2,[r3,#8]
000020  2401              MOVS     r4,#1
000022  4322              ORRS     r2,r2,r4
000024  609a              STR      r2,[r3,#8]
;;;280    	if (lock_sts) 	LOCKREG();
000026  2800              CMP      r0,#0
000028  d001              BEQ      |L25.46|
00002a  2000              MOVS     r0,#0
00002c  6008              STR      r0,[r1,#0]
                  |L25.46|
;;;281    }
00002e  bd10              POP      {r4,pc}
;;;282    
                          ENDP

                  |L25.48|
                          DCD      0x50000100

                          AREA ||i.DrvSYS_ResetIP||, CODE, READONLY, ALIGN=2

                  DrvSYS_ResetIP PROC
;;;209    /*---------------------------------------------------------------------------------------------------------*/
;;;210    void DrvSYS_ResetIP(E_SYS_IP_RST eIpRst)
000000  b5f0              PUSH     {r4-r7,lr}
;;;211    {	
;;;212    	uint32_t lock_sts = 0;
;;;213    
;;;214    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4a18              LDR      r2,|L26.100|
000004  6811              LDR      r1,[r2,#0]
;;;215    
;;;216    	if (eIpRst == E_SYS_PDMA_RST)
;;;217    	{
;;;218    		if (lock_sts)	UNLOCKREG();
;;;219    		GCR->IPRST_CTL1_BITS.PDMA_RST = 1;
000006  2305              MOVS     r3,#5
000008  07c9              LSLS     r1,r1,#31             ;214
00000a  17c9              ASRS     r1,r1,#31             ;214
00000c  1c49              ADDS     r1,r1,#1              ;214
00000e  2400              MOVS     r4,#0                 ;212
000010  2759              MOVS     r7,#0x59              ;218
000012  2616              MOVS     r6,#0x16              ;218
000014  2588              MOVS     r5,#0x88              ;218
000016  071b              LSLS     r3,r3,#28
000018  2820              CMP      r0,#0x20              ;216
00001a  d00a              BEQ      |L26.50|
;;;220    		GCR->IPRST_CTL1_BITS.PDMA_RST = 0;
;;;221    		if (lock_sts)	LOCKREG();
;;;222    	}
;;;223    	else if (eIpRst == E_SYS_EBI_RST)
00001c  2821              CMP      r0,#0x21
00001e  d012              BEQ      |L26.70|
;;;224    	{
;;;225    		if (lock_sts)	UNLOCKREG();
;;;226    		GCR->IPRST_CTL1_BITS.EBI_RST = 1;
;;;227    		GCR->IPRST_CTL1_BITS.EBI_RST = 0;
;;;228    		if (lock_sts)	LOCKREG();
;;;229    	}
;;;230    	else
;;;231    	{
;;;232    		GCR->IPRST_CTL2 |= (1<<eIpRst);
000020  68da              LDR      r2,[r3,#0xc]
000022  2101              MOVS     r1,#1
000024  4081              LSLS     r1,r1,r0
000026  430a              ORRS     r2,r2,r1
000028  60da              STR      r2,[r3,#0xc]
;;;233    		GCR->IPRST_CTL2 &= ~(1<<eIpRst);
00002a  68d8              LDR      r0,[r3,#0xc]
00002c  4388              BICS     r0,r0,r1
00002e  60d8              STR      r0,[r3,#0xc]
;;;234    	}
;;;235    }
000030  bdf0              POP      {r4-r7,pc}
                  |L26.50|
000032  2900              CMP      r1,#0                 ;218
000034  d000              BEQ      |L26.56|
000036  6017              STR      r7,[r2,#0]            ;218
                  |L26.56|
000038  6016              STR      r6,[r2,#0]            ;218
00003a  6015              STR      r5,[r2,#0]            ;218
00003c  689d              LDR      r5,[r3,#8]            ;219
00003e  2004              MOVS     r0,#4                 ;219
000040  e008              B        |L26.84|
                  |L26.66|
000042  6014              STR      r4,[r2,#0]            ;221
000044  bdf0              POP      {r4-r7,pc}
                  |L26.70|
000046  2900              CMP      r1,#0                 ;225
000048  d000              BEQ      |L26.76|
00004a  6017              STR      r7,[r2,#0]            ;225
                  |L26.76|
00004c  6016              STR      r6,[r2,#0]            ;225
00004e  6015              STR      r5,[r2,#0]            ;225
000050  689d              LDR      r5,[r3,#8]            ;226
000052  2008              MOVS     r0,#8                 ;226
                  |L26.84|
000054  4305              ORRS     r5,r5,r0              ;219
000056  609d              STR      r5,[r3,#8]            ;219
000058  689d              LDR      r5,[r3,#8]            ;220
00005a  4385              BICS     r5,r5,r0              ;220
00005c  609d              STR      r5,[r3,#8]            ;220
00005e  2900              CMP      r1,#0                 ;221
000060  d1ef              BNE      |L26.66|
000062  bdf0              POP      {r4-r7,pc}
;;;236    
                          ENDP

                  |L26.100|
                          DCD      0x50000100

                          AREA ||i.DrvSYS_SelectBODVolt||, CODE, READONLY, ALIGN=2

                  DrvSYS_SelectBODVolt PROC
;;;295    /*---------------------------------------------------------------------------------------------------------*/
;;;296    void DrvSYS_SelectBODVolt(uint8_t u8Volt)
000000  b530              PUSH     {r4,r5,lr}
;;;297    {
;;;298        uint32_t lock_sts = 0;
;;;299    	assert_param(CHECK_BOD_VOLT(u8Volt));
;;;300    
;;;301    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4a0c              LDR      r2,|L27.52|
000004  6811              LDR      r1,[r2,#0]
000006  07c9              LSLS     r1,r1,#31
000008  17c9              ASRS     r1,r1,#31
00000a  1c49              ADDS     r1,r1,#1
;;;302    
;;;303    	if (lock_sts)	UNLOCKREG();
00000c  d001              BEQ      |L27.18|
00000e  2359              MOVS     r3,#0x59
000010  6013              STR      r3,[r2,#0]
                  |L27.18|
000012  2316              MOVS     r3,#0x16
000014  6013              STR      r3,[r2,#0]
000016  2388              MOVS     r3,#0x88
000018  6013              STR      r3,[r2,#0]
;;;304    	GCR->BODCTL |= (1 << u8Volt);
00001a  4d06              LDR      r5,|L27.52|
00001c  3dc0              SUBS     r5,r5,#0xc0
00001e  6a6b              LDR      r3,[r5,#0x24]
000020  2401              MOVS     r4,#1
000022  4084              LSLS     r4,r4,r0
000024  4323              ORRS     r3,r3,r4
000026  626b              STR      r3,[r5,#0x24]
;;;305        if (lock_sts)	LOCKREG();
000028  2900              CMP      r1,#0
00002a  d001              BEQ      |L27.48|
00002c  2000              MOVS     r0,#0
00002e  6010              STR      r0,[r2,#0]
                  |L27.48|
;;;306    }
000030  bd30              POP      {r4,r5,pc}
;;;307    
                          ENDP

000032  0000              DCW      0x0000
                  |L27.52|
                          DCD      0x50000100

                          AREA ||i.DrvSYS_SelectHCLKSource||, CODE, READONLY, ALIGN=2

                  DrvSYS_SelectHCLKSource PROC
;;;516    /*---------------------------------------------------------------------------------------------------------*/
;;;517    int32_t DrvSYS_SelectHCLKSource(uint8_t u8ClkSrcSel)
000000  b510              PUSH     {r4,lr}
;;;518    {
;;;519    	uint32_t lock_sts = 0;
;;;520    
;;;521    	assert_param(CHECK_HCLK_SOURCE(u8ClkSrcSel));
;;;522    
;;;523    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4a0f              LDR      r2,|L28.64|
000004  6811              LDR      r1,[r2,#0]
000006  07c9              LSLS     r1,r1,#31
000008  17c9              ASRS     r1,r1,#31
00000a  1c49              ADDS     r1,r1,#1
;;;524    
;;;525    	if (lock_sts)	UNLOCKREG();
00000c  d001              BEQ      |L28.18|
00000e  2359              MOVS     r3,#0x59
000010  6013              STR      r3,[r2,#0]
                  |L28.18|
000012  2316              MOVS     r3,#0x16
000014  6013              STR      r3,[r2,#0]
000016  2388              MOVS     r3,#0x88
000018  6013              STR      r3,[r2,#0]
;;;526    	CLK->CLKSEL0 = u8ClkSrcSel;
00001a  4b0a              LDR      r3,|L28.68|
00001c  6118              STR      r0,[r3,#0x10]
;;;527    	if (lock_sts)	LOCKREG();
00001e  2900              CMP      r1,#0
000020  d001              BEQ      |L28.38|
000022  2000              MOVS     r0,#0
000024  6010              STR      r0,[r2,#0]
                  |L28.38|
;;;528    
;;;529    	if (CLK->CLKSTATUS_BITS.CLK_SW_FAIL)  {
000026  68d8              LDR      r0,[r3,#0xc]
000028  0600              LSLS     r0,r0,#24
00002a  d505              BPL      |L28.56|
;;;530    		CLK->CLKSTATUS_BITS.CLK_SW_FAIL = 1;  /* Clear Clock Switch Fail Flag */
00002c  68d8              LDR      r0,[r3,#0xc]
00002e  2180              MOVS     r1,#0x80
000030  4308              ORRS     r0,r0,r1
000032  60d8              STR      r0,[r3,#0xc]
;;;531              	return E_DRVSYS_ERR_CLKSWITCH_FAIL;
000034  4804              LDR      r0,|L28.72|
;;;532        	}
;;;533    		
;;;534    	SystemCoreClockUpdate();
;;;535    	
;;;536    	return 0;
;;;537    }
000036  bd10              POP      {r4,pc}
                  |L28.56|
000038  f7fffffe          BL       SystemCoreClockUpdate
00003c  2000              MOVS     r0,#0                 ;536
00003e  bd10              POP      {r4,pc}
;;;538    
                          ENDP

                  |L28.64|
                          DCD      0x50000100
                  |L28.68|
                          DCD      0x50000200
                  |L28.72|
                          DCD      0xffff960c

                          AREA ||i.DrvSYS_SelectIPClockSource||, CODE, READONLY, ALIGN=2

                  DrvSYS_SelectIPClockSource PROC
;;;578    /*---------------------------------------------------------------------------------------------------------*/
;;;579    int32_t DrvSYS_SelectIPClockSource(uint32_t u32IpClkSrc, uint8_t u8ClkSrcSel)
000000  0a03              LSRS     r3,r0,#8
;;;580    {
;;;581    	uint32_t u32Mask, u32BitPos, u32RegNum;
;;;582    	 
;;;583           assert_param(CHECK_IP_CLKSRC(u32IpClkSrc));
;;;584    
;;;585    	u32BitPos = (u32IpClkSrc & 0x0000FF00) >> 8;
;;;586    	u32Mask  = (u32IpClkSrc & 0x000000FF)  << u32BitPos;
000002  b2c2              UXTB     r2,r0
000004  409a              LSLS     r2,r2,r3
000006  b510              PUSH     {r4,lr}               ;580
;;;587           u32RegNum = (u32IpClkSrc & 0x00FF0000) >> 16;
000008  0203              LSLS     r3,r0,#8
00000a  0e1b              LSRS     r3,r3,#24
;;;588    
;;;589           if (u32RegNum == 1)
;;;590    	 	CLK->CLKSEL1 = (CLK->CLKSEL1 & (~u32Mask)) | (u8ClkSrcSel << u32BitPos);
00000c  4c07              LDR      r4,|L29.44|
00000e  0a00              LSRS     r0,r0,#8              ;585
000010  4081              LSLS     r1,r1,r0
;;;591           else
;;;592    	 	CLK->CLKSEL2 = (CLK->CLKSEL1 & (~u32Mask)) | (u8ClkSrcSel << u32BitPos);
000012  6960              LDR      r0,[r4,#0x14]
000014  2b01              CMP      r3,#1                 ;589
000016  d004              BEQ      |L29.34|
000018  4390              BICS     r0,r0,r2
00001a  4308              ORRS     r0,r0,r1
00001c  61a0              STR      r0,[r4,#0x18]
                  |L29.30|
;;;593    
;;;594    	return E_SUCCESS;
00001e  2000              MOVS     r0,#0
;;;595    }
000020  bd10              POP      {r4,pc}
                  |L29.34|
000022  4390              BICS     r0,r0,r2              ;590
000024  4308              ORRS     r0,r0,r1              ;590
000026  6160              STR      r0,[r4,#0x14]         ;590
000028  e7f9              B        |L29.30|
;;;596    
                          ENDP

00002a  0000              DCW      0x0000
                  |L29.44|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_SelectPLLSource||, CODE, READONLY, ALIGN=2

                  DrvSYS_SelectPLLSource PROC
;;;772    /*---------------------------------------------------------------------------------------------------------*/
;;;773    void DrvSYS_SelectPLLSource(E_SYS_PLL_CLKSRC ePllSrc)
000000  4a04              LDR      r2,|L30.20|
;;;774    {
;;;775    	CLK->PLLCTL_BITS.PLL_SRC = ePllSrc;
000002  6a51              LDR      r1,[r2,#0x24]
000004  0213              LSLS     r3,r2,#8
000006  07c0              LSLS     r0,r0,#31
000008  4399              BICS     r1,r1,r3
00000a  0b80              LSRS     r0,r0,#14
00000c  4301              ORRS     r1,r1,r0
00000e  6251              STR      r1,[r2,#0x24]
;;;776    }
000010  4770              BX       lr
;;;777    
                          ENDP

000012  0000              DCW      0x0000
                  |L30.20|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_SetBODFunction||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetBODFunction PROC
;;;324    /*---------------------------------------------------------------------------------------------------------*/
;;;325    void DrvSYS_SetBODFunction(int32_t i32Enalbe, int32_t i32Mode, BOD_CALLBACK bodcallbackFn, int32_t i32Volt)
000000  b5ff              PUSH     {r0-r7,lr}
;;;326    {
;;;327    	uint32_t u32MaskBits, u32SetBits;
;;;328    	uint32_t lock_sts = 0;
;;;329    	
;;;330    	assert_param(CHECK_BOD_ENABLE(i32Enalbe));
;;;331    	assert_param(CHECK_BOD_MODE(i32Mode));
;;;332    	assert_param(CHECK_BOD_VOLT(i32Volt));
;;;333    
;;;334    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4e1f              LDR      r6,|L31.128|
000004  4684              MOV      r12,r0                ;326
000006  6830              LDR      r0,[r6,#0]
;;;335    
;;;336    	u32MaskBits = ((1 << (i32Volt + 8)) | 	/* BOD INT control bit */
000008  2501              MOVS     r5,#1
00000a  07c0              LSLS     r0,r0,#31             ;334
00000c  17c2              ASRS     r2,r0,#31             ;334
00000e  1c52              ADDS     r2,r2,#1              ;334
000010  4618              MOV      r0,r3
000012  3008              ADDS     r0,r0,#8
000014  462c              MOV      r4,r5
000016  4084              LSLS     r4,r4,r0
000018  46a6              MOV      lr,r4
00001a  1d18              ADDS     r0,r3,#4
00001c  462f              MOV      r7,r5
00001e  4087              LSLS     r7,r7,r0
000020  462c              MOV      r4,r5
000022  409c              LSLS     r4,r4,r3
000024  4670              MOV      r0,lr
000026  4b17              LDR      r3,|L31.132|
000028  4338              ORRS     r0,r0,r7
00002a  4320              ORRS     r0,r0,r4
00002c  601d              STR      r5,[r3,#0]
;;;337    				   (1 << (i32Volt + 4)) |	/* BOD Reset control bit */
;;;338    				   (1 << (i32Volt)));		/* BOD enable bit */
;;;339    
;;;340    	NVIC_DisableIRQ(BOD_IRQn);
;;;341    	
;;;342    	if (i32Enalbe == 1)  {  /* Enable BOD function */
00002e  4663              MOV      r3,r12
000030  2b01              CMP      r3,#1
000032  d01b              BEQ      |L31.108|
;;;343    		if (i32Mode == 1)  {  
;;;344    			u32SetBits = ((1 << (i32Volt + 4)) | (1 << (i32Volt)));		/* BOD Reset and Enable bit */
;;;345    		}
;;;346    		else  {
;;;347    			u32SetBits = ((1 << (i32Volt + 8)) |  (1 << (i32Volt)));	      /* BOD Interrupt and Enable bit */
;;;348    			BOD_callbackFn = bodcallbackFn;
;;;349    		}
;;;350    	}
;;;351    	else
;;;352    		u32SetBits = 0;     /* Disable BOD function */
000034  2700              MOVS     r7,#0
                  |L31.54|
;;;353    		
;;;354    	if (lock_sts)	UNLOCKREG();
000036  2a00              CMP      r2,#0
000038  d001              BEQ      |L31.62|
00003a  2359              MOVS     r3,#0x59
00003c  6033              STR      r3,[r6,#0]
                  |L31.62|
00003e  2316              MOVS     r3,#0x16
000040  6033              STR      r3,[r6,#0]
000042  2388              MOVS     r3,#0x88
000044  6033              STR      r3,[r6,#0]
;;;355    	GCR->BODCTL = ((GCR->BODCTL & (~u32MaskBits)) | u32SetBits);
000046  4c0e              LDR      r4,|L31.128|
000048  3cc0              SUBS     r4,r4,#0xc0
00004a  6a63              LDR      r3,[r4,#0x24]
00004c  4383              BICS     r3,r3,r0
00004e  433b              ORRS     r3,r3,r7
000050  6263              STR      r3,[r4,#0x24]
;;;356    	if (lock_sts)	LOCKREG();
000052  2a00              CMP      r2,#0
000054  d001              BEQ      |L31.90|
000056  2000              MOVS     r0,#0
000058  6030              STR      r0,[r6,#0]
                  |L31.90|
;;;357    		
;;;358    	if (i32Enalbe && (!i32Mode))
00005a  4660              MOV      r0,r12
00005c  2800              CMP      r0,#0
00005e  d004              BEQ      |L31.106|
000060  2900              CMP      r1,#0
000062  d102              BNE      |L31.106|
000064  4907              LDR      r1,|L31.132|
000066  3980              SUBS     r1,r1,#0x80
000068  600d              STR      r5,[r1,#0]
                  |L31.106|
;;;359    		NVIC_EnableIRQ(BOD_IRQn);
;;;360    		
;;;361    }
00006a  bdff              POP      {r0-r7,pc}
                  |L31.108|
00006c  2901              CMP      r1,#1                 ;343
00006e  d005              BEQ      |L31.124|
000070  4677              MOV      r7,lr                 ;343
000072  4327              ORRS     r7,r7,r4              ;347
000074  4c04              LDR      r4,|L31.136|
000076  9b02              LDR      r3,[sp,#8]            ;348
000078  6023              STR      r3,[r4,#0]            ;348  ; BOD_callbackFn
00007a  e7dc              B        |L31.54|
                  |L31.124|
00007c  4327              ORRS     r7,r7,r4              ;344
00007e  e7da              B        |L31.54|
;;;362    
                          ENDP

                  |L31.128|
                          DCD      0x50000100
                  |L31.132|
                          DCD      0xe000e180
                  |L31.136|
                          DCD      ||.data||

                          AREA ||i.DrvSYS_SetClockDivider||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetClockDivider PROC
;;;611    /*---------------------------------------------------------------------------------------------------------*/
;;;612    int32_t DrvSYS_SetClockDivider(uint32_t u32IpDiv , int32_t i32value)
000000  b570              PUSH     {r4-r6,lr}
;;;613    {
;;;614    	uint32_t u32Mask, u32BitPos, u32RegNum;
;;;615    	 
;;;616        assert_param(CHECK_IP_CLKDIV(u32IpDiv));
;;;617    
;;;618        u32BitPos = (u32IpDiv & 0x0000FF00) >> 8;
000002  0a03              LSRS     r3,r0,#8
;;;619        u32Mask  = (u32IpDiv & 0x000000FF)  << u32BitPos;
000004  b2c2              UXTB     r2,r0
000006  409a              LSLS     r2,r2,r3
;;;620    	u32RegNum = (u32IpDiv & 0x00FF0000) >> 16;
000008  0203              LSLS     r3,r0,#8
00000a  0e1b              LSRS     r3,r3,#24
00000c  0a05              LSRS     r5,r0,#8              ;618
;;;621    
;;;622    	if (u32RegNum == 0)
;;;623    	    CLK->CLKDIV0 = (CLK->CLKDIV0 & (~u32Mask)) | (i32value << u32BitPos);
00000e  4c09              LDR      r4,|L32.52|
000010  40a9              LSLS     r1,r1,r5
000012  2b00              CMP      r3,#0                 ;622
;;;624    	else
;;;625    		CLK->CLKDIV1 = (CLK->CLKDIV0 & (~u32Mask)) | (i32value << u32BitPos);
000014  69e3              LDR      r3,[r4,#0x1c]
000016  d005              BEQ      |L32.36|
000018  4393              BICS     r3,r3,r2
00001a  430b              ORRS     r3,r3,r1
00001c  6223              STR      r3,[r4,#0x20]
                  |L32.30|
;;;626    
;;;627         	if (u32IpDiv == HCLK_CLK_DIV)
00001e  280f              CMP      r0,#0xf
000020  d004              BEQ      |L32.44|
000022  e005              B        |L32.48|
                  |L32.36|
000024  4393              BICS     r3,r3,r2              ;623
000026  430b              ORRS     r3,r3,r1              ;623
000028  61e3              STR      r3,[r4,#0x1c]         ;623
00002a  e7f8              B        |L32.30|
                  |L32.44|
;;;628    	 	SystemCoreClockUpdate();
00002c  f7fffffe          BL       SystemCoreClockUpdate
                  |L32.48|
;;;629    
;;;630    	return E_SUCCESS;
000030  2000              MOVS     r0,#0
;;;631    }
000032  bd70              POP      {r4-r6,pc}
;;;632    
                          ENDP

                  |L32.52|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_SetFreqDividerOutput||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetFreqDividerOutput PROC
;;;1231   /*---------------------------------------------------------------------------------------------------------*/
;;;1232   int32_t DrvSYS_SetFreqDividerOutput(int32_t i32Flag, uint8_t u8Divider)
000000  460a              MOV      r2,r1
;;;1233   {
000002  b500              PUSH     {lr}
;;;1234   	assert_param(CHECK_FREQ_DIVIDER(u8Divider));
;;;1235   
;;;1236   	if (i32Flag)
;;;1237   	{
;;;1238   		CLK->FRQDIV_BITS.FSEL = u8Divider;
000004  490b              LDR      r1,|L33.52|
000006  2800              CMP      r0,#0                 ;1236
000008  d006              BEQ      |L33.24|
00000a  6a8b              LDR      r3,[r1,#0x28]
00000c  0712              LSLS     r2,r2,#28
00000e  091b              LSRS     r3,r3,#4
000010  011b              LSLS     r3,r3,#4
000012  0f12              LSRS     r2,r2,#28
000014  4313              ORRS     r3,r3,r2
000016  628b              STR      r3,[r1,#0x28]
                  |L33.24|
;;;1239   	}
;;;1240   	CLK->FRQDIV_BITS.FDIV_EN = i32Flag; 		
000018  6a8a              LDR      r2,[r1,#0x28]
00001a  2310              MOVS     r3,#0x10
00001c  439a              BICS     r2,r2,r3
00001e  07c3              LSLS     r3,r0,#31
000020  0edb              LSRS     r3,r3,#27
000022  431a              ORRS     r2,r2,r3
000024  628a              STR      r2,[r1,#0x28]
;;;1241   	DrvSYS_SetIPClock(E_SYS_FDIV_CLK, i32Flag);
000026  4601              MOV      r1,r0
000028  2006              MOVS     r0,#6
00002a  f7fffffe          BL       DrvSYS_SetIPClock
;;;1242   
;;;1243   	return E_SUCCESS;
00002e  2000              MOVS     r0,#0
;;;1244   }
000030  bd00              POP      {pc}
;;;1245   
                          ENDP

000032  0000              DCW      0x0000
                  |L33.52|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_SetIPClock||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetIPClock PROC
;;;469    /*---------------------------------------------------------------------------------------------------------*/
;;;470    void DrvSYS_SetIPClock(E_SYS_IP_CLK eIpClk, int32_t i32Enable)
000000  b510              PUSH     {r4,lr}
;;;471    {	
;;;472    	uint32_t lock_sts = 0;
;;;473    	assert_param(CHECK_IPCLK_SRC(eIpClk));
;;;474    
;;;475    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4c19              LDR      r4,|L34.104|
000004  6822              LDR      r2,[r4,#0]
000006  07d2              LSLS     r2,r2,#31
000008  17d3              ASRS     r3,r2,#31
00000a  1c5b              ADDS     r3,r3,#1
;;;476    
;;;477    
;;;478    	if (eIpClk >= 32)  { /* AHB Clock Source */
;;;479    		if (i32Enable == 1)
;;;480    			CLK->AHBCLK |= (1 << (eIpClk - 32));
00000c  4a17              LDR      r2,|L34.108|
00000e  2820              CMP      r0,#0x20              ;478
000010  d30a              BCC      |L34.40|
000012  3820              SUBS     r0,r0,#0x20
000014  2301              MOVS     r3,#1                 ;471
000016  4083              LSLS     r3,r3,r0
;;;481    		else
;;;482    			CLK->AHBCLK &= ~(1 << (eIpClk - 32));
000018  6850              LDR      r0,[r2,#4]
00001a  2901              CMP      r1,#1                 ;479
00001c  d002              BEQ      |L34.36|
00001e  4398              BICS     r0,r0,r3
                  |L34.32|
000020  6050              STR      r0,[r2,#4]
                  |L34.34|
;;;483    	}
;;;484    	else { /*APB Clock Source */
;;;485    		if (eIpClk == E_SYS_WDT_CLK)  {
;;;486    			if (lock_sts)	UNLOCKREG();
;;;487    			CLK->APBCLK_BITS.WDT_EN = i32Enable;
;;;488    			if (lock_sts)	LOCKREG();
;;;489    		}
;;;490    		else  {
;;;491    			if (i32Enable)
;;;492    				CLK->APBCLK |= (1<<eIpClk);
;;;493    			else
;;;494    				CLK->APBCLK &= ~(1<<eIpClk);
;;;495    		}		
;;;496    	}
;;;497    		
;;;498    }
000022  bd10              POP      {r4,pc}
                  |L34.36|
000024  4318              ORRS     r0,r0,r3              ;480
000026  e7fb              B        |L34.32|
                  |L34.40|
000028  2800              CMP      r0,#0                 ;485
00002a  d006              BEQ      |L34.58|
00002c  2301              MOVS     r3,#1                 ;471
00002e  4083              LSLS     r3,r3,r0              ;492
000030  6890              LDR      r0,[r2,#8]            ;494
000032  2900              CMP      r1,#0                 ;491
000034  d015              BEQ      |L34.98|
000036  4318              ORRS     r0,r0,r3              ;492
000038  e014              B        |L34.100|
                  |L34.58|
00003a  2b00              CMP      r3,#0                 ;486
00003c  d001              BEQ      |L34.66|
00003e  2059              MOVS     r0,#0x59              ;486
000040  6020              STR      r0,[r4,#0]            ;486
                  |L34.66|
000042  2016              MOVS     r0,#0x16              ;486
000044  6020              STR      r0,[r4,#0]            ;486
000046  2088              MOVS     r0,#0x88              ;486
000048  6020              STR      r0,[r4,#0]            ;486
00004a  6890              LDR      r0,[r2,#8]            ;487
00004c  07c9              LSLS     r1,r1,#31             ;487
00004e  0840              LSRS     r0,r0,#1              ;487
000050  0040              LSLS     r0,r0,#1              ;487
000052  0fc9              LSRS     r1,r1,#31             ;487
000054  4308              ORRS     r0,r0,r1              ;487
000056  6090              STR      r0,[r2,#8]            ;487
000058  2b00              CMP      r3,#0                 ;488
00005a  d0e2              BEQ      |L34.34|
00005c  2000              MOVS     r0,#0                 ;488
00005e  6020              STR      r0,[r4,#0]            ;488
000060  bd10              POP      {r4,pc}
                  |L34.98|
000062  4398              BICS     r0,r0,r3              ;494
                  |L34.100|
000064  6090              STR      r0,[r2,#8]            ;494
000066  bd10              POP      {r4,pc}
;;;499    
                          ENDP

                  |L34.104|
                          DCD      0x50000100
                  |L34.108|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_SetOscCtrl||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetOscCtrl PROC
;;;647    /*---------------------------------------------------------------------------------------------------------*/
;;;648    int32_t DrvSYS_SetOscCtrl(E_SYS_CHIP_CLKSRC eClkSrc, int32_t i32Enable)
000000  b530              PUSH     {r4,r5,lr}
;;;649    {	
;;;650    	uint32_t lock_sts = 0;
;;;651    	
;;;652    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4c1b              LDR      r4,|L35.112|
000004  6822              LDR      r2,[r4,#0]
000006  07d2              LSLS     r2,r2,#31
000008  17d2              ASRS     r2,r2,#31
00000a  1c52              ADDS     r2,r2,#1
;;;653    	
;;;654    	if (lock_sts)	UNLOCKREG();
00000c  d001              BEQ      |L35.18|
00000e  2359              MOVS     r3,#0x59
000010  6023              STR      r3,[r4,#0]
                  |L35.18|
000012  2316              MOVS     r3,#0x16
000014  6023              STR      r3,[r4,#0]
000016  2388              MOVS     r3,#0x88
000018  6023              STR      r3,[r4,#0]
;;;655    	switch(eClkSrc)
;;;656    	{
;;;657    		case E_SYS_HXT:  
;;;658    			CLK->PWRCTL_BITS.HXT_EN = i32Enable;
00001a  4b16              LDR      r3,|L35.116|
00001c  2801              CMP      r0,#1                 ;655
00001e  d007              BEQ      |L35.48|
000020  2802              CMP      r0,#2                 ;655
000022  d00b              BEQ      |L35.60|
000024  2804              CMP      r0,#4                 ;655
000026  d016              BEQ      |L35.86|
000028  2808              CMP      r0,#8                 ;655
00002a  d01a              BEQ      |L35.98|
;;;659    			break;
;;;660    		case E_SYS_LXT:
;;;661    			CLK->PWRCTL_BITS.LXT_EN = i32Enable;
;;;662    			break;
;;;663    		case E_SYS_HIRC:
;;;664    		    CLK->PWRCTL_BITS.HIRC_EN = i32Enable;
;;;665    			break;
;;;666    		case E_SYS_LIRC:
;;;667    		    CLK->PWRCTL_BITS.LIRC_EN = i32Enable;
;;;668    			break;				
;;;669    		default:
;;;670    			return E_DRVSYS_ERR_ARGUMENT;
00002c  4812              LDR      r0,|L35.120|
;;;671    	}
;;;672    	if(lock_sts)	LOCKREG();
;;;673    	
;;;674    	return E_SUCCESS;
;;;675    }
00002e  bd30              POP      {r4,r5,pc}
                  |L35.48|
000030  6818              LDR      r0,[r3,#0]            ;658
000032  07c9              LSLS     r1,r1,#31             ;658
000034  0840              LSRS     r0,r0,#1              ;658
000036  0040              LSLS     r0,r0,#1              ;658
000038  0fc9              LSRS     r1,r1,#31             ;658
00003a  e004              B        |L35.70|
                  |L35.60|
00003c  6818              LDR      r0,[r3,#0]            ;661
00003e  2502              MOVS     r5,#2                 ;661
000040  43a8              BICS     r0,r0,r5              ;661
000042  07c9              LSLS     r1,r1,#31             ;661
000044  0f89              LSRS     r1,r1,#30             ;661
                  |L35.70|
000046  4308              ORRS     r0,r0,r1              ;658
000048  6018              STR      r0,[r3,#0]            ;658
00004a  2a00              CMP      r2,#0                 ;672
00004c  d001              BEQ      |L35.82|
00004e  2000              MOVS     r0,#0                 ;672
000050  6020              STR      r0,[r4,#0]            ;672
                  |L35.82|
000052  2000              MOVS     r0,#0                 ;674
000054  bd30              POP      {r4,r5,pc}
                  |L35.86|
000056  6818              LDR      r0,[r3,#0]            ;664
000058  2504              MOVS     r5,#4                 ;664
00005a  43a8              BICS     r0,r0,r5              ;664
00005c  07c9              LSLS     r1,r1,#31             ;664
00005e  0f49              LSRS     r1,r1,#29             ;664
000060  e7f1              B        |L35.70|
                  |L35.98|
000062  6818              LDR      r0,[r3,#0]            ;667
000064  2508              MOVS     r5,#8                 ;667
000066  43a8              BICS     r0,r0,r5              ;667
000068  07c9              LSLS     r1,r1,#31             ;667
00006a  0f09              LSRS     r1,r1,#28             ;667
00006c  e7eb              B        |L35.70|
;;;676    
                          ENDP

00006e  0000              DCW      0x0000
                  |L35.112|
                          DCD      0x50000100
                  |L35.116|
                          DCD      0x50000200
                  |L35.120|
                          DCD      0xffff9603

                          AREA ||i.DrvSYS_SetPLLContent||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetPLLContent PROC
;;;906    /*---------------------------------------------------------------------------------------------------------*/
;;;907    void DrvSYS_SetPLLContent(uint32_t u32PllContent)
000000  4901              LDR      r1,|L36.8|
;;;908    {
;;;909    	CLK->PLLCTL  = u32PllContent;
000002  6248              STR      r0,[r1,#0x24]
;;;910    }
000004  4770              BX       lr
;;;911    
                          ENDP

000006  0000              DCW      0x0000
                  |L36.8|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_SetPLLMode||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetPLLMode PROC
;;;789    /*---------------------------------------------------------------------------------------------------------*/
;;;790    void DrvSYS_SetPLLMode(int32_t i32Flag)
000000  4a04              LDR      r2,|L37.20|
;;;791    {
;;;792    	CLK->PLLCTL_BITS.PD = i32Flag;
000002  6a51              LDR      r1,[r2,#0x24]
000004  01d3              LSLS     r3,r2,#7
000006  07c0              LSLS     r0,r0,#31
000008  4399              BICS     r1,r1,r3
00000a  0bc0              LSRS     r0,r0,#15
00000c  4301              ORRS     r1,r1,r0
00000e  6251              STR      r1,[r2,#0x24]
;;;793    }
000010  4770              BX       lr
;;;794    
                          ENDP

000012  0000              DCW      0x0000
                  |L37.20|
                          DCD      0x50000200

                          AREA ||i.DrvSYS_SetPowerDownWakeUpInt||, CODE, READONLY, ALIGN=2

                  DrvSYS_SetPowerDownWakeUpInt PROC
;;;711    /*---------------------------------------------------------------------------------------------------------*/
;;;712    void DrvSYS_SetPowerDownWakeUpInt(int32_t i32Enable, PWRWU_CALLBACK pdwucallbackFn, int32_t i32enWUDelay)
000000  b5f0              PUSH     {r4-r7,lr}
;;;713    {
;;;714    	uint32_t lock_sts = 0;
;;;715    	
;;;716    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4d18              LDR      r5,|L38.100|
000004  468e              MOV      lr,r1                 ;713
000006  6829              LDR      r1,[r5,#0]
000008  4694              MOV      r12,r2                ;713
00000a  07c9              LSLS     r1,r1,#31
00000c  17cb              ASRS     r3,r1,#31
00000e  1c5b              ADDS     r3,r3,#1
;;;717    	
;;;718    	if (lock_sts)	UNLOCKREG();
000010  d001              BEQ      |L38.22|
000012  2159              MOVS     r1,#0x59
000014  6029              STR      r1,[r5,#0]
                  |L38.22|
000016  2116              MOVS     r1,#0x16
000018  6029              STR      r1,[r5,#0]
00001a  2188              MOVS     r1,#0x88
00001c  6029              STR      r1,[r5,#0]
;;;719    	CLK->PWRCTL_BITS.PD_WK_IE = i32Enable;
00001e  4c12              LDR      r4,|L38.104|
000020  6822              LDR      r2,[r4,#0]
000022  2620              MOVS     r6,#0x20
000024  43b2              BICS     r2,r2,r6
000026  07c6              LSLS     r6,r0,#31
000028  0eb6              LSRS     r6,r6,#26
00002a  4332              ORRS     r2,r2,r6
00002c  6022              STR      r2,[r4,#0]
;;;720    	
;;;721    	if (i32Enable)
;;;722    	{		
;;;723    		CLK->PWRCTL_BITS.WK_DLY = i32enWUDelay;
00002e  2610              MOVS     r6,#0x10
000030  0649              LSLS     r1,r1,#25
000032  2200              MOVS     r2,#0                 ;714
000034  2800              CMP      r0,#0                 ;721
;;;724    		PWRWU_callbackFn = pdwucallbackFn;
000036  4f0d              LDR      r7,|L38.108|
;;;725    		NVIC_EnableIRQ(PDWU_IRQn);
;;;726    	}
;;;727    	else
;;;728    	{ 
;;;729    		CLK->PWRCTL_BITS.WK_DLY = 0;
000038  6820              LDR      r0,[r4,#0]
00003a  d009              BEQ      |L38.80|
00003c  43b0              BICS     r0,r0,r6              ;723
00003e  4666              MOV      r6,r12                ;723
000040  07f6              LSLS     r6,r6,#31             ;723
000042  0ef6              LSRS     r6,r6,#27             ;723
000044  4330              ORRS     r0,r0,r6              ;723
000046  6020              STR      r0,[r4,#0]            ;723
000048  4670              MOV      r0,lr                 ;724
00004a  6078              STR      r0,[r7,#4]            ;724  ; PWRWU_callbackFn
00004c  4808              LDR      r0,|L38.112|
00004e  e004              B        |L38.90|
                  |L38.80|
000050  43b0              BICS     r0,r0,r6
000052  6020              STR      r0,[r4,#0]
000054  4806              LDR      r0,|L38.112|
000056  607a              STR      r2,[r7,#4]  ; PWRWU_callbackFn
000058  3080              ADDS     r0,r0,#0x80
                  |L38.90|
00005a  6001              STR      r1,[r0,#0]
;;;730    		PWRWU_callbackFn = NULL;
;;;731    		NVIC_DisableIRQ(PDWU_IRQn);
;;;732    	}	
;;;733    	if (lock_sts)	LOCKREG();
00005c  2b00              CMP      r3,#0
00005e  d000              BEQ      |L38.98|
000060  602a              STR      r2,[r5,#0]
                  |L38.98|
;;;734    }
000062  bdf0              POP      {r4-r7,pc}
;;;735    
                          ENDP

                  |L38.100|
                          DCD      0x50000100
                  |L38.104|
                          DCD      0x50000200
                  |L38.108|
                          DCD      ||.data||
                  |L38.112|
                          DCD      0xe000e100

                          AREA ||i.DrvSYS_UnlockProtectedReg||, CODE, READONLY, ALIGN=2

                  DrvSYS_UnlockProtectedReg PROC
;;;107    /*---------------------------------------------------------------------------------------------------------*/
;;;108    int32_t DrvSYS_UnlockProtectedReg(void)
000000  4807              LDR      r0,|L39.32|
;;;109    {
;;;110    	uint32_t lockbit;
;;;111    
;;;112    	GCR->RegLockAddr = 0x59;
000002  2159              MOVS     r1,#0x59
000004  6001              STR      r1,[r0,#0]
;;;113    	GCR->RegLockAddr = 0x16;
000006  2116              MOVS     r1,#0x16
000008  6001              STR      r1,[r0,#0]
;;;114    	GCR->RegLockAddr = 0x88;
00000a  2188              MOVS     r1,#0x88
00000c  6001              STR      r1,[r0,#0]
;;;115    
;;;116    	lockbit = GCR->RegLockAddr & 0x01;
00000e  6800              LDR      r0,[r0,#0]
000010  07c0              LSLS     r0,r0,#31
000012  0fc0              LSRS     r0,r0,#31
;;;117    	return (lockbit)? 0 : E_DRVSYS_ERR_UNLOCK_FAIL;
000014  d001              BEQ      |L39.26|
000016  2000              MOVS     r0,#0
;;;118    } 
000018  4770              BX       lr
                  |L39.26|
00001a  4802              LDR      r0,|L39.36|
00001c  4770              BX       lr
;;;119     
                          ENDP

00001e  0000              DCW      0x0000
                  |L39.32|
                          DCD      0x50000100
                  |L39.36|
                          DCD      0xffff9601

                          AREA ||i.HIRC_IRQHandler||, CODE, READONLY, ALIGN=2

                  HIRC_IRQHandler PROC
;;;41     /*---------------------------------------------------------------------------------------------------------*/
;;;42     void HIRC_IRQHandler(void)
000000  b430              PUSH     {r4,r5}
;;;43     {
;;;44     	uint32_t u32IRCStatus;
;;;45     
;;;46     	u32IRCStatus = GCR->IRCTRIMISR;
000002  4912              LDR      r1,|L40.76|
000004  6888              LDR      r0,[r1,#8]
;;;47     	/* Clear the interrupt */
;;;48     	if (GCR->IRCTRIMISR_BITS.TRIM_FAIL_IS == 1)
000006  688a              LDR      r2,[r1,#8]
000008  0792              LSLS     r2,r2,#30
00000a  d503              BPL      |L40.20|
;;;49     		GCR->IRCTRIMISR_BITS.TRIM_FAIL_IS = 1;
00000c  688a              LDR      r2,[r1,#8]
00000e  2302              MOVS     r3,#2
000010  431a              ORRS     r2,r2,r3
000012  608a              STR      r2,[r1,#8]
                  |L40.20|
;;;50     
;;;51     	if (GCR->IRCTRIMISR_BITS.ERR_32K_IS == 1)
000014  688a              LDR      r2,[r1,#8]
000016  0752              LSLS     r2,r2,#29
000018  d503              BPL      |L40.34|
;;;52     		GCR->IRCTRIMISR_BITS.ERR_32K_IS = 1;
00001a  688a              LDR      r2,[r1,#8]
00001c  2304              MOVS     r3,#4
00001e  431a              ORRS     r2,r2,r3
000020  608a              STR      r2,[r1,#8]
                  |L40.34|
;;;53     
;;;54     	GCR->IRCTRIMCTL_BITS.TRIM_LOOP = 3;
000022  680a              LDR      r2,[r1,#0]
000024  2330              MOVS     r3,#0x30
000026  431a              ORRS     r2,r2,r3
000028  600a              STR      r2,[r1,#0]
;;;55     	GCR->IRCTRIMCTL_BITS.TRIM_SEL = g_trimClk;
00002a  680a              LDR      r2,[r1,#0]
00002c  0893              LSRS     r3,r2,#2
00002e  4a08              LDR      r2,|L40.80|
000030  009b              LSLS     r3,r3,#2
000032  68d4              LDR      r4,[r2,#0xc]  ; g_trimClk
000034  07a4              LSLS     r4,r4,#30
000036  0fa4              LSRS     r4,r4,#30
000038  4323              ORRS     r3,r3,r4
00003a  600b              STR      r3,[r1,#0]
;;;56     
;;;57     	/* Call	the	callback function of IRC interrupt */
;;;58     	if ( _pfIrcCallback )
00003c  6891              LDR      r1,[r2,#8]  ; _pfIrcCallback
00003e  2900              CMP      r1,#0
000040  d001              BEQ      |L40.70|
;;;59     		_pfIrcCallback(u32IRCStatus);
000042  bc30              POP      {r4,r5}
000044  4708              BX       r1
                  |L40.70|
;;;60     }
000046  bc30              POP      {r4,r5}
000048  4770              BX       lr
;;;61     
                          ENDP

00004a  0000              DCW      0x0000
                  |L40.76|
                          DCD      0x50000080
                  |L40.80|
                          DCD      ||.data||

                          AREA ||i.PWRWU_IRQHandler||, CODE, READONLY, ALIGN=2

                  PWRWU_IRQHandler PROC
;;;687    /*---------------------------------------------------------------------------------------------------------*/
;;;688    void PWRWU_IRQHandler(void)
000000  4904              LDR      r1,|L41.20|
;;;689    {
;;;690    	CLK->WK_INTSTS = 1;
000002  2001              MOVS     r0,#1
000004  6308              STR      r0,[r1,#0x30]
;;;691    	if (PWRWU_callbackFn != NULL)
000006  4804              LDR      r0,|L41.24|
000008  6840              LDR      r0,[r0,#4]  ; PWRWU_callbackFn
00000a  2800              CMP      r0,#0
00000c  d000              BEQ      |L41.16|
;;;692    		PWRWU_callbackFn();	
00000e  4700              BX       r0
                  |L41.16|
;;;693    }
000010  4770              BX       lr
;;;694    
                          ENDP

000012  0000              DCW      0x0000
                  |L41.20|
                          DCD      0x50000200
                  |L41.24|
                          DCD      ||.data||

                          AREA ||.data||, DATA, ALIGN=2

                  BOD_callbackFn
                          DCD      0x00000000
                  PWRWU_callbackFn
                          DCD      0x00000000
                  _pfIrcCallback
                          DCD      0x00000000
                  g_trimClk
                          DCD      0x00000000
                  _DrvSYS_PLL_Table
000010  ffff0110          DCW      0xffff,0x0110
000014  ffff0010          DCW      0xffff,0x0010
000018  001cffff          DCW      0x001c,0xffff
00001c  ffff0210          DCW      0xffff,0x0210
000020  ffff0110          DCW      0xffff,0x0110
000024  ffff0120          DCW      0xffff,0x0120
000028  ffff0200          DCW      0xffff,0x0200
00002c  ffff0100          DCW      0xffff,0x0100
000030  0230ffff          DCW      0x0230,0xffff
000034  0310ffff          DCW      0x0310,0xffff
000038  0210ffff          DCW      0x0210,0xffff
00003c  0220ffff          DCW      0x0220,0xffff
000040  ffff1320          DCW      0xffff,0x1320
000044  ffff0320          DCW      0xffff,0x0320
000048  0330ffff          DCW      0x0330,0xffff
