; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_pdma.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_pdma.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_pdma.crf ..\bsp\Driver\nano1xx_pdma.c]
                          THUMB

                          AREA ||i.PDMA_CRCEnableInt||, CODE, READONLY, ALIGN=2

                  PDMA_CRCEnableInt PROC
;;;131      */
;;;132    void PDMA_CRCEnableInt(uint32_t IntSource)
000000  4904              LDR      r1,|L1.20|
;;;133    {
;;;134    	PDMACRC->DMAIER |= IntSource;
000002  6a0a              LDR      r2,[r1,#0x20]
000004  4302              ORRS     r2,r2,r0
000006  620a              STR      r2,[r1,#0x20]
000008  2001              MOVS     r0,#1
00000a  4903              LDR      r1,|L1.24|
00000c  0680              LSLS     r0,r0,#26
00000e  6008              STR      r0,[r1,#0]
;;;135    
;;;136        /* Enable Specified Interrupt */
;;;137    	NVIC_EnableIRQ(PDMA_IRQn);
;;;138    }
000010  4770              BX       lr
;;;139    
                          ENDP

000012  0000              DCW      0x0000
                  |L1.20|
                          DCD      0x50008e00
                  |L1.24|
                          DCD      0xe000e100

                          AREA ||i.PDMA_Close||, CODE, READONLY, ALIGN=2

                  PDMA_Close PROC
;;;41       */
;;;42     void PDMA_Close(void)
000000  4901              LDR      r1,|L2.8|
;;;43     {
;;;44        	/* Disable All PDMA clock */
;;;45     	PDMAGCR->CSR = 0;
000002  2000              MOVS     r0,#0
000004  6008              STR      r0,[r1,#0]
;;;46     
;;;47     }
000006  4770              BX       lr
;;;48     
                          ENDP

                  |L2.8|
                          DCD      0x50008f00

                          AREA ||i.PDMA_EnableInt||, CODE, READONLY, ALIGN=2

                  PDMA_EnableInt PROC
;;;93       */
;;;94     void PDMA_EnableInt(PDMA_TypeDef *ch, uint32_t IntSource)
000000  6a02              LDR      r2,[r0,#0x20]
;;;95     {
;;;96     	ch->IER |= IntSource;
000002  430a              ORRS     r2,r2,r1
000004  6202              STR      r2,[r0,#0x20]
000006  2001              MOVS     r0,#1
000008  4901              LDR      r1,|L3.16|
00000a  0680              LSLS     r0,r0,#26
00000c  6008              STR      r0,[r1,#0]
;;;97     
;;;98         /* Enable Specified Interrupt */
;;;99     	NVIC_EnableIRQ(PDMA_IRQn);
;;;100    }
00000e  4770              BX       lr
;;;101    
                          ENDP

                  |L3.16|
                          DCD      0xe000e100

                          AREA ||i.PDMA_Open||, CODE, READONLY, ALIGN=1

                  PDMA_Open PROC
;;;54       */
;;;55     void PDMA_Open(PDMA_TypeDef *ch, STR_PDMA_T *sParam)
000000  b510              PUSH     {r4,lr}
;;;56     {
;;;57     	/*-----------------------------------------------------------------------------------------------------*/
;;;58         /* Set PDMA settings                                                                                   */
;;;59         /*-----------------------------------------------------------------------------------------------------*/
;;;60     	ch->SAR = sParam->SrcAddr;			/* Source Start Address */
000002  684a              LDR      r2,[r1,#4]
000004  6042              STR      r2,[r0,#4]
;;;61     	ch->DAR = sParam->DestAddr;			/* Destination Start Address */
000006  68ca              LDR      r2,[r1,#0xc]
000008  6082              STR      r2,[r0,#8]
;;;62     	ch->BCR = sParam->ByteCnt;			/* Byte Count */
00000a  698a              LDR      r2,[r1,#0x18]
00000c  60c2              STR      r2,[r0,#0xc]
;;;63     	ch->CSR = (uint32_t)sParam->SrcCtrl |sParam->DestCtrl |sParam->TransWidth |sParam->Mode |
00000e  688b              LDR      r3,[r1,#8]
000010  680a              LDR      r2,[r1,#0]
000012  694c              LDR      r4,[r1,#0x14]
000014  431a              ORRS     r2,r2,r3
000016  690b              LDR      r3,[r1,#0x10]
000018  69c9              LDR      r1,[r1,#0x1c]
00001a  4323              ORRS     r3,r3,r4
00001c  431a              ORRS     r2,r2,r3
00001e  430a              ORRS     r2,r2,r1
000020  2101              MOVS     r1,#1
000022  430a              ORRS     r2,r2,r1
000024  6002              STR      r2,[r0,#0]
;;;64     			  sParam->IsTimeOutEnable |PDMA_CSR_CEN;
;;;65     }
000026  bd10              POP      {r4,pc}
;;;66     
                          ENDP


                          AREA ||i.PDMA_OpenCRC||, CODE, READONLY, ALIGN=2

                  PDMA_OpenCRC PROC
;;;107      */
;;;108    void PDMA_OpenCRC(STR_CRC_T *sParam)
000000  b530              PUSH     {r4,r5,lr}
;;;109    {
;;;110    	/*-----------------------------------------------------------------------------------------------------*/
;;;111        /* Set CRC settings                                                                                   */
;;;112        /*-----------------------------------------------------------------------------------------------------*/
;;;113    	PDMAGCR->CSR |= (1<<24);					/* Enable CRC Clock */
000002  4a14              LDR      r2,|L5.84|
000004  6813              LDR      r3,[r2,#0]
000006  2101              MOVS     r1,#1
000008  0609              LSLS     r1,r1,#24
00000a  430b              ORRS     r3,r3,r1
00000c  6013              STR      r3,[r2,#0]
;;;114    
;;;115    	PDMACRC->DMASAR = sParam->u32DMASrcAddr;		/* Set Source Address */
00000e  4d12              LDR      r5,|L5.88|
000010  68c2              LDR      r2,[r0,#0xc]
000012  606a              STR      r2,[r5,#4]
;;;116    	PDMACRC->DMABCR = sParam->u16DMAByteCnt;		/* Set Byte Count Register */
000014  8a02              LDRH     r2,[r0,#0x10]
000016  60ea              STR      r2,[r5,#0xc]
;;;117    
;;;118    	PDMACRC->CTL = sParam->u32Mode | sParam->u32CPUWdlen | 
000018  6804              LDR      r4,[r0,#0]
00001a  6842              LDR      r2,[r0,#4]
00001c  4314              ORRS     r4,r4,r2
00001e  7a02              LDRB     r2,[r0,#8]
000020  2a00              CMP      r2,#0
000022  d000              BEQ      |L5.38|
;;;119    			(sParam->bIsChecksumComplement ? PDMACRC_CTL_CHECKSUM_COM : 0) |
000024  00ca              LSLS     r2,r1,#3
                  |L5.38|
000026  7a43              LDRB     r3,[r0,#9]
000028  2b00              CMP      r3,#0
00002a  d001              BEQ      |L5.48|
;;;120    			(sParam->bIsWriteDataComplement ? PDMACRC_CTL_WDATA_COM : 0) |
00002c  2301              MOVS     r3,#1
00002e  069b              LSLS     r3,r3,#26
                  |L5.48|
000030  431a              ORRS     r2,r2,r3
000032  4314              ORRS     r4,r4,r2
000034  7a82              LDRB     r2,[r0,#0xa]
000036  2a00              CMP      r2,#0
000038  d001              BEQ      |L5.62|
;;;121    			(sParam->bIsChecksumReverse ? PDMACRC_CTL_CHECKSUM_RVS : 0) |
00003a  2201              MOVS     r2,#1
00003c  0652              LSLS     r2,r2,#25
                  |L5.62|
00003e  7ac0              LDRB     r0,[r0,#0xb]
000040  4314              ORRS     r4,r4,r2
000042  2800              CMP      r0,#0
000044  d100              BNE      |L5.72|
;;;122    			(sParam->bIsWriteDataReverse ? PDMACRC_CTL_WDATA_RVS : 0) |
000046  2100              MOVS     r1,#0
                  |L5.72|
000048  430c              ORRS     r4,r4,r1
00004a  2001              MOVS     r0,#1
00004c  4304              ORRS     r4,r4,r0
00004e  602c              STR      r4,[r5,#0]
;;;123    			PDMACRC_CTL_CEN;
;;;124    }
000050  bd30              POP      {r4,r5,pc}
;;;125    
                          ENDP

000052  0000              DCW      0x0000
                  |L5.84|
                          DCD      0x50008f00
                  |L5.88|
                          DCD      0x50008e00

                          AREA ||i.PDMA_OpenVDMA||, CODE, READONLY, ALIGN=2

                  PDMA_OpenVDMA PROC
;;;71       */
;;;72     void PDMA_OpenVDMA(STR_VDMA_T *sParam)
000000  490c              LDR      r1,|L6.52|
;;;73     {
;;;74     	/*-----------------------------------------------------------------------------------------------------*/
;;;75         /* Set VDMA settings                                                                                   */
;;;76         /*-----------------------------------------------------------------------------------------------------*/
;;;77     	PDMAGCR->CSR |= (1<<8);					/* Enable Channel Clock */
000002  680a              LDR      r2,[r1,#0]
000004  23ff              MOVS     r3,#0xff
000006  3301              ADDS     r3,#1
000008  431a              ORRS     r2,r2,r3
00000a  600a              STR      r2,[r1,#0]
;;;78     
;;;79     	VDMA->SAR    = sParam->SrcAddr;			/* Set Source Address */
00000c  490a              LDR      r1,|L6.56|
00000e  6842              LDR      r2,[r0,#4]
000010  604a              STR      r2,[r1,#4]
;;;80     	VDMA->DAR    = sParam->DestAddr;		/* Set Destination Address */
000012  6882              LDR      r2,[r0,#8]
000014  608a              STR      r2,[r1,#8]
;;;81     	VDMA->BCR    = sParam->ByteCnt;			/* Set Byte Count Register */
000016  68c2              LDR      r2,[r0,#0xc]
000018  60ca              STR      r2,[r1,#0xc]
;;;82     	VDMA->DASOCR = sParam->u16Dastobl;
00001a  8b02              LDRH     r2,[r0,#0x18]
00001c  630a              STR      r2,[r1,#0x30]
;;;83     	VDMA->SASOCR = (sParam->u16Stbc << 16) | sParam->u16Sastobl;
00001e  6942              LDR      r2,[r0,#0x14]
000020  2310              MOVS     r3,#0x10
000022  41da              RORS     r2,r2,r3
000024  62ca              STR      r2,[r1,#0x2c]
;;;84     
;;;85     	VDMA->CSR = sParam->Dir | sParam->IsStrideEnable | VDMA_CSR_CEN;
000026  6802              LDR      r2,[r0,#0]
000028  6900              LDR      r0,[r0,#0x10]
00002a  4302              ORRS     r2,r2,r0
00002c  2001              MOVS     r0,#1
00002e  4302              ORRS     r2,r2,r0
000030  600a              STR      r2,[r1,#0]
;;;86     }
000032  4770              BX       lr
;;;87     
                          ENDP

                  |L6.52|
                          DCD      0x50008f00
                  |L6.56|
                          DCD      0x50008000

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_pdma.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___14_nano1xx_pdma_c_603ef63b____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___14_nano1xx_pdma_c_603ef63b____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___14_nano1xx_pdma_c_603ef63b____REVSH|
#line 130
|__asm___14_nano1xx_pdma_c_603ef63b____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
