; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_rtc.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_rtc.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_rtc.crf ..\bsp\Driver\nano1xx_rtc.c]
                          THUMB

                          AREA ||i.RTC_Close||, CODE, READONLY, ALIGN=2

                  RTC_Close PROC
;;;1107    */
;;;1108   int32_t RTC_Close (void)
000000  b500              PUSH     {lr}
000002  2001              MOVS     r0,#1
000004  4903              LDR      r1,|L1.20|
000006  07c0              LSLS     r0,r0,#31
000008  6008              STR      r0,[r1,#0]
;;;1109   {
;;;1110     	NVIC_DisableIRQ(RTC_IRQn);
;;;1111     
;;;1112     	RTC_DisableInt(RTC_RIER_TIER | RTC_RIER_AIER | RTC_RIER_SNOOPIER);
00000a  2007              MOVS     r0,#7
00000c  f7fffffe          BL       RTC_DisableInt
;;;1113   	
;;;1114       return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;1115   }
000012  bd00              POP      {pc}
;;;1116   
                          ENDP

                  |L1.20|
                          DCD      0xe000e180

                          AREA ||i.RTC_DisableInt||, CODE, READONLY, ALIGN=2

                  RTC_DisableInt PROC
;;;1066    */
;;;1067   int32_t RTC_DisableInt(uint32_t i32IntSrc)
000000  490f              LDR      r1,|L2.64|
;;;1068   {
;;;1069   	
;;;1070   	if(i32IntSrc & RTC_RIER_TIER)
000002  0782              LSLS     r2,r0,#30
000004  d506              BPL      |L2.20|
;;;1071   	{	
;;;1072   		RTC->RIER &= ~RTC_RIER_TIER; 
000006  6a8b              LDR      r3,[r1,#0x28]
000008  2202              MOVS     r2,#2
00000a  4393              BICS     r3,r3,r2
00000c  628b              STR      r3,[r1,#0x28]
;;;1073   		RTC->RIIR |= RTC_RIIR_TIS; 
00000e  6acb              LDR      r3,[r1,#0x2c]
000010  4313              ORRS     r3,r3,r2
000012  62cb              STR      r3,[r1,#0x2c]
                  |L2.20|
;;;1074   	}
;;;1075   	
;;;1076   	if(i32IntSrc & RTC_RIER_AIER)
000014  07c2              LSLS     r2,r0,#31
000016  d007              BEQ      |L2.40|
;;;1077   	{
;;;1078   		RTC->RIER &= ~RTC_RIER_AIER; 
000018  6a8a              LDR      r2,[r1,#0x28]
00001a  0852              LSRS     r2,r2,#1
00001c  0052              LSLS     r2,r2,#1
00001e  628a              STR      r2,[r1,#0x28]
;;;1079   		RTC->RIIR |= RTC_RIIR_AIS;
000020  6aca              LDR      r2,[r1,#0x2c]
000022  2301              MOVS     r3,#1
000024  431a              ORRS     r2,r2,r3
000026  62ca              STR      r2,[r1,#0x2c]
                  |L2.40|
;;;1080   	}
;;;1081   	
;;;1082   	if(i32IntSrc & RTC_RIER_SNOOPIER)
000028  0740              LSLS     r0,r0,#29
00002a  d506              BPL      |L2.58|
;;;1083   	{
;;;1084   		RTC->RIER &= ~RTC_RIER_SNOOPIER; 
00002c  6a8a              LDR      r2,[r1,#0x28]
00002e  2004              MOVS     r0,#4
000030  4382              BICS     r2,r2,r0
000032  628a              STR      r2,[r1,#0x28]
;;;1085   		RTC->RIIR |= RTC_RIIR_SNOOPIS; 
000034  6aca              LDR      r2,[r1,#0x2c]
000036  4302              ORRS     r2,r2,r0
000038  62ca              STR      r2,[r1,#0x2c]
                  |L2.58|
;;;1086   	}
;;;1087   
;;;1088   	return E_SUCCESS;	
00003a  2000              MOVS     r0,#0
;;;1089   
;;;1090   }
00003c  4770              BX       lr
;;;1091   
                          ENDP

00003e  0000              DCW      0x0000
                  |L2.64|
                          DCD      0x40008000

                          AREA ||i.RTC_DisableSpareFunc||, CODE, READONLY, ALIGN=2

                  RTC_DisableSpareFunc PROC
;;;953     */
;;;954    void RTC_DisableSpareFunc(void)
000000  b500              PUSH     {lr}
;;;955    {
;;;956    	RTC_WriteEnable();
000002  f7fffffe          BL       RTC_WriteEnable
;;;957    
;;;958    	/* Disable snooper pin event detection */
;;;959    	RTC->SPRCTL &= ~RTC_SPRCTL_SNOOPEN;
000006  4804              LDR      r0,|L3.24|
000008  6bc1              LDR      r1,[r0,#0x3c]
00000a  0849              LSRS     r1,r1,#1
00000c  0049              LSLS     r1,r1,#1
00000e  63c1              STR      r1,[r0,#0x3c]
                  |L3.16|
;;;960    	while((RTC->SPRCTL & RTC_SPRCTL_SPRRDY) == 0);
000010  6bc1              LDR      r1,[r0,#0x3c]
000012  0609              LSLS     r1,r1,#24
000014  d5fc              BPL      |L3.16|
;;;961    }
000016  bd00              POP      {pc}
;;;962    
                          ENDP

                  |L3.24|
                          DCD      0x40008000

                          AREA ||i.RTC_EnableInt||, CODE, READONLY, ALIGN=2

                  RTC_EnableInt PROC
;;;1035    */
;;;1036   int32_t RTC_EnableInt(uint32_t str_IntSrc)
000000  4904              LDR      r1,|L4.20|
;;;1037   {
;;;1038   	RTC->RIER |= str_IntSrc; 
000002  6a8a              LDR      r2,[r1,#0x28]
000004  4302              ORRS     r2,r2,r0
000006  628a              STR      r2,[r1,#0x28]
000008  0408              LSLS     r0,r1,#16
00000a  4903              LDR      r1,|L4.24|
00000c  6008              STR      r0,[r1,#0]
;;;1039   	
;;;1040   	NVIC_EnableIRQ(RTC_IRQn); 
;;;1041   
;;;1042   	return E_SUCCESS;
00000e  2000              MOVS     r0,#0
;;;1043   
;;;1044   }
000010  4770              BX       lr
;;;1045   
                          ENDP

000012  0000              DCW      0x0000
                  |L4.20|
                          DCD      0x40008000
                  |L4.24|
                          DCD      0xe000e100

                          AREA ||i.RTC_EnableSpareFunc||, CODE, READONLY, ALIGN=2

                  RTC_EnableSpareFunc PROC
;;;915     */
;;;916    void RTC_EnableSpareFunc(uint32_t eSpareEdge)
000000  b510              PUSH     {r4,lr}
;;;917    {
000002  4604              MOV      r4,r0
;;;918    	RTC_WriteEnable();
000004  f7fffffe          BL       RTC_WriteEnable
;;;919    
;;;920    	/* detection edge select */
;;;921    	if(eSpareEdge)
;;;922    	{
;;;923    		RTC->SPRCTL |= RTC_SPRCTL_SNOOPEDGE;
000008  4909              LDR      r1,|L5.48|
00000a  2202              MOVS     r2,#2
;;;924    	}
;;;925    	else
;;;926    	{
;;;927    		RTC->SPRCTL &= ~RTC_SPRCTL_SNOOPEDGE;
00000c  6bc8              LDR      r0,[r1,#0x3c]
00000e  2c00              CMP      r4,#0                 ;921
000010  d001              BEQ      |L5.22|
000012  4310              ORRS     r0,r0,r2              ;923
000014  e000              B        |L5.24|
                  |L5.22|
000016  4390              BICS     r0,r0,r2
                  |L5.24|
000018  63c8              STR      r0,[r1,#0x3c]         ;923
                  |L5.26|
;;;928    	}
;;;929    
;;;930    	while((RTC->SPRCTL & RTC_SPRCTL_SPRRDY) == 0);
00001a  6bc8              LDR      r0,[r1,#0x3c]
00001c  0600              LSLS     r0,r0,#24
00001e  d5fc              BPL      |L5.26|
;;;931    	
;;;932    	/* enable snooper pin event detection */
;;;933    	RTC->SPRCTL |= RTC_SPRCTL_SNOOPEN;
000020  6bc8              LDR      r0,[r1,#0x3c]
000022  2201              MOVS     r2,#1
000024  4310              ORRS     r0,r0,r2
000026  63c8              STR      r0,[r1,#0x3c]
                  |L5.40|
;;;934    	while((RTC->SPRCTL & RTC_SPRCTL_SPRRDY) == 0);
000028  6bc8              LDR      r0,[r1,#0x3c]
00002a  0600              LSLS     r0,r0,#24
00002c  d5fc              BPL      |L5.40|
;;;935    	
;;;936    }
00002e  bd10              POP      {r4,pc}
;;;937    
                          ENDP

                  |L5.48|
                          DCD      0x40008000

                          AREA ||i.RTC_Init||, CODE, READONLY, ALIGN=2

                  RTC_Init PROC
;;;172     */
;;;173    int32_t RTC_Init (void)
000000  b530              PUSH     {r4,r5,lr}
;;;174    {
;;;175        int32_t i32i =0;
;;;176    	volatile int32_t i32delay=1000;
;;;177    	uint32_t lock_sts = 0;
;;;178    
;;;179    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4b17              LDR      r3,|L6.96|
000004  217d              MOVS     r1,#0x7d              ;176
000006  6818              LDR      r0,[r3,#0]
000008  00c9              LSLS     r1,r1,#3              ;176
00000a  07c0              LSLS     r0,r0,#31
00000c  17c2              ASRS     r2,r0,#31
00000e  1c52              ADDS     r2,r2,#1
;;;180    
;;;181        /*-----------------------------------------------------------------------------------------------------*/
;;;182        /* Initial time data struct and some parameters.                                                       */
;;;183        /*-----------------------------------------------------------------------------------------------------*/
;;;184    
;;;185    	/* un-lock */
;;;186    	if (lock_sts)	UNLOCKREG();
000010  d005              BEQ      |L6.30|
000012  2059              MOVS     r0,#0x59
000014  6018              STR      r0,[r3,#0]
000016  2016              MOVS     r0,#0x16
000018  6018              STR      r0,[r3,#0]
00001a  2088              MOVS     r0,#0x88
00001c  6018              STR      r0,[r3,#0]
                  |L6.30|
;;;187    	/* Enable 32K Clock */
;;;188    	CLK->PWRCTL |= CLK_PWRCTL_LXT_EN;
00001e  4c11              LDR      r4,|L6.100|
000020  6820              LDR      r0,[r4,#0]
000022  2502              MOVS     r5,#2
000024  4328              ORRS     r0,r0,r5
000026  6020              STR      r0,[r4,#0]
                  |L6.40|
;;;189    	  
;;;190    	/* Waiting for 32K stable */
;;;191      	while(i32delay--);
000028  4608              MOV      r0,r1
00002a  1e49              SUBS     r1,r1,#1
00002c  2800              CMP      r0,#0
00002e  d1fb              BNE      |L6.40|
;;;192    	
;;;193    	/* Enable RTC Clock */
;;;194    	CLK->APBCLK |= CLK_APBCLK_RTC_EN;
000030  68a0              LDR      r0,[r4,#8]
000032  4328              ORRS     r0,r0,r5
000034  60a0              STR      r0,[r4,#8]
;;;195    	
;;;196    	if (lock_sts)	LOCKREG();
000036  2a00              CMP      r2,#0
000038  d001              BEQ      |L6.62|
00003a  2000              MOVS     r0,#0
00003c  6018              STR      r0,[r3,#0]
                  |L6.62|
;;;197    
;;;198        /*-----------------------------------------------------------------------------------------------------*/
;;;199        /* When RTC is power on, write 0xa5eb1357 to RTC_INIR to reset all logic.                              */
;;;200        /*-----------------------------------------------------------------------------------------------------*/
;;;201    	
;;;202    	RTC->INIR = DRVRTC_INIT_KEY;
00003e  490b              LDR      r1,|L6.108|
000040  4809              LDR      r0,|L6.104|
000042  6008              STR      r0,[r1,#0]
;;;203    
;;;204        for (i32i = 0 ; i32i < DRVRTC_WAIT_COUNT ; i32i++)
000044  2000              MOVS     r0,#0
                  |L6.70|
;;;205        {
;;;206    		if(RTC->INIR == 0x1)  /* Check RTC_INIR[0] to find out RTC reset signal */
000046  680a              LDR      r2,[r1,#0]
000048  2a01              CMP      r2,#1
00004a  d003              BEQ      |L6.84|
00004c  1c40              ADDS     r0,r0,#1              ;204
00004e  1c42              ADDS     r2,r0,#1              ;204
000050  d1f9              BNE      |L6.70|
000052  e003              B        |L6.92|
                  |L6.84|
;;;207            { 
;;;208                break;
;;;209            }
;;;210        }
;;;211    
;;;212        if (i32i == DRVRTC_WAIT_COUNT)
000054  1c40              ADDS     r0,r0,#1
000056  d001              BEQ      |L6.92|
;;;213        {
;;;214            RTCDEBUG("\nRTC: DrvRTC_Init, initial RTC FAILED!\n");
;;;215            return E_DRVRTC_ERR_EIO;
;;;216        }
;;;217    
;;;218        return E_SUCCESS;
000058  2000              MOVS     r0,#0
;;;219    }
00005a  bd30              POP      {r4,r5,pc}
                  |L6.92|
00005c  2006              MOVS     r0,#6                 ;215
00005e  bd30              POP      {r4,r5,pc}
;;;220    
                          ENDP

                  |L6.96|
                          DCD      0x50000100
                  |L6.100|
                          DCD      0x50000200
                  |L6.104|
                          DCD      0xa5eb1357
                  |L6.108|
                          DCD      0x40008000

                          AREA ||i.RTC_Open||, CODE, READONLY, ALIGN=2

                  RTC_Open PROC
;;;260     */
;;;261    int32_t RTC_Open (S_DRVRTC_TIME_DATA_T *sPt)
000000  b5f8              PUSH     {r3-r7,lr}
;;;262    {
;;;263        uint32_t u32Reg;
;;;264    	
;;;265    	volatile int32_t i32delay=1000;
000002  267d              MOVS     r6,#0x7d
000004  4604              MOV      r4,r0                 ;262
000006  00f6              LSLS     r6,r6,#3
;;;266            
;;;267        /*-----------------------------------------------------------------------------------------------------*/
;;;268        /* DO BASIC JUDGEMENT TO Check RTC time data value is reasonable or not.                               */
;;;269        /*-----------------------------------------------------------------------------------------------------*/
;;;270    	assert_param(	!( ((sPt->u32Year - DRVRTC_YEAR2000) > 99)|
;;;271    							((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12))|
;;;272    							((sPt->u32cDay   == 0) || (sPt->u32cDay   > 31))));
;;;273    
;;;274    	assert_param( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) || (sPt->u8cClockDisplay==DRVRTC_CLOCK_24));
;;;275    
;;;276    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) &&
;;;277    							((sPt->u32cHour == 0) || (sPt->u32cHour > 12))));
;;;278    
;;;279    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_24) &&
;;;280    							(sPt->u32cHour > 23)));
;;;281    
;;;282    	assert_param(	!((sPt->u32cMinute > 59) |
;;;283    							(sPt->u32cSecond > 59) |
;;;284    							(sPt->u32cSecond > 59)));
;;;285    
;;;286    	assert_param( !(sPt->u32cDayOfWeek > 6) );
;;;287    
;;;288    
;;;289        /*-----------------------------------------------------------------------------------------------------*/
;;;290        /* Important, call DrvRTC_WriteEnable() before write data into any register.                              */
;;;291        /* User should be write data as soon as possible.Access enable wiil clear after 200ms                  */
;;;292    	/*-----------------------------------------------------------------------------------------------------*/
;;;293        g_u32Reg = RTC_WriteEnable();
000008  f7fffffe          BL       RTC_WriteEnable
00000c  4601              MOV      r1,r0
00000e  483a              LDR      r0,|L7.248|
000010  6041              STR      r1,[r0,#4]  ; g_u32Reg
;;;294        if (g_u32Reg != 0)
000012  6840              LDR      r0,[r0,#4]  ; g_u32Reg
000014  2800              CMP      r0,#0
000016  d001              BEQ      |L7.28|
;;;295        {
;;;296            return E_DRVRTC_ERR_FAILED;
000018  2009              MOVS     r0,#9
;;;297        }
;;;298        
;;;299        /*-----------------------------------------------------------------------------------------------------*/
;;;300        /* Second, set RTC 24/12 hour setting                                                                  */
;;;301        /*-----------------------------------------------------------------------------------------------------*/
;;;302        if (sPt->u8cClockDisplay == DRVRTC_CLOCK_12)
;;;303        {
;;;304            RTC_WriteEnable();
;;;305    		RTC->TSSR &= ~RTC_TSSR_24hr;
;;;306    
;;;307            /*-------------------------------------------------------------------------------------------------*/
;;;308            /* important, range of 12-hour PM mode is 21 upto 32                                               */
;;;309            /*-------------------------------------------------------------------------------------------------*/
;;;310            if (sPt->u8cAmPm == DRVRTC_PM)
;;;311                sPt->u32cHour += 20;
;;;312        }
;;;313        else                                                                               /* DRVRTC_CLOCK_24 */
;;;314        {
;;;315            RTC_WriteEnable();
;;;316    		RTC->TSSR |= RTC_TSSR_24hr;
;;;317            RTCDEBUG ("RTC: 24-hour\n");
;;;318        }
;;;319    
;;;320        /*-----------------------------------------------------------------------------------------------------*/
;;;321        /* Set RTC Calender Loading                                                                            */
;;;322        /*-----------------------------------------------------------------------------------------------------*/
;;;323        u32Reg    = ((sPt->u32Year - DRVRTC_YEAR2000) / 10) << 20;
;;;324        u32Reg    |= (((sPt->u32Year - DRVRTC_YEAR2000) % 10) << 16);
;;;325        u32Reg    |= ((sPt->u32cMonth  / 10) << 12);
;;;326        u32Reg    |= ((sPt->u32cMonth  % 10) << 8);
;;;327        u32Reg    |= ((sPt->u32cDay    / 10) << 4);
;;;328        u32Reg    |= (sPt->u32cDay     % 10);
;;;329        g_u32Reg = u32Reg;
;;;330    	
;;;331    	RTC_WriteEnable();
;;;332    	RTC->TSSR |= RTC_TSSR_24hr;
;;;333        RTC->CLR = (uint32_t)g_u32Reg;
;;;334    
;;;335    	/*-----------------------------------------------------------------------------------------------------*/
;;;336        /* Set RTC Time Loading                                                                                */
;;;337        /*-----------------------------------------------------------------------------------------------------*/
;;;338        u32Reg     = ((sPt->u32cHour / 10) << 20);
;;;339        u32Reg    |= ((sPt->u32cHour % 10) << 16);
;;;340        u32Reg    |= ((sPt->u32cMinute / 10) << 12);
;;;341        u32Reg    |= ((sPt->u32cMinute % 10) << 8);
;;;342        u32Reg    |= ((sPt->u32cSecond / 10) << 4);
;;;343        u32Reg    |= (sPt->u32cSecond % 10);
;;;344        g_u32Reg = u32Reg;
;;;345    
;;;346     	RTC_WriteEnable();
;;;347        RTC->TLR = (uint32_t)g_u32Reg;
;;;348    
;;;349    	RTC->DWR = sPt->u32cDayOfWeek;
;;;350    
;;;351    	RTC->TTR &= ~RTC_TTR_TWKE;
;;;352    	RTC->TTR |= sPt->u8IsEnableWakeUp ? RTC_TTR_TWKE:0;
;;;353    
;;;354    	/* Waiting for RTC settings stable */
;;;355      	while(i32delay--);
;;;356    
;;;357        return E_SUCCESS;
;;;358    }
00001a  bdf8              POP      {r3-r7,pc}
                  |L7.28|
00001c  7820              LDRB     r0,[r4,#0]            ;302
00001e  4d37              LDR      r5,|L7.252|
000020  2800              CMP      r0,#0                 ;302
000022  d05b              BEQ      |L7.220|
000024  f7fffffe          BL       RTC_WriteEnable
000028  6968              LDR      r0,[r5,#0x14]         ;316
00002a  2101              MOVS     r1,#1                 ;316
00002c  4308              ORRS     r0,r0,r1              ;316
00002e  6168              STR      r0,[r5,#0x14]         ;316
                  |L7.48|
000030  207d              MOVS     r0,#0x7d              ;323
000032  69e1              LDR      r1,[r4,#0x1c]         ;323
000034  0100              LSLS     r0,r0,#4              ;323
000036  1a08              SUBS     r0,r1,r0              ;323
000038  210a              MOVS     r1,#0xa               ;323
00003a  f7fffffe          BL       __aeabi_uidivmod
00003e  040f              LSLS     r7,r1,#16             ;324
000040  0500              LSLS     r0,r0,#20             ;323
000042  4307              ORRS     r7,r7,r0              ;324
000044  210a              MOVS     r1,#0xa               ;325
000046  69a0              LDR      r0,[r4,#0x18]         ;325
000048  f7fffffe          BL       __aeabi_uidivmod
00004c  0300              LSLS     r0,r0,#12             ;325
00004e  4338              ORRS     r0,r0,r7              ;325
000050  020f              LSLS     r7,r1,#8              ;326
000052  4307              ORRS     r7,r7,r0              ;326
000054  210a              MOVS     r1,#0xa               ;327
000056  6960              LDR      r0,[r4,#0x14]         ;327
000058  f7fffffe          BL       __aeabi_uidivmod
00005c  0100              LSLS     r0,r0,#4              ;327
00005e  4338              ORRS     r0,r0,r7              ;327
000060  4f25              LDR      r7,|L7.248|
000062  4301              ORRS     r1,r1,r0              ;328
000064  6079              STR      r1,[r7,#4]            ;329  ; g_u32Reg
000066  f7fffffe          BL       RTC_WriteEnable
00006a  6968              LDR      r0,[r5,#0x14]         ;332
00006c  2101              MOVS     r1,#1                 ;332
00006e  4308              ORRS     r0,r0,r1              ;332
000070  6168              STR      r0,[r5,#0x14]         ;332
000072  6878              LDR      r0,[r7,#4]            ;333  ; g_u32Reg
000074  6128              STR      r0,[r5,#0x10]         ;333
000076  210a              MOVS     r1,#0xa               ;338
000078  68e0              LDR      r0,[r4,#0xc]          ;338
00007a  f7fffffe          BL       __aeabi_uidivmod
00007e  040a              LSLS     r2,r1,#16             ;339
000080  0500              LSLS     r0,r0,#20             ;338
000082  4302              ORRS     r2,r2,r0              ;339
000084  9200              STR      r2,[sp,#0]            ;340
000086  210a              MOVS     r1,#0xa               ;340
000088  68a0              LDR      r0,[r4,#8]            ;340
00008a  f7fffffe          BL       __aeabi_uidivmod
00008e  9a00              LDR      r2,[sp,#0]            ;340
000090  0300              LSLS     r0,r0,#12             ;340
000092  4310              ORRS     r0,r0,r2              ;340
000094  020a              LSLS     r2,r1,#8              ;341
000096  4302              ORRS     r2,r2,r0              ;341
000098  9200              STR      r2,[sp,#0]            ;342
00009a  210a              MOVS     r1,#0xa               ;342
00009c  6860              LDR      r0,[r4,#4]            ;342
00009e  f7fffffe          BL       __aeabi_uidivmod
0000a2  9a00              LDR      r2,[sp,#0]            ;342
0000a4  0100              LSLS     r0,r0,#4              ;342
0000a6  4310              ORRS     r0,r0,r2              ;342
0000a8  4301              ORRS     r1,r1,r0              ;343
0000aa  6079              STR      r1,[r7,#4]            ;344  ; g_u32Reg
0000ac  f7fffffe          BL       RTC_WriteEnable
0000b0  6878              LDR      r0,[r7,#4]            ;347  ; g_u32Reg
0000b2  60e8              STR      r0,[r5,#0xc]          ;347
0000b4  6920              LDR      r0,[r4,#0x10]         ;349
0000b6  61a8              STR      r0,[r5,#0x18]         ;349
0000b8  6b28              LDR      r0,[r5,#0x30]         ;351
0000ba  2108              MOVS     r1,#8                 ;351
0000bc  4388              BICS     r0,r0,r1              ;351
0000be  6328              STR      r0,[r5,#0x30]         ;351
0000c0  6b29              LDR      r1,[r5,#0x30]         ;352
0000c2  3420              ADDS     r4,r4,#0x20           ;352
0000c4  7820              LDRB     r0,[r4,#0]            ;352
0000c6  2800              CMP      r0,#0                 ;352
0000c8  d000              BEQ      |L7.204|
0000ca  2008              MOVS     r0,#8                 ;352
                  |L7.204|
0000cc  4301              ORRS     r1,r1,r0              ;352
0000ce  6329              STR      r1,[r5,#0x30]         ;352
                  |L7.208|
0000d0  4635              MOV      r5,r6                 ;355
0000d2  1e76              SUBS     r6,r6,#1              ;355
0000d4  2d00              CMP      r5,#0                 ;355
0000d6  d1fb              BNE      |L7.208|
0000d8  2000              MOVS     r0,#0                 ;357
0000da  bdf8              POP      {r3-r7,pc}
                  |L7.220|
0000dc  f7fffffe          BL       RTC_WriteEnable
0000e0  6968              LDR      r0,[r5,#0x14]         ;305
0000e2  0840              LSRS     r0,r0,#1              ;305
0000e4  0040              LSLS     r0,r0,#1              ;305
0000e6  6168              STR      r0,[r5,#0x14]         ;305
0000e8  7860              LDRB     r0,[r4,#1]            ;310
0000ea  2802              CMP      r0,#2                 ;310
0000ec  d1a0              BNE      |L7.48|
0000ee  68e0              LDR      r0,[r4,#0xc]          ;311
0000f0  3014              ADDS     r0,r0,#0x14           ;311
0000f2  60e0              STR      r0,[r4,#0xc]          ;311
0000f4  e79c              B        |L7.48|
;;;359    
                          ENDP

0000f6  0000              DCW      0x0000
                  |L7.248|
                          DCD      ||.data||
                  |L7.252|
                          DCD      0x40008000

                          AREA ||i.RTC_Read||, CODE, READONLY, ALIGN=2

                  RTC_Read PROC
;;;391     */
;;;392    int32_t RTC_Read (S_DRVRTC_TIME_DATA_T *sPt)
000000  b510              PUSH     {r4,lr}
;;;393    {
;;;394        uint32_t u32Tmp;
;;;395        
;;;396    	sPt->u8cClockDisplay = RTC->TSSR & RTC_TSSR_24hr;    /* 12/24-hour */
000002  4a39              LDR      r2,|L8.232|
000004  6951              LDR      r1,[r2,#0x14]
000006  07cb              LSLS     r3,r1,#31
000008  0fdb              LSRS     r3,r3,#31
00000a  7003              STRB     r3,[r0,#0]
;;;397        sPt->u32cDayOfWeek   = RTC->DWR & RTC_DWR_DWR;       /* Day of week */
00000c  6991              LDR      r1,[r2,#0x18]
00000e  0749              LSLS     r1,r1,#29
000010  0f49              LSRS     r1,r1,#29
;;;398    
;;;399    	g_u32hiYear  = (RTC->CLR & RTC_CLR_TEN_YEAR) >> 20;
000012  6101              STR      r1,[r0,#0x10]
000014  6911              LDR      r1,[r2,#0x10]
000016  0209              LSLS     r1,r1,#8
000018  0f0c              LSRS     r4,r1,#28
00001a  4934              LDR      r1,|L8.236|
00001c  608c              STR      r4,[r1,#8]  ; g_u32hiYear
;;;400        g_u32loYear  = (RTC->CLR & RTC_CLR_YEAR) >> 16;
00001e  6914              LDR      r4,[r2,#0x10]
000020  0324              LSLS     r4,r4,#12
000022  0f24              LSRS     r4,r4,#28
000024  60cc              STR      r4,[r1,#0xc]  ; g_u32loYear
;;;401        g_u32hiMonth = (RTC->CLR & RTC_CLR_TEN_MON) >> 12;
000026  6914              LDR      r4,[r2,#0x10]
000028  04e4              LSLS     r4,r4,#19
00002a  0fe4              LSRS     r4,r4,#31
00002c  610c              STR      r4,[r1,#0x10]  ; g_u32hiMonth
;;;402        g_u32loMonth = (RTC->CLR & RTC_CLR_MON) >> 8;
00002e  6914              LDR      r4,[r2,#0x10]
000030  0524              LSLS     r4,r4,#20
000032  0f24              LSRS     r4,r4,#28
000034  614c              STR      r4,[r1,#0x14]  ; g_u32loMonth
;;;403        g_u32hiDay   = (RTC->CLR & RTC_CLR_TEN_DAY) >> 4;
000036  6914              LDR      r4,[r2,#0x10]
000038  06a4              LSLS     r4,r4,#26
00003a  0fa4              LSRS     r4,r4,#30
00003c  618c              STR      r4,[r1,#0x18]  ; g_u32hiDay
;;;404        g_u32loDay   = (RTC->CLR & RTC_CLR_DAY);
00003e  6914              LDR      r4,[r2,#0x10]
000040  0724              LSLS     r4,r4,#28
000042  0f24              LSRS     r4,r4,#28
000044  61cc              STR      r4,[r1,#0x1c]  ; g_u32loDay
;;;405    
;;;406    	g_u32hiHour =  (RTC->TLR & RTC_TLR_TEN_HR) >> 20;
000046  68d4              LDR      r4,[r2,#0xc]
000048  02a4              LSLS     r4,r4,#10
00004a  0fa4              LSRS     r4,r4,#30
00004c  620c              STR      r4,[r1,#0x20]  ; g_u32hiHour
;;;407        g_u32loHour =  (RTC->TLR & RTC_TLR_HR) >> 16;
00004e  68d4              LDR      r4,[r2,#0xc]
000050  0324              LSLS     r4,r4,#12
000052  0f24              LSRS     r4,r4,#28
000054  624c              STR      r4,[r1,#0x24]  ; g_u32loHour
;;;408        g_u32hiMin  =  (RTC->TLR & RTC_TLR_TEN_MIN) >> 12;
000056  68d4              LDR      r4,[r2,#0xc]
000058  0464              LSLS     r4,r4,#17
00005a  0f64              LSRS     r4,r4,#29
00005c  628c              STR      r4,[r1,#0x28]  ; g_u32hiMin
;;;409        g_u32loMin  =  (RTC->TLR & RTC_TLR_MIN) >> 8;
00005e  68d4              LDR      r4,[r2,#0xc]
000060  0524              LSLS     r4,r4,#20
000062  0f24              LSRS     r4,r4,#28
000064  62cc              STR      r4,[r1,#0x2c]  ; g_u32loMin
;;;410        g_u32hiSec  =  (RTC->TLR & RTC_TLR_TEN_SEC) >> 4;
000066  68d4              LDR      r4,[r2,#0xc]
000068  0664              LSLS     r4,r4,#25
00006a  0f64              LSRS     r4,r4,#29
00006c  630c              STR      r4,[r1,#0x30]  ; g_u32hiSec
;;;411        g_u32loSec  =  (RTC->TLR & RTC_TLR_SEC);	
00006e  68d2              LDR      r2,[r2,#0xc]
000070  0712              LSLS     r2,r2,#28
000072  0f12              LSRS     r2,r2,#28
000074  634a              STR      r2,[r1,#0x34]  ; g_u32loSec
;;;412    
;;;413        u32Tmp = (g_u32hiYear * 10);									/* Compute to 20XX year */
000076  688a              LDR      r2,[r1,#8]  ; g_u32hiYear
000078  240a              MOVS     r4,#0xa
00007a  4362              MULS     r2,r4,r2
;;;414        u32Tmp+= g_u32loYear;
00007c  68cc              LDR      r4,[r1,#0xc]  ; g_u32loYear
00007e  1912              ADDS     r2,r2,r4
;;;415        sPt->u32Year   =   u32Tmp  + DRVRTC_YEAR2000;
000080  247d              MOVS     r4,#0x7d
000082  0124              LSLS     r4,r4,#4
000084  1912              ADDS     r2,r2,r4
;;;416        
;;;417        u32Tmp = (g_u32hiMonth * 10);									/* Compute 0~12 month */
000086  61c2              STR      r2,[r0,#0x1c]
000088  690a              LDR      r2,[r1,#0x10]  ; g_u32hiMonth
00008a  240a              MOVS     r4,#0xa
00008c  4362              MULS     r2,r4,r2
;;;418        sPt->u32cMonth = u32Tmp + g_u32loMonth;
00008e  694c              LDR      r4,[r1,#0x14]  ; g_u32loMonth
000090  1912              ADDS     r2,r2,r4
;;;419        
;;;420        u32Tmp = (g_u32hiDay * 10);										/* Compute 0~31 day */
000092  6182              STR      r2,[r0,#0x18]
000094  698a              LDR      r2,[r1,#0x18]  ; g_u32hiDay
000096  240a              MOVS     r4,#0xa
000098  4362              MULS     r2,r4,r2
;;;421        sPt->u32cDay   =  u32Tmp  + g_u32loDay;
00009a  69cc              LDR      r4,[r1,#0x1c]  ; g_u32loDay
00009c  1912              ADDS     r2,r2,r4
;;;422    
;;;423        if (sPt->u8cClockDisplay == DRVRTC_CLOCK_12)					/* Compute12/24 hout */
00009e  6142              STR      r2,[r0,#0x14]
;;;424        {
;;;425            u32Tmp = (g_u32hiHour * 10);
;;;426            u32Tmp+= g_u32loHour;
;;;427            sPt->u32cHour = u32Tmp;                                		/* AM: 1~12. PM: 21~32. */
;;;428    
;;;429            if (sPt->u32cHour >= 21)
;;;430            {
;;;431                sPt->u8cAmPm = DRVRTC_PM;
;;;432                sPt->u32cHour -= 20;
;;;433            }
;;;434            else
;;;435            {
;;;436                sPt->u8cAmPm = DRVRTC_AM;
;;;437            }
;;;438            
;;;439            u32Tmp = (g_u32hiMin  * 10);
;;;440            u32Tmp+= g_u32loMin;
;;;441            sPt->u32cMinute = u32Tmp;
;;;442            
;;;443            u32Tmp = (g_u32hiSec  * 10);
;;;444            u32Tmp+= g_u32loSec;
;;;445            sPt->u32cSecond = u32Tmp;
;;;446    
;;;447        }
;;;448        else
;;;449        {   															/* DRVRTC_CLOCK_24 */
;;;450            u32Tmp = (g_u32hiHour * 10);
0000a0  6a0a              LDR      r2,[r1,#0x20]  ; g_u32hiHour
0000a2  2b00              CMP      r3,#0                 ;423
0000a4  d004              BEQ      |L8.176|
0000a6  230a              MOVS     r3,#0xa
0000a8  435a              MULS     r2,r3,r2
;;;451            u32Tmp+= g_u32loHour;
0000aa  6a4b              LDR      r3,[r1,#0x24]  ; g_u32loHour
0000ac  18d2              ADDS     r2,r2,r3
;;;452            sPt->u32cHour   = u32Tmp;
;;;453            
;;;454            u32Tmp = (g_u32hiMin  * 10);
;;;455            u32Tmp+= g_u32loMin;
;;;456            sPt->u32cMinute = u32Tmp;
;;;457            
;;;458            u32Tmp = (g_u32hiSec  * 10);
;;;459            u32Tmp+= g_u32loSec;
;;;460            sPt->u32cSecond = u32Tmp;
0000ae  e009              B        |L8.196|
                  |L8.176|
0000b0  230a              MOVS     r3,#0xa               ;425
0000b2  435a              MULS     r2,r3,r2              ;425
0000b4  6a4b              LDR      r3,[r1,#0x24]         ;426  ; g_u32loHour
0000b6  18d2              ADDS     r2,r2,r3              ;426
0000b8  60c2              STR      r2,[r0,#0xc]          ;429
0000ba  2a15              CMP      r2,#0x15              ;429
0000bc  d304              BCC      |L8.200|
0000be  2302              MOVS     r3,#2                 ;431
0000c0  7043              STRB     r3,[r0,#1]            ;431
0000c2  3a14              SUBS     r2,r2,#0x14           ;432
                  |L8.196|
0000c4  60c2              STR      r2,[r0,#0xc]          ;452
0000c6  e001              B        |L8.204|
                  |L8.200|
0000c8  2201              MOVS     r2,#1                 ;436
0000ca  7042              STRB     r2,[r0,#1]            ;436
                  |L8.204|
0000cc  6a8a              LDR      r2,[r1,#0x28]         ;439  ; g_u32hiMin
0000ce  230a              MOVS     r3,#0xa               ;439
0000d0  435a              MULS     r2,r3,r2              ;439
0000d2  6acb              LDR      r3,[r1,#0x2c]         ;440  ; g_u32loMin
0000d4  18d2              ADDS     r2,r2,r3              ;440
0000d6  6082              STR      r2,[r0,#8]            ;443
0000d8  6b0a              LDR      r2,[r1,#0x30]         ;443  ; g_u32hiSec
0000da  230a              MOVS     r3,#0xa               ;443
0000dc  6b49              LDR      r1,[r1,#0x34]         ;444  ; g_u32loSec
0000de  435a              MULS     r2,r3,r2              ;443
0000e0  1851              ADDS     r1,r2,r1              ;444
;;;461        }
;;;462    
;;;463        return E_SUCCESS;
0000e2  6041              STR      r1,[r0,#4]
0000e4  2000              MOVS     r0,#0
;;;464    
;;;465    }
0000e6  bd10              POP      {r4,pc}
;;;466    
                          ENDP

                  |L8.232|
                          DCD      0x40008000
                  |L8.236|
                          DCD      ||.data||

                          AREA ||i.RTC_ReadAlarm||, CODE, READONLY, ALIGN=2

                  RTC_ReadAlarm PROC
;;;498     */
;;;499    int32_t RTC_ReadAlarm (S_DRVRTC_TIME_DATA_T *sPt)
000000  b510              PUSH     {r4,lr}
;;;500    {
;;;501        uint32_t u32Tmp;
;;;502        
;;;503    	sPt->u8cClockDisplay = RTC->TSSR & RTC_TSSR_24hr;    /* 12/24-hour */
000002  4a39              LDR      r2,|L9.232|
000004  6951              LDR      r1,[r2,#0x14]
000006  07cb              LSLS     r3,r1,#31
000008  0fdb              LSRS     r3,r3,#31
00000a  7003              STRB     r3,[r0,#0]
;;;504        sPt->u32cDayOfWeek   = RTC->DWR & RTC_DWR_DWR;       /* Day of week */
00000c  6991              LDR      r1,[r2,#0x18]
00000e  0749              LSLS     r1,r1,#29
000010  0f49              LSRS     r1,r1,#29
;;;505    
;;;506    	g_u32hiYear  = (RTC->CAR & RTC_CAR_TEN_YEAR) >> 20;
000012  6101              STR      r1,[r0,#0x10]
000014  6a11              LDR      r1,[r2,#0x20]
000016  0209              LSLS     r1,r1,#8
000018  0f0c              LSRS     r4,r1,#28
00001a  4934              LDR      r1,|L9.236|
00001c  608c              STR      r4,[r1,#8]  ; g_u32hiYear
;;;507    	g_u32loYear  = (RTC->CAR & RTC_CAR_YEAR) >> 16;
00001e  6a14              LDR      r4,[r2,#0x20]
000020  0324              LSLS     r4,r4,#12
000022  0f24              LSRS     r4,r4,#28
000024  60cc              STR      r4,[r1,#0xc]  ; g_u32loYear
;;;508    	g_u32hiMonth = (RTC->CAR & RTC_CAR_TEN_MON) >> 12;
000026  6a14              LDR      r4,[r2,#0x20]
000028  04e4              LSLS     r4,r4,#19
00002a  0fe4              LSRS     r4,r4,#31
00002c  610c              STR      r4,[r1,#0x10]  ; g_u32hiMonth
;;;509    	g_u32loMonth = (RTC->CAR & RTC_CAR_MON) >> 8;
00002e  6a14              LDR      r4,[r2,#0x20]
000030  0524              LSLS     r4,r4,#20
000032  0f24              LSRS     r4,r4,#28
000034  614c              STR      r4,[r1,#0x14]  ; g_u32loMonth
;;;510    	g_u32hiDay	 = (RTC->CAR & RTC_CAR_TEN_DAY) >> 4;
000036  6a14              LDR      r4,[r2,#0x20]
000038  06a4              LSLS     r4,r4,#26
00003a  0fa4              LSRS     r4,r4,#30
00003c  618c              STR      r4,[r1,#0x18]  ; g_u32hiDay
;;;511    	g_u32loDay	 = (RTC->CAR & RTC_CAR_DAY);
00003e  6a14              LDR      r4,[r2,#0x20]
000040  0724              LSLS     r4,r4,#28
000042  0f24              LSRS     r4,r4,#28
000044  61cc              STR      r4,[r1,#0x1c]  ; g_u32loDay
;;;512    	
;;;513    	g_u32hiHour =  (RTC->TAR & RTC_TAR_TEN_HR) >> 20;
000046  69d4              LDR      r4,[r2,#0x1c]
000048  02a4              LSLS     r4,r4,#10
00004a  0fa4              LSRS     r4,r4,#30
00004c  620c              STR      r4,[r1,#0x20]  ; g_u32hiHour
;;;514    	g_u32loHour =  (RTC->TAR & RTC_TAR_HR) >> 16;
00004e  69d4              LDR      r4,[r2,#0x1c]
000050  0324              LSLS     r4,r4,#12
000052  0f24              LSRS     r4,r4,#28
000054  624c              STR      r4,[r1,#0x24]  ; g_u32loHour
;;;515    	g_u32hiMin	=  (RTC->TAR & RTC_TAR_TEN_MIN) >> 12;
000056  69d4              LDR      r4,[r2,#0x1c]
000058  0464              LSLS     r4,r4,#17
00005a  0f64              LSRS     r4,r4,#29
00005c  628c              STR      r4,[r1,#0x28]  ; g_u32hiMin
;;;516    	g_u32loMin	=  (RTC->TAR & RTC_TAR_MIN) >> 8;
00005e  69d4              LDR      r4,[r2,#0x1c]
000060  0524              LSLS     r4,r4,#20
000062  0f24              LSRS     r4,r4,#28
000064  62cc              STR      r4,[r1,#0x2c]  ; g_u32loMin
;;;517    	g_u32hiSec	=  (RTC->TAR & RTC_TAR_TEN_SEC) >> 4;
000066  69d4              LDR      r4,[r2,#0x1c]
000068  0664              LSLS     r4,r4,#25
00006a  0f64              LSRS     r4,r4,#29
00006c  630c              STR      r4,[r1,#0x30]  ; g_u32hiSec
;;;518    	g_u32loSec	=  (RTC->TAR & RTC_TAR_SEC);
00006e  69d2              LDR      r2,[r2,#0x1c]
000070  0712              LSLS     r2,r2,#28
000072  0f12              LSRS     r2,r2,#28
000074  634a              STR      r2,[r1,#0x34]  ; g_u32loSec
;;;519    
;;;520        u32Tmp = (g_u32hiYear * 10);									/* Compute to 20XX year */
000076  688a              LDR      r2,[r1,#8]  ; g_u32hiYear
000078  240a              MOVS     r4,#0xa
00007a  4362              MULS     r2,r4,r2
;;;521        u32Tmp+= g_u32loYear;
00007c  68cc              LDR      r4,[r1,#0xc]  ; g_u32loYear
00007e  1912              ADDS     r2,r2,r4
;;;522        sPt->u32Year   =   u32Tmp  + DRVRTC_YEAR2000;
000080  247d              MOVS     r4,#0x7d
000082  0124              LSLS     r4,r4,#4
000084  1912              ADDS     r2,r2,r4
;;;523        
;;;524        u32Tmp = (g_u32hiMonth * 10);									/* Compute 0~12 month */
000086  61c2              STR      r2,[r0,#0x1c]
000088  690a              LDR      r2,[r1,#0x10]  ; g_u32hiMonth
00008a  240a              MOVS     r4,#0xa
00008c  4362              MULS     r2,r4,r2
;;;525        sPt->u32cMonth = u32Tmp + g_u32loMonth;
00008e  694c              LDR      r4,[r1,#0x14]  ; g_u32loMonth
000090  1912              ADDS     r2,r2,r4
;;;526        
;;;527        u32Tmp = (g_u32hiDay * 10);										/* Compute 0~31 day */
000092  6182              STR      r2,[r0,#0x18]
000094  698a              LDR      r2,[r1,#0x18]  ; g_u32hiDay
000096  240a              MOVS     r4,#0xa
000098  4362              MULS     r2,r4,r2
;;;528        sPt->u32cDay   =  u32Tmp  + g_u32loDay;
00009a  69cc              LDR      r4,[r1,#0x1c]  ; g_u32loDay
00009c  1912              ADDS     r2,r2,r4
;;;529    
;;;530        if (sPt->u8cClockDisplay == DRVRTC_CLOCK_12)					/* Compute12/24 hout */
00009e  6142              STR      r2,[r0,#0x14]
;;;531        {
;;;532            u32Tmp = (g_u32hiHour * 10);
;;;533            u32Tmp+= g_u32loHour;
;;;534            sPt->u32cHour = u32Tmp;                                		/* AM: 1~12. PM: 21~32. */
;;;535    
;;;536            if (sPt->u32cHour >= 21)
;;;537            {
;;;538                sPt->u8cAmPm = DRVRTC_PM;
;;;539                sPt->u32cHour -= 20;
;;;540            }
;;;541            else
;;;542            {
;;;543                sPt->u8cAmPm = DRVRTC_AM;
;;;544            }
;;;545            
;;;546            u32Tmp = (g_u32hiMin  * 10);
;;;547            u32Tmp+= g_u32loMin;
;;;548            sPt->u32cMinute = u32Tmp;
;;;549            
;;;550            u32Tmp = (g_u32hiSec  * 10);
;;;551            u32Tmp+= g_u32loSec;
;;;552            sPt->u32cSecond = u32Tmp;
;;;553    
;;;554        }
;;;555        else
;;;556        {   															/* DRVRTC_CLOCK_24 */
;;;557            u32Tmp = (g_u32hiHour * 10);
0000a0  6a0a              LDR      r2,[r1,#0x20]  ; g_u32hiHour
0000a2  2b00              CMP      r3,#0                 ;530
0000a4  d004              BEQ      |L9.176|
0000a6  230a              MOVS     r3,#0xa
0000a8  435a              MULS     r2,r3,r2
;;;558            u32Tmp+= g_u32loHour;
0000aa  6a4b              LDR      r3,[r1,#0x24]  ; g_u32loHour
0000ac  18d2              ADDS     r2,r2,r3
;;;559            sPt->u32cHour   = u32Tmp;
;;;560            
;;;561            u32Tmp = (g_u32hiMin  * 10);
;;;562            u32Tmp+= g_u32loMin;
;;;563            sPt->u32cMinute = u32Tmp;
;;;564            
;;;565            u32Tmp = (g_u32hiSec  * 10);
;;;566            u32Tmp+= g_u32loSec;
;;;567            sPt->u32cSecond = u32Tmp;
0000ae  e009              B        |L9.196|
                  |L9.176|
0000b0  230a              MOVS     r3,#0xa               ;532
0000b2  435a              MULS     r2,r3,r2              ;532
0000b4  6a4b              LDR      r3,[r1,#0x24]         ;533  ; g_u32loHour
0000b6  18d2              ADDS     r2,r2,r3              ;533
0000b8  60c2              STR      r2,[r0,#0xc]          ;536
0000ba  2a15              CMP      r2,#0x15              ;536
0000bc  d304              BCC      |L9.200|
0000be  2302              MOVS     r3,#2                 ;538
0000c0  7043              STRB     r3,[r0,#1]            ;538
0000c2  3a14              SUBS     r2,r2,#0x14           ;539
                  |L9.196|
0000c4  60c2              STR      r2,[r0,#0xc]          ;559
0000c6  e001              B        |L9.204|
                  |L9.200|
0000c8  2201              MOVS     r2,#1                 ;543
0000ca  7042              STRB     r2,[r0,#1]            ;543
                  |L9.204|
0000cc  6a8a              LDR      r2,[r1,#0x28]         ;546  ; g_u32hiMin
0000ce  230a              MOVS     r3,#0xa               ;546
0000d0  435a              MULS     r2,r3,r2              ;546
0000d2  6acb              LDR      r3,[r1,#0x2c]         ;547  ; g_u32loMin
0000d4  18d2              ADDS     r2,r2,r3              ;547
0000d6  6082              STR      r2,[r0,#8]            ;550
0000d8  6b0a              LDR      r2,[r1,#0x30]         ;550  ; g_u32hiSec
0000da  230a              MOVS     r3,#0xa               ;550
0000dc  6b49              LDR      r1,[r1,#0x34]         ;551  ; g_u32loSec
0000de  435a              MULS     r2,r3,r2              ;550
0000e0  1851              ADDS     r1,r2,r1              ;551
;;;568        }
;;;569    
;;;570        return E_SUCCESS;
0000e2  6041              STR      r1,[r0,#4]
0000e4  2000              MOVS     r0,#0
;;;571    
;;;572    }
0000e6  bd10              POP      {r4,pc}
;;;573    
                          ENDP

                  |L9.232|
                          DCD      0x40008000
                  |L9.236|
                          DCD      ||.data||

                          AREA ||i.RTC_SetFrequencyCompensation||, CODE, READONLY, ALIGN=2

                  RTC_SetFrequencyCompensation PROC
;;;70      */
;;;71     int32_t RTC_SetFrequencyCompensation(int32_t i32FrequencyX100)
000000  b570              PUSH     {r4-r6,lr}
;;;72     {
;;;73         int32_t i32RegInt,i32RegFra ;
;;;74     
;;;75     	/* Compute Interger and Fraction for RTC register*/
;;;76         i32RegInt = (i32FrequencyX100/100) - DRVRTC_FCR_REFERENCE;
000002  2164              MOVS     r1,#0x64
000004  f7fffffe          BL       __aeabi_idivmod
000008  4a0c              LDR      r2,|L10.60|
00000a  1884              ADDS     r4,r0,r2
;;;77         i32RegFra = (((i32FrequencyX100%100)) * 60) / 100;
00000c  203c              MOVS     r0,#0x3c
00000e  4348              MULS     r0,r1,r0
000010  2164              MOVS     r1,#0x64
000012  f7fffffe          BL       __aeabi_idivmod
000016  4605              MOV      r5,r0
;;;78         
;;;79     	/* Judge Interger part is reasonable */
;;;80         if ( (i32RegInt < 0) | (i32RegInt > 15) )
000018  0fe0              LSRS     r0,r4,#31
00001a  2c0f              CMP      r4,#0xf
00001c  dd01              BLE      |L10.34|
00001e  2101              MOVS     r1,#1
000020  e000              B        |L10.36|
                  |L10.34|
000022  2100              MOVS     r1,#0
                  |L10.36|
000024  4308              ORRS     r0,r0,r1
000026  d001              BEQ      |L10.44|
;;;81         {
;;;82             return E_DRVRTC_ERR_FCR_VALUE ;
000028  2005              MOVS     r0,#5
;;;83         }
;;;84     	
;;;85     	RTC_WriteEnable();
;;;86     
;;;87     	RTC->FCR = (uint32_t)((i32RegInt<<8) | i32RegFra);
;;;88     
;;;89         return E_SUCCESS;
;;;90     }
00002a  bd70              POP      {r4-r6,pc}
                  |L10.44|
00002c  f7fffffe          BL       RTC_WriteEnable
000030  0220              LSLS     r0,r4,#8              ;87
000032  4903              LDR      r1,|L10.64|
000034  4328              ORRS     r0,r0,r5              ;87
000036  6088              STR      r0,[r1,#8]            ;87
000038  2000              MOVS     r0,#0                 ;89
00003a  bd70              POP      {r4-r6,pc}
;;;91     
                          ENDP

                  |L10.60|
                          DCD      0xffff8007
                  |L10.64|
                          DCD      0x40008000

                          AREA ||i.RTC_SetTickMode||, CODE, READONLY, ALIGN=2

                  RTC_SetTickMode PROC
;;;995     */
;;;996    int32_t RTC_SetTickMode(uint8_t ucMode)
000000  b510              PUSH     {r4,lr}
;;;997    {
000002  4604              MOV      r4,r0
;;;998    
;;;999        if (RTC_WriteEnable() != 0)   				/* Write PASSWORD to access enable*/
000004  f7fffffe          BL       RTC_WriteEnable
000008  2800              CMP      r0,#0
00000a  d001              BEQ      |L11.16|
;;;1000       {
;;;1001       	return E_DRVRTC_ERR_EIO ;
00000c  2006              MOVS     r0,#6
;;;1002       }
;;;1003       
;;;1004   	if (ucMode > DRVRTC_TICK_1_128_SEC)             /* Tick mode 0 to 7 */
;;;1005       {
;;;1006       	return E_DRVRTC_ERR_ENOTTY ;
;;;1007       }
;;;1008               
;;;1009   	RTC->TTR = RTC->TTR & ~RTC_TTR_TTR | ucMode;
;;;1010   
;;;1011   	return E_SUCCESS;
;;;1012   
;;;1013   }
00000e  bd10              POP      {r4,pc}
                  |L11.16|
000010  2c07              CMP      r4,#7                 ;1004
000012  d901              BLS      |L11.24|
000014  2007              MOVS     r0,#7                 ;1006
000016  bd10              POP      {r4,pc}
                  |L11.24|
000018  4803              LDR      r0,|L11.40|
00001a  6b01              LDR      r1,[r0,#0x30]         ;1009
00001c  08c9              LSRS     r1,r1,#3              ;1009
00001e  00c9              LSLS     r1,r1,#3              ;1009
000020  4321              ORRS     r1,r1,r4              ;1009
000022  6301              STR      r1,[r0,#0x30]         ;1009
000024  2000              MOVS     r0,#0                 ;1011
000026  bd10              POP      {r4,pc}
;;;1014   
                          ENDP

                  |L11.40|
                          DCD      0x40008000

                          AREA ||i.RTC_SpareRegsAccess||, CODE, READONLY, ALIGN=2

                  RTC_SpareRegsAccess PROC
;;;842     */
;;;843    int32_t RTC_SpareRegsAccess (int32_t sparenum, int32_t value, int32_t wrsel)
000000  b5f0              PUSH     {r4-r7,lr}
;;;844    {
000002  4606              MOV      r6,r0
000004  460f              MOV      r7,r1
000006  4614              MOV      r4,r2
;;;845    	uint32_t ret = E_SUCCESS;
000008  2500              MOVS     r5,#0
;;;846    
;;;847    	RTC_WriteEnable();
00000a  f7fffffe          BL       RTC_WriteEnable
;;;848    
;;;849    	if(wrsel==0)
;;;850    		while((RTC->SPRCTL & RTC_SPRCTL_SPRRDY) == 0);
00000e  494e              LDR      r1,|L12.328|
000010  2c00              CMP      r4,#0                 ;849
000012  d102              BNE      |L12.26|
                  |L12.20|
000014  6bc8              LDR      r0,[r1,#0x3c]
000016  0600              LSLS     r0,r0,#24
000018  d5fc              BPL      |L12.20|
                  |L12.26|
;;;851    	
;;;852    	if(sparenum==0)
;;;853    		(wrsel==1) ? (RTC->SPR0=value) : (ret=RTC->SPR0);
00001a  484b              LDR      r0,|L12.328|
00001c  3040              ADDS     r0,r0,#0x40
00001e  2e00              CMP      r6,#0                 ;852
000020  d02a              BEQ      |L12.120|
;;;854    	if(sparenum==1)
000022  2e01              CMP      r6,#1
000024  d072              BEQ      |L12.268|
;;;855    		(wrsel==1) ? (RTC->SPR1=value) : (ret=RTC->SPR1);
;;;856    	if(sparenum==2)
000026  2e02              CMP      r6,#2
000028  d02e              BEQ      |L12.136|
;;;857    		(wrsel==1) ? (RTC->SPR2=value) : (ret=RTC->SPR2);
;;;858    	if(sparenum==3)
00002a  2e03              CMP      r6,#3
00002c  d06f              BEQ      |L12.270|
;;;859    		(wrsel==1) ? (RTC->SPR3=value) : (ret=RTC->SPR3);
;;;860    	if(sparenum==4)
00002e  2e04              CMP      r6,#4
000030  d032              BEQ      |L12.152|
;;;861    		(wrsel==1) ? (RTC->SPR4=value) : (ret=RTC->SPR4);
;;;862    	if(sparenum==5)
000032  2e05              CMP      r6,#5
000034  d036              BEQ      |L12.164|
;;;863    		(wrsel==1) ? (RTC->SPR5=value) : (ret=RTC->SPR5);
;;;864    	if(sparenum==6)
000036  2e06              CMP      r6,#6
000038  d03a              BEQ      |L12.176|
;;;865    		(wrsel==1) ? (RTC->SPR6=value) : (ret=RTC->SPR6);
;;;866    	if(sparenum==7)
00003a  2e07              CMP      r6,#7
00003c  d03e              BEQ      |L12.188|
;;;867    		(wrsel==1) ? (RTC->SPR7=value) : (ret=RTC->SPR7);
;;;868    	if(sparenum==8)
00003e  2e08              CMP      r6,#8
000040  d042              BEQ      |L12.200|
;;;869    		(wrsel==1) ? (RTC->SPR8=value) : (ret=RTC->SPR8);
;;;870    	if(sparenum==9)
000042  2e09              CMP      r6,#9
000044  d046              BEQ      |L12.212|
;;;871    		(wrsel==1) ? (RTC->SPR9=value) : (ret=RTC->SPR9);
;;;872    	if(sparenum==10)
000046  2e0a              CMP      r6,#0xa
000048  d04a              BEQ      |L12.224|
;;;873    		(wrsel==1) ? (RTC->SPR10=value) : (ret=RTC->SPR10);
;;;874    	if(sparenum==11)
00004a  2e0b              CMP      r6,#0xb
00004c  d04e              BEQ      |L12.236|
;;;875    		(wrsel==1) ? (RTC->SPR11=value) : (ret=RTC->SPR11);
;;;876    	if(sparenum==12)
00004e  2e0c              CMP      r6,#0xc
000050  d052              BEQ      |L12.248|
;;;877    		(wrsel==1) ? (RTC->SPR12=value) : (ret=RTC->SPR12);
;;;878    	if(sparenum==13)
000052  2e0d              CMP      r6,#0xd
000054  d056              BEQ      |L12.260|
;;;879    		(wrsel==1) ? (RTC->SPR13=value) : (ret=RTC->SPR13);
;;;880    	if(sparenum==14)
000056  2e0e              CMP      r6,#0xe
000058  d05c              BEQ      |L12.276|
;;;881    		(wrsel==1) ? (RTC->SPR14=value) : (ret=RTC->SPR14);
;;;882    	if(sparenum==15)
00005a  2e0f              CMP      r6,#0xf
00005c  d060              BEQ      |L12.288|
;;;883    		(wrsel==1) ? (RTC->SPR15=value) : (ret=RTC->SPR15);
;;;884    	if(sparenum==16)
;;;885    		(wrsel==1) ? (RTC->SPR16=value) : (ret=RTC->SPR16);
00005e  483a              LDR      r0,|L12.328|
000060  3080              ADDS     r0,r0,#0x80
000062  2e10              CMP      r6,#0x10              ;884
000064  d008              BEQ      |L12.120|
;;;886    	if(sparenum==17)
000066  2e11              CMP      r6,#0x11
000068  d062              BEQ      |L12.304|
;;;887    		(wrsel==1) ? (RTC->SPR17=value) : (ret=RTC->SPR17);
;;;888    	if(sparenum==18)
00006a  2e12              CMP      r6,#0x12
00006c  d00c              BEQ      |L12.136|
;;;889    		(wrsel==1) ? (RTC->SPR18=value) : (ret=RTC->SPR18);
;;;890    	if(sparenum==19)
00006e  2e13              CMP      r6,#0x13
000070  d067              BEQ      |L12.322|
;;;891    		(wrsel==1) ? (RTC->SPR19=value) : (ret=RTC->SPR19);
;;;892    
;;;893    	if(wrsel==1)
000072  2c01              CMP      r4,#1
000074  d060              BEQ      |L12.312|
000076  e062              B        |L12.318|
                  |L12.120|
000078  2c01              CMP      r4,#1                 ;853
00007a  d057              BEQ      |L12.300|
00007c  6805              LDR      r5,[r0,#0]            ;885
00007e  e05e              B        |L12.318|
                  |L12.128|
000080  6047              STR      r7,[r0,#4]            ;855
000082  e059              B        |L12.312|
                  |L12.132|
000084  6845              LDR      r5,[r0,#4]            ;855
000086  e05a              B        |L12.318|
                  |L12.136|
000088  2c01              CMP      r4,#1                 ;857
00008a  d054              BEQ      |L12.310|
00008c  6885              LDR      r5,[r0,#8]            ;889
00008e  e056              B        |L12.318|
                  |L12.144|
000090  60c7              STR      r7,[r0,#0xc]          ;859
000092  e051              B        |L12.312|
                  |L12.148|
000094  68c5              LDR      r5,[r0,#0xc]          ;859
000096  e052              B        |L12.318|
                  |L12.152|
000098  2c01              CMP      r4,#1                 ;861
00009a  d001              BEQ      |L12.160|
00009c  6905              LDR      r5,[r0,#0x10]         ;861
00009e  e04e              B        |L12.318|
                  |L12.160|
0000a0  6107              STR      r7,[r0,#0x10]         ;861
0000a2  e049              B        |L12.312|
                  |L12.164|
0000a4  2c01              CMP      r4,#1                 ;863
0000a6  d001              BEQ      |L12.172|
0000a8  6945              LDR      r5,[r0,#0x14]         ;863
0000aa  e048              B        |L12.318|
                  |L12.172|
0000ac  6147              STR      r7,[r0,#0x14]         ;863
0000ae  e043              B        |L12.312|
                  |L12.176|
0000b0  2c01              CMP      r4,#1                 ;865
0000b2  d001              BEQ      |L12.184|
0000b4  6985              LDR      r5,[r0,#0x18]         ;865
0000b6  e042              B        |L12.318|
                  |L12.184|
0000b8  6187              STR      r7,[r0,#0x18]         ;865
0000ba  e03d              B        |L12.312|
                  |L12.188|
0000bc  2c01              CMP      r4,#1                 ;867
0000be  d001              BEQ      |L12.196|
0000c0  69c5              LDR      r5,[r0,#0x1c]         ;867
0000c2  e03c              B        |L12.318|
                  |L12.196|
0000c4  61c7              STR      r7,[r0,#0x1c]         ;867
0000c6  e037              B        |L12.312|
                  |L12.200|
0000c8  2c01              CMP      r4,#1                 ;869
0000ca  d001              BEQ      |L12.208|
0000cc  6a05              LDR      r5,[r0,#0x20]         ;869
0000ce  e036              B        |L12.318|
                  |L12.208|
0000d0  6207              STR      r7,[r0,#0x20]         ;869
0000d2  e031              B        |L12.312|
                  |L12.212|
0000d4  2c01              CMP      r4,#1                 ;871
0000d6  d001              BEQ      |L12.220|
0000d8  6a45              LDR      r5,[r0,#0x24]         ;871
0000da  e030              B        |L12.318|
                  |L12.220|
0000dc  6247              STR      r7,[r0,#0x24]         ;871
0000de  e02b              B        |L12.312|
                  |L12.224|
0000e0  2c01              CMP      r4,#1                 ;873
0000e2  d001              BEQ      |L12.232|
0000e4  6a85              LDR      r5,[r0,#0x28]         ;873
0000e6  e02a              B        |L12.318|
                  |L12.232|
0000e8  6287              STR      r7,[r0,#0x28]         ;873
0000ea  e025              B        |L12.312|
                  |L12.236|
0000ec  2c01              CMP      r4,#1                 ;875
0000ee  d001              BEQ      |L12.244|
0000f0  6ac5              LDR      r5,[r0,#0x2c]         ;875
0000f2  e024              B        |L12.318|
                  |L12.244|
0000f4  62c7              STR      r7,[r0,#0x2c]         ;875
0000f6  e01f              B        |L12.312|
                  |L12.248|
0000f8  2c01              CMP      r4,#1                 ;877
0000fa  d001              BEQ      |L12.256|
0000fc  6b05              LDR      r5,[r0,#0x30]         ;877
0000fe  e01e              B        |L12.318|
                  |L12.256|
000100  6307              STR      r7,[r0,#0x30]         ;877
000102  e019              B        |L12.312|
                  |L12.260|
000104  2c01              CMP      r4,#1                 ;879
000106  d003              BEQ      |L12.272|
000108  6b45              LDR      r5,[r0,#0x34]         ;879
00010a  e018              B        |L12.318|
                  |L12.268|
00010c  e010              B        |L12.304|
                  |L12.270|
00010e  e018              B        |L12.322|
                  |L12.272|
000110  6347              STR      r7,[r0,#0x34]         ;879
000112  e011              B        |L12.312|
                  |L12.276|
000114  2c01              CMP      r4,#1                 ;881
000116  d001              BEQ      |L12.284|
000118  6b85              LDR      r5,[r0,#0x38]         ;881
00011a  e010              B        |L12.318|
                  |L12.284|
00011c  6387              STR      r7,[r0,#0x38]         ;881
00011e  e00b              B        |L12.312|
                  |L12.288|
000120  2c01              CMP      r4,#1                 ;883
000122  d001              BEQ      |L12.296|
000124  6bc5              LDR      r5,[r0,#0x3c]         ;883
000126  e00a              B        |L12.318|
                  |L12.296|
000128  63c7              STR      r7,[r0,#0x3c]         ;883
00012a  e005              B        |L12.312|
                  |L12.300|
00012c  6007              STR      r7,[r0,#0]            ;885
00012e  e003              B        |L12.312|
                  |L12.304|
000130  2c01              CMP      r4,#1                 ;887
000132  d1a7              BNE      |L12.132|
000134  e7a4              B        |L12.128|
                  |L12.310|
000136  6087              STR      r7,[r0,#8]            ;889
                  |L12.312|
;;;894    		while((RTC->SPRCTL & RTC_SPRCTL_SPRRDY) == 0);
000138  6bc8              LDR      r0,[r1,#0x3c]
00013a  0600              LSLS     r0,r0,#24
00013c  d5fc              BPL      |L12.312|
                  |L12.318|
;;;895    	
;;;896    	return ret;
00013e  4628              MOV      r0,r5
;;;897    
;;;898    }
000140  bdf0              POP      {r4-r7,pc}
                  |L12.322|
000142  2c01              CMP      r4,#1                 ;891
000144  d1a6              BNE      |L12.148|
000146  e7a3              B        |L12.144|
;;;899    
                          ENDP

                  |L12.328|
                          DCD      0x40008000

                          AREA ||i.RTC_Write||, CODE, READONLY, ALIGN=2

                  RTC_Write PROC
;;;608     */
;;;609    int32_t RTC_Write(S_DRVRTC_TIME_DATA_T *sPt)
000000  b5f8              PUSH     {r3-r7,lr}
;;;610    {
000002  4604              MOV      r4,r0
;;;611        uint32_t u32Reg;
;;;612        /*-----------------------------------------------------------------------------------------------------*/
;;;613        /* Check RTC time data value is reasonable or not.                                                     */
;;;614        /*-----------------------------------------------------------------------------------------------------*/
;;;615    	assert_param(	!( ((sPt->u32Year - DRVRTC_YEAR2000) > 99)|
;;;616    							((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12))|
;;;617    							((sPt->u32cDay   == 0) || (sPt->u32cDay   > 31))));
;;;618    
;;;619    	assert_param( !( (sPt->u32cMonth == 0) || (sPt->u32cMonth > 12) ));
;;;620        
;;;621    	assert_param( !( (sPt->u32cDay == 0) || (sPt->u32cDay > 31) ));
;;;622    
;;;623    	assert_param( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) || (sPt->u8cClockDisplay==DRVRTC_CLOCK_24));
;;;624    
;;;625    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) &&
;;;626    							((sPt->u32cHour == 0) || (sPt->u32cHour > 12))));
;;;627    
;;;628    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_24) &&
;;;629    							(sPt->u32cHour > 23)));
;;;630    
;;;631    	assert_param( !(sPt->u32cMinute > 59));
;;;632    	assert_param( !(sPt->u32cSecond > 59));
;;;633    	assert_param( !(sPt->u32cDayOfWeek > 6));
;;;634    
;;;635    
;;;636        /*-----------------------------------------------------------------------------------------------------*/
;;;637        /* Important, call DrvRTC_Open() before write data into any register.                                     */
;;;638        /*-----------------------------------------------------------------------------------------------------*/
;;;639        g_u32Reg = RTC_WriteEnable();
000004  f7fffffe          BL       RTC_WriteEnable
000008  4d2d              LDR      r5,|L13.192|
00000a  6068              STR      r0,[r5,#4]  ; g_u32Reg
;;;640        if (g_u32Reg != 0)
00000c  6868              LDR      r0,[r5,#4]  ; g_u32Reg
00000e  2800              CMP      r0,#0
000010  d001              BEQ      |L13.22|
;;;641        {
;;;642            return E_DRVRTC_ERR_FAILED;
000012  2009              MOVS     r0,#9
;;;643        }
;;;644    
;;;645    	/*---------------------------------------------------------------------------------------------*/
;;;646        /* Second, set RTC time data.                                                                  */
;;;647        /*---------------------------------------------------------------------------------------------*/
;;;648    
;;;649        if (sPt->u8cClockDisplay == DRVRTC_CLOCK_12)
;;;650        {
;;;651        	g_chHourMode = DRVRTC_CLOCK_12;
;;;652    		RTC->TSSR &= ~RTC_TSSR_24hr;
;;;653            RTCDEBUG ("RTC: 12-hour\n");
;;;654            /*-----------------------------------------------------------------------------------------*/
;;;655            /* important, range of 12-hour PM mode is 21 upto 32                                       */
;;;656            /*-----------------------------------------------------------------------------------------*/
;;;657            if (sPt->u8cAmPm == DRVRTC_PM)
;;;658            	sPt->u32cHour += 20;
;;;659        }
;;;660        else                                                                  /* DRVRTC_CLOCK_24 */
;;;661        {
;;;662        	g_chHourMode = DRVRTC_CLOCK_24;
;;;663    		RTC->TSSR |= RTC_TSSR_24hr;
;;;664            RTCDEBUG ("RTC: 24-hour\n");
;;;665        }
;;;666    
;;;667    	RTC->DWR = sPt->u32cDayOfWeek & RTC_DWR_DWR;
;;;668    		    
;;;669    	/*---------------------------------------------------------------------------------------------*/
;;;670        /* Second, set RTC time data.                                                                  */
;;;671        /*---------------------------------------------------------------------------------------------*/
;;;672    
;;;673    	u32Reg     = ((sPt->u32Year - DRVRTC_YEAR2000) / 10) << 20;
;;;674    	u32Reg    |= (((sPt->u32Year - DRVRTC_YEAR2000) % 10) << 16);
;;;675    	u32Reg    |= ((sPt->u32cMonth  / 10) << 12);
;;;676    	u32Reg    |= ((sPt->u32cMonth  % 10) << 8);
;;;677    	u32Reg    |= ((sPt->u32cDay    / 10) << 4);
;;;678    	u32Reg    |= (sPt->u32cDay     % 10);
;;;679        g_u32Reg = u32Reg;
;;;680    	RTC_WriteEnable();
;;;681              
;;;682    	RTC->CLR = (uint32_t)g_u32Reg;
;;;683    	RTCDEBUG ("RTC: REG_RTC_CLR[0x%08x]\n", RTC->CLR);  
;;;684                
;;;685    	u32Reg     = ((sPt->u32cHour / 10) << 20);
;;;686    	u32Reg    |= ((sPt->u32cHour % 10) << 16);
;;;687    	u32Reg    |= ((sPt->u32cMinute / 10) << 12);
;;;688    	u32Reg    |= ((sPt->u32cMinute % 10) << 8);
;;;689    	u32Reg    |= ((sPt->u32cSecond / 10) << 4);
;;;690    	u32Reg    |= (sPt->u32cSecond % 10);
;;;691    	g_u32Reg = u32Reg;
;;;692    		
;;;693    	RTC_WriteEnable();
;;;694        RTC->TLR = (uint32_t)g_u32Reg;
;;;695    	RTCDEBUG ("RTC: REG_RTC_TLR[0x%08x]\n", RTC->TLR);   
;;;696    			
;;;697        return E_SUCCESS;	
;;;698    
;;;699    }
000014  bdf8              POP      {r3-r7,pc}
                  |L13.22|
000016  7820              LDRB     r0,[r4,#0]            ;649
000018  4e2a              LDR      r6,|L13.196|
00001a  2800              CMP      r0,#0                 ;649
00001c  d043              BEQ      |L13.166|
00001e  2001              MOVS     r0,#1                 ;662
000020  7028              STRB     r0,[r5,#0]            ;662
000022  6971              LDR      r1,[r6,#0x14]         ;663
000024  4301              ORRS     r1,r1,r0              ;663
000026  6171              STR      r1,[r6,#0x14]         ;663
                  |L13.40|
000028  6920              LDR      r0,[r4,#0x10]         ;667
00002a  0740              LSLS     r0,r0,#29             ;667
00002c  0f40              LSRS     r0,r0,#29             ;667
00002e  61b0              STR      r0,[r6,#0x18]         ;667
000030  207d              MOVS     r0,#0x7d              ;673
000032  69e1              LDR      r1,[r4,#0x1c]         ;673
000034  0100              LSLS     r0,r0,#4              ;673
000036  1a08              SUBS     r0,r1,r0              ;673
000038  210a              MOVS     r1,#0xa               ;673
00003a  f7fffffe          BL       __aeabi_uidivmod
00003e  040f              LSLS     r7,r1,#16             ;674
000040  0500              LSLS     r0,r0,#20             ;673
000042  4307              ORRS     r7,r7,r0              ;674
000044  210a              MOVS     r1,#0xa               ;675
000046  69a0              LDR      r0,[r4,#0x18]         ;675
000048  f7fffffe          BL       __aeabi_uidivmod
00004c  0300              LSLS     r0,r0,#12             ;675
00004e  4338              ORRS     r0,r0,r7              ;675
000050  020f              LSLS     r7,r1,#8              ;676
000052  4307              ORRS     r7,r7,r0              ;676
000054  210a              MOVS     r1,#0xa               ;677
000056  6960              LDR      r0,[r4,#0x14]         ;677
000058  f7fffffe          BL       __aeabi_uidivmod
00005c  0100              LSLS     r0,r0,#4              ;677
00005e  4338              ORRS     r0,r0,r7              ;677
000060  4301              ORRS     r1,r1,r0              ;678
000062  6069              STR      r1,[r5,#4]            ;679  ; g_u32Reg
000064  f7fffffe          BL       RTC_WriteEnable
000068  6868              LDR      r0,[r5,#4]            ;682  ; g_u32Reg
00006a  6130              STR      r0,[r6,#0x10]         ;682
00006c  210a              MOVS     r1,#0xa               ;685
00006e  68e0              LDR      r0,[r4,#0xc]          ;685
000070  f7fffffe          BL       __aeabi_uidivmod
000074  040f              LSLS     r7,r1,#16             ;686
000076  0500              LSLS     r0,r0,#20             ;685
000078  4307              ORRS     r7,r7,r0              ;686
00007a  210a              MOVS     r1,#0xa               ;687
00007c  68a0              LDR      r0,[r4,#8]            ;687
00007e  f7fffffe          BL       __aeabi_uidivmod
000082  0300              LSLS     r0,r0,#12             ;687
000084  4338              ORRS     r0,r0,r7              ;687
000086  020f              LSLS     r7,r1,#8              ;688
000088  4307              ORRS     r7,r7,r0              ;688
00008a  210a              MOVS     r1,#0xa               ;689
00008c  6860              LDR      r0,[r4,#4]            ;689
00008e  f7fffffe          BL       __aeabi_uidivmod
000092  0100              LSLS     r0,r0,#4              ;689
000094  4338              ORRS     r0,r0,r7              ;689
000096  4301              ORRS     r1,r1,r0              ;690
000098  6069              STR      r1,[r5,#4]            ;691  ; g_u32Reg
00009a  f7fffffe          BL       RTC_WriteEnable
00009e  6868              LDR      r0,[r5,#4]            ;694  ; g_u32Reg
0000a0  60f0              STR      r0,[r6,#0xc]          ;694
0000a2  2000              MOVS     r0,#0                 ;697
0000a4  bdf8              POP      {r3-r7,pc}
                  |L13.166|
0000a6  2000              MOVS     r0,#0                 ;651
0000a8  7028              STRB     r0,[r5,#0]            ;651
0000aa  6970              LDR      r0,[r6,#0x14]         ;652
0000ac  0840              LSRS     r0,r0,#1              ;652
0000ae  0040              LSLS     r0,r0,#1              ;652
0000b0  6170              STR      r0,[r6,#0x14]         ;652
0000b2  7860              LDRB     r0,[r4,#1]            ;657
0000b4  2802              CMP      r0,#2                 ;657
0000b6  d1b7              BNE      |L13.40|
0000b8  68e0              LDR      r0,[r4,#0xc]          ;658
0000ba  3014              ADDS     r0,r0,#0x14           ;658
0000bc  60e0              STR      r0,[r4,#0xc]          ;658
0000be  e7b3              B        |L13.40|
;;;700    
                          ENDP

                  |L13.192|
                          DCD      ||.data||
                  |L13.196|
                          DCD      0x40008000

                          AREA ||i.RTC_WriteAlarm||, CODE, READONLY, ALIGN=2

                  RTC_WriteAlarm PROC
;;;734     */
;;;735    int32_t RTC_WriteAlarm(S_DRVRTC_TIME_DATA_T *sPt)
000000  b5f8              PUSH     {r3-r7,lr}
;;;736    //int32_t RTC_Write(E_DRVRTC_TIME_SELECT eTime, S_DRVRTC_TIME_DATA_T *sPt)
;;;737    {
000002  4604              MOV      r4,r0
;;;738        uint32_t u32Reg;
;;;739        /*-----------------------------------------------------------------------------------------------------*/
;;;740        /* Check RTC time data value is reasonable or not.                                                     */
;;;741        /*-----------------------------------------------------------------------------------------------------*/
;;;742    	assert_param(	!( ((sPt->u32Year - DRVRTC_YEAR2000) > 99)|
;;;743    							((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12))|
;;;744    							((sPt->u32cDay   == 0) || (sPt->u32cDay   > 31))));
;;;745    
;;;746    	assert_param( !( (sPt->u32cMonth == 0) || (sPt->u32cMonth > 12) ));
;;;747        
;;;748    	assert_param( !( (sPt->u32cDay == 0) || (sPt->u32cDay > 31) ));
;;;749    
;;;750    	assert_param( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) || (sPt->u8cClockDisplay==DRVRTC_CLOCK_24));
;;;751    
;;;752    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) &&
;;;753    							((sPt->u32cHour == 0) || (sPt->u32cHour > 12))));
;;;754    
;;;755    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_24) &&
;;;756    							(sPt->u32cHour > 23)));
;;;757    
;;;758    	assert_param( !(sPt->u32cMinute > 59));
;;;759    	assert_param( !(sPt->u32cSecond > 59));
;;;760    	assert_param( !(sPt->u32cDayOfWeek > 6));
;;;761    
;;;762    
;;;763        /*-----------------------------------------------------------------------------------------------------*/
;;;764        /* Important, call DrvRTC_Open() before write data into any register.                                     */
;;;765        /*-----------------------------------------------------------------------------------------------------*/
;;;766        g_u32Reg = RTC_WriteEnable();
000004  f7fffffe          BL       RTC_WriteEnable
000008  4e2d              LDR      r6,|L14.192|
00000a  6070              STR      r0,[r6,#4]  ; g_u32Reg
;;;767        if (g_u32Reg != 0)
00000c  6870              LDR      r0,[r6,#4]  ; g_u32Reg
00000e  2800              CMP      r0,#0
000010  d001              BEQ      |L14.22|
;;;768        {
;;;769            return E_DRVRTC_ERR_FAILED;
000012  2009              MOVS     r0,#9
;;;770        }
;;;771    
;;;772    	/*---------------------------------------------------------------------------------------------*/
;;;773        /* Set Calender alarm time data.                                                               */
;;;774        /*---------------------------------------------------------------------------------------------*/
;;;775    	u32Reg     = ((sPt->u32Year - DRVRTC_YEAR2000) / 10) << 20;
;;;776    	u32Reg    |= (((sPt->u32Year - DRVRTC_YEAR2000) % 10) << 16);
;;;777    	u32Reg    |= ((sPt->u32cMonth  / 10) << 12);
;;;778    	u32Reg    |= ((sPt->u32cMonth  % 10) << 8);
;;;779    	u32Reg    |= ((sPt->u32cDay    / 10) << 4);
;;;780    	u32Reg    |= (sPt->u32cDay     % 10);
;;;781        g_u32Reg = u32Reg;
;;;782    	RTC_WriteEnable();
;;;783    			
;;;784    	RTC->CAR = (uint32_t)g_u32Reg;
;;;785    	RTCDEBUG ("RTC: REG_RTC_CAR[0x%08x]\n", RTC->CAR);  
;;;786    			
;;;787    						 
;;;788        if (g_chHourMode == DRVRTC_CLOCK_12)
;;;789        {
;;;790        	if (sPt->u8cAmPm == DRVRTC_PM)       /* important, range of 12-hour PM mode is 21 upto 32 */
;;;791            	sPt->u32cHour += 20;
;;;792        }
;;;793    
;;;794    	/*---------------------------------------------------------------------------------------------*/
;;;795        /* Set Time alarm time data.                                                                   */
;;;796        /*---------------------------------------------------------------------------------------------*/
;;;797    	u32Reg     = ((sPt->u32cHour / 10) << 20);
;;;798    	u32Reg    |= ((sPt->u32cHour % 10) << 16);
;;;799    	u32Reg    |= ((sPt->u32cMinute / 10) << 12);
;;;800    	u32Reg    |= ((sPt->u32cMinute % 10) << 8);
;;;801    	u32Reg    |= ((sPt->u32cSecond / 10) << 4);
;;;802    	u32Reg    |= (sPt->u32cSecond % 10);
;;;803    
;;;804    	g_u32Reg = u32Reg;
;;;805        RTC_WriteEnable();
;;;806        RTC->TAR = (uint32_t)g_u32Reg;
;;;807    	RTCDEBUG ("RTC: REG_RTC_TAR[0x%08x]\n", RTC->TAR);   
;;;808    
;;;809    	/*---------------------------------------------------------------------------------------------*/
;;;810        /* Finally, enable alarm interrupt.                                                            */
;;;811        /*---------------------------------------------------------------------------------------------*/
;;;812    	RTC_EnableInt(RTC_RIER_AIER);
;;;813                
;;;814    	RTC->TTR &= ~RTC_TTR_TWKE;
;;;815    	RTC->TTR |= sPt->u8IsEnableWakeUp ? RTC_TTR_TWKE:0;
;;;816    			
;;;817    	return E_SUCCESS;
;;;818    
;;;819    }
000014  bdf8              POP      {r3-r7,pc}
                  |L14.22|
000016  207d              MOVS     r0,#0x7d              ;775
000018  69e1              LDR      r1,[r4,#0x1c]         ;775
00001a  0100              LSLS     r0,r0,#4              ;775
00001c  1a08              SUBS     r0,r1,r0              ;775
00001e  210a              MOVS     r1,#0xa               ;775
000020  f7fffffe          BL       __aeabi_uidivmod
000024  040d              LSLS     r5,r1,#16             ;776
000026  0500              LSLS     r0,r0,#20             ;775
000028  4305              ORRS     r5,r5,r0              ;776
00002a  210a              MOVS     r1,#0xa               ;777
00002c  69a0              LDR      r0,[r4,#0x18]         ;777
00002e  f7fffffe          BL       __aeabi_uidivmod
000032  0300              LSLS     r0,r0,#12             ;777
000034  4328              ORRS     r0,r0,r5              ;777
000036  020d              LSLS     r5,r1,#8              ;778
000038  4305              ORRS     r5,r5,r0              ;778
00003a  210a              MOVS     r1,#0xa               ;779
00003c  6960              LDR      r0,[r4,#0x14]         ;779
00003e  f7fffffe          BL       __aeabi_uidivmod
000042  0100              LSLS     r0,r0,#4              ;779
000044  4328              ORRS     r0,r0,r5              ;779
000046  4301              ORRS     r1,r1,r0              ;780
000048  6071              STR      r1,[r6,#4]            ;781  ; g_u32Reg
00004a  f7fffffe          BL       RTC_WriteEnable
00004e  6870              LDR      r0,[r6,#4]            ;784  ; g_u32Reg
000050  4d1c              LDR      r5,|L14.196|
000052  6228              STR      r0,[r5,#0x20]         ;784
000054  7830              LDRB     r0,[r6,#0]            ;788  ; g_chHourMode
000056  2800              CMP      r0,#0                 ;788
000058  d105              BNE      |L14.102|
00005a  7860              LDRB     r0,[r4,#1]            ;790
00005c  2802              CMP      r0,#2                 ;790
00005e  d102              BNE      |L14.102|
000060  68e0              LDR      r0,[r4,#0xc]          ;791
000062  3014              ADDS     r0,r0,#0x14           ;791
000064  60e0              STR      r0,[r4,#0xc]          ;791
                  |L14.102|
000066  210a              MOVS     r1,#0xa               ;797
000068  68e0              LDR      r0,[r4,#0xc]          ;797
00006a  f7fffffe          BL       __aeabi_uidivmod
00006e  040f              LSLS     r7,r1,#16             ;798
000070  0500              LSLS     r0,r0,#20             ;797
000072  4307              ORRS     r7,r7,r0              ;798
000074  210a              MOVS     r1,#0xa               ;799
000076  68a0              LDR      r0,[r4,#8]            ;799
000078  f7fffffe          BL       __aeabi_uidivmod
00007c  0300              LSLS     r0,r0,#12             ;799
00007e  4338              ORRS     r0,r0,r7              ;799
000080  020f              LSLS     r7,r1,#8              ;800
000082  4307              ORRS     r7,r7,r0              ;800
000084  210a              MOVS     r1,#0xa               ;801
000086  6860              LDR      r0,[r4,#4]            ;801
000088  f7fffffe          BL       __aeabi_uidivmod
00008c  0100              LSLS     r0,r0,#4              ;801
00008e  4338              ORRS     r0,r0,r7              ;801
000090  4301              ORRS     r1,r1,r0              ;802
000092  6071              STR      r1,[r6,#4]            ;804  ; g_u32Reg
000094  f7fffffe          BL       RTC_WriteEnable
000098  6870              LDR      r0,[r6,#4]            ;806  ; g_u32Reg
00009a  61e8              STR      r0,[r5,#0x1c]         ;806
00009c  2001              MOVS     r0,#1                 ;812
00009e  f7fffffe          BL       RTC_EnableInt
0000a2  6b28              LDR      r0,[r5,#0x30]         ;814
0000a4  2108              MOVS     r1,#8                 ;814
0000a6  4388              BICS     r0,r0,r1              ;814
0000a8  6328              STR      r0,[r5,#0x30]         ;814
0000aa  6b29              LDR      r1,[r5,#0x30]         ;815
0000ac  3420              ADDS     r4,r4,#0x20           ;815
0000ae  7820              LDRB     r0,[r4,#0]            ;815
0000b0  2800              CMP      r0,#0                 ;815
0000b2  d000              BEQ      |L14.182|
0000b4  2008              MOVS     r0,#8                 ;815
                  |L14.182|
0000b6  4301              ORRS     r1,r1,r0              ;815
0000b8  6329              STR      r1,[r5,#0x30]         ;815
0000ba  2000              MOVS     r0,#0                 ;817
0000bc  bdf8              POP      {r3-r7,pc}
;;;820    
                          ENDP

0000be  0000              DCW      0x0000
                  |L14.192|
                          DCD      ||.data||
                  |L14.196|
                          DCD      0x40008000

                          AREA ||i.RTC_WriteEnable||, CODE, READONLY, ALIGN=2

                  RTC_WriteEnable PROC
;;;112     */
;;;113    int32_t RTC_WriteEnable (void)
000000  b510              PUSH     {r4,lr}
;;;114    {
;;;115        int32_t i32i = 0;
;;;116    
;;;117    	int i32retry = 100;
;;;118        
;;;119    	/*-------------------------------------------------------------------------------------------------*/
;;;120        /* After 200ms, Access enable wiil auto-clear. As soon as possible to do your setting              */
;;;121        /*-------------------------------------------------------------------------------------------------*/
;;;122    	RETRY:
;;;123    
;;;124    	i32i = 0;
;;;125    	
;;;126    	RTC->AER = DRVRTC_WRITE_KEY;
000002  4b0a              LDR      r3,|L15.44|
000004  4a0a              LDR      r2,|L15.48|
000006  2164              MOVS     r1,#0x64              ;117
                  |L15.8|
000008  2000              MOVS     r0,#0                 ;124
00000a  6053              STR      r3,[r2,#4]
                  |L15.12|
;;;127    	
;;;128        for (i32i = 0 ; i32i < DRVRTC_WAIT_COUNT ; i32i++)
;;;129    	{
;;;130            /*-------------------------------------------------------------------------------------------------*/
;;;131            /* check RTC_AER[16] to find out RTC write enable                                                  */
;;;132            /*-------------------------------------------------------------------------------------------------*/
;;;133    		RTC->AER = DRVRTC_WRITE_KEY;
00000c  6053              STR      r3,[r2,#4]
;;;134    		
;;;135    		if (RTC->AER & RTC_AER_ENF)
00000e  6854              LDR      r4,[r2,#4]
000010  03e4              LSLS     r4,r4,#15
000012  d403              BMI      |L15.28|
000014  1c40              ADDS     r0,r0,#1              ;128
000016  1c44              ADDS     r4,r0,#1              ;128
000018  d1f8              BNE      |L15.12|
00001a  e003              B        |L15.36|
                  |L15.28|
;;;136    		    break;
;;;137    	}
;;;138    
;;;139    	if (i32i == DRVRTC_WAIT_COUNT)
00001c  1c40              ADDS     r0,r0,#1
00001e  d001              BEQ      |L15.36|
;;;140        {
;;;141            RTCDEBUG ("\nRTC: DrvRTC_WriteEnable, set write enable FAILED!\n");
;;;142    
;;;143    		i32retry--;
;;;144    
;;;145            if(!i32retry)
;;;146    	   		return E_DRVRTC_ERR_FAILED;
;;;147    						
;;;148    		goto RETRY;
;;;149        }
;;;150    
;;;151    	return E_SUCCESS;
000020  2000              MOVS     r0,#0
;;;152    }
000022  bd10              POP      {r4,pc}
                  |L15.36|
000024  1e49              SUBS     r1,r1,#1              ;143
000026  d1ef              BNE      |L15.8|
000028  2009              MOVS     r0,#9                 ;146
00002a  bd10              POP      {r4,pc}
;;;153    
                          ENDP

                  |L15.44|
                          DCD      0x0000a965
                  |L15.48|
                          DCD      0x40008000

                          AREA ||.data||, DATA, ALIGN=2

                  g_chHourMode
000000  00000000          DCB      0x00,0x00,0x00,0x00
                  g_u32Reg
                          DCD      0x00000000
                  g_u32hiYear
                          DCD      0x00000000
                  g_u32loYear
                          DCD      0x00000000
                  g_u32hiMonth
                          DCD      0x00000000
                  g_u32loMonth
                          DCD      0x00000000
                  g_u32hiDay
                          DCD      0x00000000
                  g_u32loDay
                          DCD      0x00000000
                  g_u32hiHour
                          DCD      0x00000000
                  g_u32loHour
                          DCD      0x00000000
                  g_u32hiMin
                          DCD      0x00000000
                  g_u32loMin
                          DCD      0x00000000
                  g_u32hiSec
                          DCD      0x00000000
                  g_u32loSec
                          DCD      0x00000000

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_rtc.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_rtc_c_61289f98____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___13_nano1xx_rtc_c_61289f98____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_rtc_c_61289f98____REVSH|
#line 130
|__asm___13_nano1xx_rtc_c_61289f98____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
