; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_sys.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_sys.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_sys.crf ..\bsp\Driver\nano1xx_sys.c]
                          THUMB

                          AREA ||i.SYS_Delay||, CODE, READONLY, ALIGN=2

                  SYS_Delay PROC
;;;262      */
;;;263    void SYS_Delay(uint32_t us)
000000  b510              PUSH     {r4,lr}
;;;264    {
000002  4604              MOV      r4,r0
;;;265    	SysTick->LOAD = (us * ((SystemCoreClock + 500000) / 1000000));
000004  480a              LDR      r0,|L1.48|
000006  4909              LDR      r1,|L1.44|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00000a  104a              ASRS     r2,r1,#1
00000c  1880              ADDS     r0,r0,r2
00000e  f7fffffe          BL       __aeabi_uidivmod
000012  4601              MOV      r1,r0
000014  4807              LDR      r0,|L1.52|
000016  4361              MULS     r1,r4,r1
000018  6141              STR      r1,[r0,#0x14]
;;;266    	SysTick->VAL  = (0x00);
00001a  2100              MOVS     r1,#0
00001c  6181              STR      r1,[r0,#0x18]
;;;267        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
00001e  2105              MOVS     r1,#5
000020  6101              STR      r1,[r0,#0x10]
                  |L1.34|
;;;268    
;;;269        /* Waiting for down-count to zero */
;;;270        while((SysTick->CTRL & (1 << 16)) == 0);
000022  6901              LDR      r1,[r0,#0x10]
000024  03c9              LSLS     r1,r1,#15
000026  d5fc              BPL      |L1.34|
;;;271    
;;;272    }
000028  bd10              POP      {r4,pc}
;;;273    
                          ENDP

00002a  0000              DCW      0x0000
                  |L1.44|
                          DCD      0x000f4240
                  |L1.48|
                          DCD      SystemCoreClock
                  |L1.52|
                          DCD      0xe000e000

                          AREA ||i.SYS_GetHCLKFreq||, CODE, READONLY, ALIGN=2

                  SYS_GetHCLKFreq PROC
;;;132      */
;;;133    uint32_t SYS_GetHCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;134    {
;;;135    	
;;;136    	uint32_t u32Freqout, u32AHBDivider, u32ClkSel;
;;;137    
;;;138    	u32ClkSel = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_MASK;
000002  4c0d              LDR      r4,|L2.56|
000004  6920              LDR      r0,[r4,#0x10]
000006  0741              LSLS     r1,r0,#29
;;;139    
;;;140    	if (u32ClkSel == CLK_CLKSEL0_HCLK_HXT)	/* external HXT crystal clock */
;;;141    	{
;;;142    		u32Freqout = __XTAL;	
000008  480c              LDR      r0,|L2.60|
00000a  0f49              LSRS     r1,r1,#29             ;138
00000c  d00d              BEQ      |L2.42|
;;;143    	}
;;;144    	else if(u32ClkSel == CLK_CLKSEL0_HCLK_LXT)		/* external LXT crystal clock */ 
00000e  2901              CMP      r1,#1
000010  d004              BEQ      |L2.28|
;;;145    	{
;;;146    		u32Freqout = __RTC_XTAL;
;;;147    	}
;;;148    	else if(u32ClkSel == CLK_CLKSEL0_HCLK_PLL)		/* PLL clock */
000012  2902              CMP      r1,#2
000014  d005              BEQ      |L2.34|
;;;149    	{
;;;150    		u32Freqout = SYS_GetPLLClockFreq();
;;;151    	}
;;;152    	else if(u32ClkSel == CLK_CLKSEL0_HCLK_LIRC)	/* internal LIRC oscillator clock */
000016  2903              CMP      r1,#3
000018  d006              BEQ      |L2.40|
00001a  e006              B        |L2.42|
                  |L2.28|
00001c  2001              MOVS     r0,#1                 ;146
00001e  03c0              LSLS     r0,r0,#15             ;146
000020  e003              B        |L2.42|
                  |L2.34|
000022  f7fffffe          BL       SYS_GetPLLClockFreq
000026  e000              B        |L2.42|
                  |L2.40|
;;;153    	{
;;;154    	 	u32Freqout = __IRC10K;
000028  4805              LDR      r0,|L2.64|
                  |L2.42|
;;;155    	}
;;;156    	else									/* internal HIRC oscillator clock */
;;;157    	{
;;;158    	 	u32Freqout = __IRC12M;
;;;159    	
;;;160    	}
;;;161    	u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK_MASK) + 1 ;
00002a  69e1              LDR      r1,[r4,#0x1c]
00002c  0709              LSLS     r1,r1,#28
00002e  0f09              LSRS     r1,r1,#28
000030  1c49              ADDS     r1,r1,#1
;;;162    	
;;;163    	return (u32Freqout/u32AHBDivider);	
000032  f7fffffe          BL       __aeabi_uidivmod
;;;164    }
000036  bd10              POP      {r4,pc}
;;;165    
                          ENDP

                  |L2.56|
                          DCD      0x50000200
                  |L2.60|
                          DCD      0x00b71b00
                  |L2.64|
                          DCD      0x00002710

                          AREA ||i.SYS_GetPLLClockFreq||, CODE, READONLY, ALIGN=2

                  SYS_GetPLLClockFreq PROC
;;;94       */
;;;95     uint32_t SYS_GetPLLClockFreq(void)
000000  b510              PUSH     {r4,lr}
;;;96     {
;;;97     	uint32_t u32Freq =0, u32PLLSrc;
;;;98         uint32_t u32NO, u32NR, u32IN_DV, u32PllReg;
;;;99     
;;;100    	u32PllReg = CLK->PLLCTL;
000002  4812              LDR      r0,|L3.76|
000004  6a40              LDR      r0,[r0,#0x24]
;;;101    
;;;102    	if (u32PllReg & CLK_PLLCTL_PD)  
000006  03c1              LSLS     r1,r0,#15
000008  d501              BPL      |L3.14|
;;;103    		return 0;	 /* PLL is in power down mode */
00000a  2000              MOVS     r0,#0
;;;104    	
;;;105    	if (u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
;;;106    		u32PLLSrc = __IRC12M;
;;;107    	else
;;;108    		u32PLLSrc = __XTAL;
;;;109    
;;;110        u32NO = (u32PllReg & CLK_PLLCTL_OUT_DV) ? 2: 1;
;;;111    
;;;112    	u32IN_DV = (u32PllReg & CLK_PLLCTL_IN_DIVIDER_MASK) >> 8;
;;;113    	if (u32IN_DV == 0)
;;;114    		u32NR = 2;
;;;115    	else if (u32IN_DV == 1)
;;;116    		u32NR = 4;
;;;117    	else if (u32IN_DV == 2)
;;;118    		u32NR = 8;
;;;119    	else
;;;120    		u32NR = 16;
;;;121    
;;;122    	u32Freq = u32PLLSrc * ((u32PllReg & CLK_PLLCTL_FB_DIVIDER_MASK) +32) / u32NR / u32NO;
;;;123    
;;;124    	return u32Freq;
;;;125    }
00000c  bd10              POP      {r4,pc}
                  |L3.14|
00000e  04c1              LSLS     r1,r0,#19             ;110
000010  d501              BPL      |L3.22|
000012  2402              MOVS     r4,#2                 ;110
000014  e000              B        |L3.24|
                  |L3.22|
000016  2401              MOVS     r4,#1                 ;110
                  |L3.24|
000018  0581              LSLS     r1,r0,#22             ;112
00001a  0f89              LSRS     r1,r1,#30             ;112
00001c  d00f              BEQ      |L3.62|
00001e  2901              CMP      r1,#1                 ;115
000020  d00f              BEQ      |L3.66|
000022  2902              CMP      r1,#2                 ;117
000024  d00f              BEQ      |L3.70|
000026  2110              MOVS     r1,#0x10              ;120
                  |L3.40|
000028  0680              LSLS     r0,r0,#26             ;122
00002a  0e80              LSRS     r0,r0,#26             ;122
00002c  4a08              LDR      r2,|L3.80|
00002e  3020              ADDS     r0,r0,#0x20           ;122
000030  4350              MULS     r0,r2,r0              ;122
000032  f7fffffe          BL       __aeabi_uidivmod
000036  4621              MOV      r1,r4                 ;122
000038  f7fffffe          BL       __aeabi_uidivmod
00003c  bd10              POP      {r4,pc}
                  |L3.62|
00003e  2102              MOVS     r1,#2                 ;114
000040  e7f2              B        |L3.40|
                  |L3.66|
000042  2104              MOVS     r1,#4                 ;116
000044  e7f0              B        |L3.40|
                  |L3.70|
000046  2108              MOVS     r1,#8                 ;118
000048  e7ee              B        |L3.40|
;;;126    
                          ENDP

00004a  0000              DCW      0x0000
                  |L3.76|
                          DCD      0x50000200
                  |L3.80|
                          DCD      0x00b71b00

                          AREA ||i.SYS_InitChipClock||, CODE, READONLY, ALIGN=2

                  SYS_InitChipClock PROC
;;;201      */
;;;202    int32_t SYS_InitChipClock(S_SYS_CHIP_CLKCFG *sChipCfg)
000000  b570              PUSH     {r4-r6,lr}
;;;203    {
;;;204    	uint32_t u32ClkEn, u32ClkSts, u32PllCtl;	
;;;205    	volatile uint32_t delayCnt;
;;;206    	
;;;207    	assert_param(CHECK_CLK_CONFIG(sChipCfg));               /* Check input parameter */
;;;208    	assert_param(CHECK_HCLK_SOURCE(sChipCfg->u32HClkSrc));  /* Check HCLK clock select */
;;;209    
;;;210    	/* enable chip clock sources */
;;;211    	u32ClkEn = u32ClkSts = (sChipCfg->u32ChipClkEn) & 0x0F; 
000002  6801              LDR      r1,[r0,#0]
000004  070a              LSLS     r2,r1,#28
000006  0f12              LSRS     r2,r2,#28
000008  4611              MOV      r1,r2
;;;212    	if (u32ClkSts & CLK_PWRCTL_HIRC_EN) 
00000a  0753              LSLS     r3,r2,#29
00000c  d503              BPL      |L4.22|
;;;213    		u32ClkSts = (u32ClkSts & ~CLK_PWRCTL_HIRC_EN) | CLK_CLKSTATUS_HIRC_STB;
00000e  2304              MOVS     r3,#4
000010  439a              BICS     r2,r2,r3
000012  2310              MOVS     r3,#0x10
000014  431a              ORRS     r2,r2,r3
                  |L4.22|
;;;214    	
;;;215    	SYS_SetChipClockSrc(u32ClkEn, 1);  /* enable the selected chip clock sources */
000016  460c              MOV      r4,r1
000018  4929              LDR      r1,|L4.192|
00001a  680b              LDR      r3,[r1,#0]
00001c  4d29              LDR      r5,|L4.196|
00001e  07db              LSLS     r3,r3,#31
000020  17db              ASRS     r3,r3,#31
000022  1c5b              ADDS     r3,r3,#1
000024  602b              STR      r3,[r5,#0]  ; lock_sts
000026  682b              LDR      r3,[r5,#0]  ; lock_sts
000028  2b00              CMP      r3,#0
00002a  d005              BEQ      |L4.56|
00002c  2359              MOVS     r3,#0x59
00002e  600b              STR      r3,[r1,#0]
000030  2316              MOVS     r3,#0x16
000032  600b              STR      r3,[r1,#0]
000034  2388              MOVS     r3,#0x88
000036  600b              STR      r3,[r1,#0]
                  |L4.56|
000038  4b23              LDR      r3,|L4.200|
00003a  681e              LDR      r6,[r3,#0]
00003c  4326              ORRS     r6,r6,r4
00003e  601e              STR      r6,[r3,#0]
000040  682c              LDR      r4,[r5,#0]  ; lock_sts
000042  2c00              CMP      r4,#0
000044  d001              BEQ      |L4.74|
000046  2400              MOVS     r4,#0
000048  600c              STR      r4,[r1,#0]
                  |L4.74|
;;;216    	
;;;217    	for (delayCnt=0; delayCnt<100000; delayCnt++)
00004a  4c20              LDR      r4,|L4.204|
00004c  2100              MOVS     r1,#0
                  |L4.78|
;;;218    		if ((CLK->CLKSTATUS & u32ClkSts) == u32ClkSts)
00004e  68de              LDR      r6,[r3,#0xc]
000050  4615              MOV      r5,r2
000052  43b5              BICS     r5,r5,r6
000054  d002              BEQ      |L4.92|
000056  1c49              ADDS     r1,r1,#1              ;217
000058  42a1              CMP      r1,r4                 ;217
00005a  d3f8              BCC      |L4.78|
                  |L4.92|
;;;219    			break;
;;;220    
;;;221    	if (delayCnt == 100000)
00005c  42a1              CMP      r1,r4
00005e  d102              BNE      |L4.102|
;;;222    		return -1;
000060  2000              MOVS     r0,#0
000062  43c0              MVNS     r0,r0
;;;223    
;;;224    	/* enable PLL */
;;;225    	if (sChipCfg->u8PLLEnable == 1)  {
;;;226    
;;;227    		/* check PLL in clock freq. */
;;;228    		assert_param(CHECK_PLLIN_CLK(sChipCfg->ePLLInFreq));
;;;229    		assert_param(CHECK_PLLOUT_CLK(sChipCfg->ePLLOutFreq));
;;;230    		
;;;231    		u32PllCtl = _DrvSYS_PLL_Table[sChipCfg->ePLLInFreq][sChipCfg->ePLLOutFreq];
;;;232    
;;;233    		if (u32PllCtl == PLL_NOT_SUPPORTED)
;;;234    			return -2;
;;;235    
;;;236    		/* select correct pll clock source */
;;;237    		u32PllCtl |= sChipCfg->u32PLLClkSrc;
;;;238    
;;;239    		/* set PLL control reg and waits for PLL clock stable */
;;;240    		CLK->PLLCTL = u32PllCtl;
;;;241    
;;;242    		for (delayCnt=0; delayCnt<100000; delayCnt++)
;;;243    			if (CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB)
;;;244    				break;
;;;245    
;;;246    		if (delayCnt == 100000)
;;;247    			return -3;		
;;;248    	}
;;;249    
;;;250    	/* set HCLK divider and source */
;;;251    	CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_MASK) | sChipCfg->u32HClkDiv;
;;;252    	SYS_SelectHCLKSource(sChipCfg->u32HClkSrc); /* select required clock source for HCLk */
;;;253    
;;;254    	return 0;
;;;255    }
000064  bd70              POP      {r4-r6,pc}
                  |L4.102|
000066  7a01              LDRB     r1,[r0,#8]            ;225
000068  2901              CMP      r1,#1                 ;225
00006a  d11d              BNE      |L4.168|
00006c  7a41              LDRB     r1,[r0,#9]            ;231
00006e  220c              MOVS     r2,#0xc               ;231
000070  4351              MULS     r1,r2,r1              ;231
000072  4a14              LDR      r2,|L4.196|
000074  320c              ADDS     r2,r2,#0xc            ;231
000076  1889              ADDS     r1,r1,r2              ;231
000078  7a82              LDRB     r2,[r0,#0xa]          ;231
00007a  0052              LSLS     r2,r2,#1              ;231
00007c  5a89              LDRH     r1,[r1,r2]            ;231
00007e  4a14              LDR      r2,|L4.208|
000080  4291              CMP      r1,r2                 ;233
000082  d102              BNE      |L4.138|
000084  2001              MOVS     r0,#1                 ;234
000086  43c0              MVNS     r0,r0                 ;234
000088  bd70              POP      {r4-r6,pc}
                  |L4.138|
00008a  6842              LDR      r2,[r0,#4]            ;237
00008c  430a              ORRS     r2,r2,r1              ;237
00008e  625a              STR      r2,[r3,#0x24]         ;240
000090  2100              MOVS     r1,#0                 ;242
                  |L4.146|
000092  68da              LDR      r2,[r3,#0xc]          ;243
000094  0752              LSLS     r2,r2,#29             ;243
000096  d402              BMI      |L4.158|
000098  1c49              ADDS     r1,r1,#1              ;242
00009a  42a1              CMP      r1,r4                 ;242
00009c  d3f9              BCC      |L4.146|
                  |L4.158|
00009e  42a1              CMP      r1,r4                 ;246
0000a0  d102              BNE      |L4.168|
0000a2  2002              MOVS     r0,#2                 ;247
0000a4  43c0              MVNS     r0,r0                 ;247
0000a6  bd70              POP      {r4-r6,pc}
                  |L4.168|
0000a8  69d9              LDR      r1,[r3,#0x1c]         ;251
0000aa  6902              LDR      r2,[r0,#0x10]         ;251
0000ac  0909              LSRS     r1,r1,#4              ;251
0000ae  0109              LSLS     r1,r1,#4              ;251
0000b0  4311              ORRS     r1,r1,r2              ;251
0000b2  61d9              STR      r1,[r3,#0x1c]         ;251
0000b4  68c0              LDR      r0,[r0,#0xc]          ;252
0000b6  f7fffffe          BL       SYS_SelectHCLKSource
0000ba  2000              MOVS     r0,#0                 ;254
0000bc  bd70              POP      {r4-r6,pc}
;;;256    
                          ENDP

0000be  0000              DCW      0x0000
                  |L4.192|
                          DCD      0x50000100
                  |L4.196|
                          DCD      ||.data||
                  |L4.200|
                          DCD      0x50000200
                  |L4.204|
                          DCD      0x000186a0
                  |L4.208|
                          DCD      0x0000ffff

                          AREA ||i.SYS_SelectHCLKSource||, CODE, READONLY, ALIGN=2

                  SYS_SelectHCLKSource PROC
;;;43       */
;;;44     int32_t SYS_SelectHCLKSource(uint32_t u32ClkSrc)
000000  b510              PUSH     {r4,lr}
;;;45     {
;;;46     	static __IO uint32_t lock_sts = 0;
;;;47     
;;;48     	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4914              LDR      r1,|L5.84|
000004  680a              LDR      r2,[r1,#0]
000006  4b14              LDR      r3,|L5.88|
000008  07d2              LSLS     r2,r2,#31
00000a  17d2              ASRS     r2,r2,#31
00000c  1c52              ADDS     r2,r2,#1
00000e  605a              STR      r2,[r3,#4]  ; lock_sts
;;;49     
;;;50     	if (lock_sts)	UNLOCKREG();
000010  685a              LDR      r2,[r3,#4]  ; lock_sts
000012  2a00              CMP      r2,#0
000014  d005              BEQ      |L5.34|
000016  2259              MOVS     r2,#0x59
000018  600a              STR      r2,[r1,#0]
00001a  2216              MOVS     r2,#0x16
00001c  600a              STR      r2,[r1,#0]
00001e  2288              MOVS     r2,#0x88
000020  600a              STR      r2,[r1,#0]
                  |L5.34|
;;;51     	CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_MASK) | u32ClkSrc;
000022  4a0e              LDR      r2,|L5.92|
000024  6914              LDR      r4,[r2,#0x10]
000026  08e4              LSRS     r4,r4,#3
000028  00e4              LSLS     r4,r4,#3
00002a  4304              ORRS     r4,r4,r0
00002c  6114              STR      r4,[r2,#0x10]
;;;52     	if (lock_sts)	LOCKREG();
00002e  6858              LDR      r0,[r3,#4]  ; lock_sts
000030  2800              CMP      r0,#0
000032  d001              BEQ      |L5.56|
000034  2000              MOVS     r0,#0
000036  6008              STR      r0,[r1,#0]
                  |L5.56|
;;;53     
;;;54     	if (CLK->CLKSTATUS & CLK_CLKSTATUS_CLK_SW_FAIL)  {
000038  68d0              LDR      r0,[r2,#0xc]
00003a  0600              LSLS     r0,r0,#24
00003c  d506              BPL      |L5.76|
;;;55     		CLK->CLKSTATUS |= CLK_CLKSTATUS_CLK_SW_FAIL;   /* Clear Clock Switch Fail Flag */
00003e  68d0              LDR      r0,[r2,#0xc]
000040  2180              MOVS     r1,#0x80
000042  4308              ORRS     r0,r0,r1
000044  60d0              STR      r0,[r2,#0xc]
;;;56             return -1;  /* HCLK isn't changed */
000046  2000              MOVS     r0,#0
000048  43c0              MVNS     r0,r0
;;;57         }
;;;58     		
;;;59     	SystemCoreClockUpdate(); /* HCLK is changed successfully */
;;;60     	
;;;61     	return 0;
;;;62     }
00004a  bd10              POP      {r4,pc}
                  |L5.76|
00004c  f7fffffe          BL       SystemCoreClockUpdate
000050  2000              MOVS     r0,#0                 ;61
000052  bd10              POP      {r4,pc}
;;;63     
                          ENDP

                  |L5.84|
                          DCD      0x50000100
                  |L5.88|
                          DCD      ||.data||
                  |L5.92|
                          DCD      0x50000200

                          AREA ||i.SYS_SetUpPowerDown||, CODE, READONLY, ALIGN=2

                  SYS_SetUpPowerDown PROC
;;;69       */
;;;70     void SYS_SetUpPowerDown(uint32_t u32Enable)
000000  b570              PUSH     {r4-r6,lr}
;;;71     {	
;;;72     	static __IO uint32_t lock_sts = 0;
;;;73     	
;;;74     	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4914              LDR      r1,|L6.84|
000004  680a              LDR      r2,[r1,#0]
000006  4c14              LDR      r4,|L6.88|
000008  07d2              LSLS     r2,r2,#31
00000a  17d2              ASRS     r2,r2,#31
00000c  1c52              ADDS     r2,r2,#1
00000e  60a2              STR      r2,[r4,#8]  ; lock_sts
;;;75     	
;;;76     	if (lock_sts)	UNLOCKREG();
000010  68a2              LDR      r2,[r4,#8]  ; lock_sts
000012  2a00              CMP      r2,#0
000014  d005              BEQ      |L6.34|
000016  2259              MOVS     r2,#0x59
000018  600a              STR      r2,[r1,#0]
00001a  2216              MOVS     r2,#0x16
00001c  600a              STR      r2,[r1,#0]
00001e  2288              MOVS     r2,#0x88
000020  600a              STR      r2,[r1,#0]
                  |L6.34|
;;;77     
;;;78     	CLK->PWRCTL |= CLK_PWRCTL_PWRDOWN_EN;	   /* Set power down bit */
000022  4a0e              LDR      r2,|L6.92|
000024  6813              LDR      r3,[r2,#0]
000026  2540              MOVS     r5,#0x40
000028  432b              ORRS     r3,r3,r5
00002a  6013              STR      r3,[r2,#0]
;;;79     	SCB->SCR |= 0x04;						   /* Sleep Deep */
00002c  4b0c              LDR      r3,|L6.96|
00002e  691d              LDR      r5,[r3,#0x10]
000030  2604              MOVS     r6,#4
000032  4335              ORRS     r5,r5,r6
000034  611d              STR      r5,[r3,#0x10]
;;;80     
;;;81     	if (u32Enable)  {
000036  2800              CMP      r0,#0
000038  d006              BEQ      |L6.72|
;;;82     		CLK->PWRCTL |= CLK_PWRCTL_WAKEINT_EN;  /* Enable wake up interrupt source */
00003a  6810              LDR      r0,[r2,#0]
00003c  2320              MOVS     r3,#0x20
00003e  4318              ORRS     r0,r0,r3
000040  6010              STR      r0,[r2,#0]
000042  04d0              LSLS     r0,r2,#19
000044  4a07              LDR      r2,|L6.100|
000046  6010              STR      r0,[r2,#0]
                  |L6.72|
;;;83     	    NVIC_EnableIRQ(PDWU_IRQn);			   /* Enable IRQ request for PDWU interupt */
;;;84     	}
;;;85     
;;;86     	if (lock_sts)	LOCKREG();
000048  68a0              LDR      r0,[r4,#8]  ; lock_sts
00004a  2800              CMP      r0,#0
00004c  d001              BEQ      |L6.82|
00004e  2000              MOVS     r0,#0
000050  6008              STR      r0,[r1,#0]
                  |L6.82|
;;;87     }
000052  bd70              POP      {r4-r6,pc}
;;;88     
                          ENDP

                  |L6.84|
                          DCD      0x50000100
                  |L6.88|
                          DCD      ||.data||
                  |L6.92|
                          DCD      0x50000200
                  |L6.96|
                          DCD      0xe000ed00
                  |L6.100|
                          DCD      0xe000e100

                          AREA ||.data||, DATA, ALIGN=2

                  lock_sts
                          DCD      0x00000000
                  |symbol_number.23|
                          DCD      0x00000000
                  |symbol_number.24|
                          DCD      0x00000000
                  _DrvSYS_PLL_Table
00000c  ffff0110          DCW      0xffff,0x0110
000010  ffff0010          DCW      0xffff,0x0010
000014  001cffff          DCW      0x001c,0xffff
000018  ffff0210          DCW      0xffff,0x0210
00001c  ffff0110          DCW      0xffff,0x0110
000020  ffff0120          DCW      0xffff,0x0120
000024  ffff0200          DCW      0xffff,0x0200
000028  ffff0100          DCW      0xffff,0x0100
00002c  0230ffff          DCW      0x0230,0xffff
000030  0310ffff          DCW      0x0310,0xffff
000034  0210ffff          DCW      0x0210,0xffff
000038  0220ffff          DCW      0x0220,0xffff
00003c  ffff1320          DCW      0xffff,0x1320
000040  ffff0320          DCW      0xffff,0x0320
000044  0330ffff          DCW      0x0330,0xffff

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_sys.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_sys_c_883593a2____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___13_nano1xx_sys_c_883593a2____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_sys_c_883593a2____REVSH|
#line 130
|__asm___13_nano1xx_sys_c_883593a2____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
