; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_timer.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_timer.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_timer.crf ..\bsp\Driver\nano1xx_timer.c]
                          THUMB

                          AREA ||i.NVIC_DisableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_DisableIRQ PROC
;;;511     */
;;;512    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;513    {
;;;514      NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L1.16|
00000a  6008              STR      r0,[r1,#0]
;;;515    }
00000c  4770              BX       lr
;;;516    
                          ENDP

00000e  0000              DCW      0x0000
                  |L1.16|
                          DCD      0xe000e180

                          AREA ||i.NVIC_EnableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_EnableIRQ PROC
;;;499     */
;;;500    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;501    {
;;;502      NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L2.16|
00000a  6008              STR      r0,[r1,#0]
;;;503    }
00000c  4770              BX       lr
;;;504    
                          ENDP

00000e  0000              DCW      0x0000
                  |L2.16|
                          DCD      0xe000e100

                          AREA ||i.TIMER_ConfigTriggerEvent||, CODE, READONLY, ALIGN=1

                  TIMER_ConfigTriggerEvent PROC
;;;138      */
;;;139    void TIMER_ConfigTriggerEvent(TIMER_TypeDef *timer, uint32_t u32Event, uint32_t u32Src)
000000  b510              PUSH     {r4,lr}
;;;140    {
;;;141    	uint32_t reg;
;;;142    
;;;143            assert_param(u32Event != 0);
;;;144            assert_param((u32Event & ~(TIMER_CTL_ADCTEEN | TIMER_CTL_DACTEEN | TIMER_CTL_PDMA_TEEN | TIMER_CTL_TKWAKEEN)) == 0);
;;;145            assert_param(!((timer != TIMER0) && (u32Event & TIMER_CTL_TKWAKEEN)));
;;;146    	assert_param((u32Src == TIMER_CTL_CAPTRGEN) || (u32Src == TIMER_CTL_TIMEOUTTRGEN));
;;;147    
;;;148    	reg = timer->CTL & ~(TIMER_CTL_ADCTEEN | TIMER_CTL_DACTEEN | TIMER_CTL_PDMA_TEEN | TIMER_CTL_TKWAKEEN | TIMER_CTL_CAPTRGEN);
000002  6803              LDR      r3,[r0,#0]
000004  248f              MOVS     r4,#0x8f
000006  0224              LSLS     r4,r4,#8
000008  43a3              BICS     r3,r3,r4
;;;149            timer->CTL = reg | u32Event | u32Src;
00000a  430b              ORRS     r3,r3,r1
00000c  4313              ORRS     r3,r3,r2
00000e  6003              STR      r3,[r0,#0]
;;;150    }
000010  bd10              POP      {r4,pc}
;;;151    
                          ENDP


                          AREA ||i.TIMER_DeInit||, CODE, READONLY, ALIGN=2

                  TIMER_DeInit PROC
;;;56       */
;;;57     void TIMER_DeInit(TIMER_TypeDef *timer)
000000  b510              PUSH     {r4,lr}
;;;58     {
;;;59     	timer->CTL = TIMER_CTL_SWRST;
000002  2102              MOVS     r1,#2
000004  6001              STR      r1,[r0,#0]
                  |L4.6|
;;;60     	while(timer->CTL & TIMER_CTL_SWRST);
000006  6801              LDR      r1,[r0,#0]
000008  0789              LSLS     r1,r1,#30
00000a  d4fc              BMI      |L4.6|
;;;61     	timer->IER = 0;
00000c  2100              MOVS     r1,#0
00000e  60c1              STR      r1,[r0,#0xc]
;;;62     
;;;63     	if(timer == TIMER0) {
000010  4a11              LDR      r2,|L4.88|
;;;64     		CLK->APBCLK &= ~CLK_APBCLK_TMR0_EN;
000012  4912              LDR      r1,|L4.92|
000014  4290              CMP      r0,r2                 ;63
000016  d105              BNE      |L4.36|
000018  6888              LDR      r0,[r1,#8]
00001a  2204              MOVS     r2,#4
00001c  4390              BICS     r0,r0,r2
00001e  6088              STR      r0,[r1,#8]
;;;65     		NVIC_DisableIRQ(TMR0_IRQn);
000020  2008              MOVS     r0,#8
000022  e007              B        |L4.52|
                  |L4.36|
;;;66     	} else if(timer == TIMER1) {
000024  4a0e              LDR      r2,|L4.96|
000026  4290              CMP      r0,r2
000028  d107              BNE      |L4.58|
;;;67     		CLK->APBCLK &= ~CLK_APBCLK_TMR1_EN;
00002a  6888              LDR      r0,[r1,#8]
00002c  2208              MOVS     r2,#8
00002e  4390              BICS     r0,r0,r2
000030  6088              STR      r0,[r1,#8]
;;;68     		NVIC_DisableIRQ(TMR1_IRQn);
000032  2009              MOVS     r0,#9
                  |L4.52|
000034  f7fffffe          BL       NVIC_DisableIRQ
;;;69     	} else if(timer == TIMER2) {
;;;70     		CLK->APBCLK &= ~CLK_APBCLK_TMR2_EN;
;;;71     		NVIC_DisableIRQ(TMR2_IRQn);
;;;72     	} else {
;;;73     		CLK->APBCLK &= ~CLK_APBCLK_TMR3_EN;
;;;74     		NVIC_DisableIRQ(TMR3_IRQn);
;;;75     	}
;;;76     
;;;77     }
000038  bd10              POP      {r4,pc}
                  |L4.58|
00003a  4a0a              LDR      r2,|L4.100|
00003c  4290              CMP      r0,r2                 ;69
00003e  6888              LDR      r0,[r1,#8]            ;73
000040  d104              BNE      |L4.76|
000042  2210              MOVS     r2,#0x10              ;70
000044  4390              BICS     r0,r0,r2              ;70
000046  6088              STR      r0,[r1,#8]            ;70
000048  200a              MOVS     r0,#0xa               ;71
00004a  e7f3              B        |L4.52|
                  |L4.76|
00004c  2220              MOVS     r2,#0x20              ;73
00004e  4390              BICS     r0,r0,r2              ;73
000050  6088              STR      r0,[r1,#8]            ;73
000052  200b              MOVS     r0,#0xb               ;74
000054  e7ee              B        |L4.52|
;;;78     
                          ENDP

000056  0000              DCW      0x0000
                  |L4.88|
                          DCD      0x40010000
                  |L4.92|
                          DCD      0x50000200
                  |L4.96|
                          DCD      0x40010100
                  |L4.100|
                          DCD      0x40110000

                          AREA ||i.TIMER_DisableInt||, CODE, READONLY, ALIGN=2

                  TIMER_DisableInt PROC
;;;109      */
;;;110    void TIMER_DisableInt(TIMER_TypeDef *timer, uint32_t u32Mask)
000000  b510              PUSH     {r4,lr}
;;;111    {
;;;112            assert_param(u32Mask != 0);
;;;113            assert_param((u32Mask & ~(TIMER_IER_TMRIE | TIMER_IER_TCAPIE)) == 0);
;;;114    
;;;115    	timer->IER &= ~u32Mask;
000002  68c2              LDR      r2,[r0,#0xc]
000004  438a              BICS     r2,r2,r1
000006  60c2              STR      r2,[r0,#0xc]
;;;116    
;;;117            if(timer->IER == 0) {
000008  68c1              LDR      r1,[r0,#0xc]
00000a  2900              CMP      r1,#0
00000c  d10a              BNE      |L5.36|
;;;118    		if(timer == TIMER0) {
00000e  4909              LDR      r1,|L5.52|
000010  4288              CMP      r0,r1
000012  d101              BNE      |L5.24|
;;;119    			NVIC_DisableIRQ(TMR0_IRQn);
000014  2008              MOVS     r0,#8
000016  e003              B        |L5.32|
                  |L5.24|
;;;120    		} else if(timer == TIMER1) {
000018  4907              LDR      r1,|L5.56|
00001a  4288              CMP      r0,r1
00001c  d103              BNE      |L5.38|
;;;121    			NVIC_DisableIRQ(TMR1_IRQn);
00001e  2009              MOVS     r0,#9
                  |L5.32|
000020  f7fffffe          BL       NVIC_DisableIRQ
                  |L5.36|
;;;122    		} else if(timer == TIMER2) {
;;;123    			NVIC_DisableIRQ(TMR2_IRQn);
;;;124    		} else {
;;;125    			NVIC_DisableIRQ(TMR3_IRQn);
;;;126    		}
;;;127            }
;;;128    
;;;129    }
000024  bd10              POP      {r4,pc}
                  |L5.38|
000026  4905              LDR      r1,|L5.60|
000028  4288              CMP      r0,r1                 ;122
00002a  d101              BNE      |L5.48|
00002c  200a              MOVS     r0,#0xa               ;123
00002e  e7f7              B        |L5.32|
                  |L5.48|
000030  200b              MOVS     r0,#0xb               ;125
000032  e7f5              B        |L5.32|
;;;130    
                          ENDP

                  |L5.52|
                          DCD      0x40010000
                  |L5.56|
                          DCD      0x40010100
                  |L5.60|
                          DCD      0x40110000

                          AREA ||i.TIMER_EnableInt||, CODE, READONLY, ALIGN=2

                  TIMER_EnableInt PROC
;;;84       */
;;;85     void TIMER_EnableInt(TIMER_TypeDef *timer, uint32_t u32Mask)
000000  b510              PUSH     {r4,lr}
;;;86     {
;;;87             assert_param(u32Mask != 0);
;;;88             assert_param((u32Mask & ~(TIMER_IER_TMRIE | TIMER_IER_TCAPIE)) == 0);
;;;89     
;;;90             timer->ISR = timer->ISR;  // clear pending interrupt
000002  6902              LDR      r2,[r0,#0x10]
000004  6102              STR      r2,[r0,#0x10]
;;;91             timer->IER |= u32Mask;
000006  68c2              LDR      r2,[r0,#0xc]
000008  430a              ORRS     r2,r2,r1
00000a  60c2              STR      r2,[r0,#0xc]
;;;92     
;;;93     	if(timer == TIMER0) {
00000c  4909              LDR      r1,|L6.52|
00000e  4288              CMP      r0,r1
000010  d101              BNE      |L6.22|
;;;94     		NVIC_EnableIRQ(TMR0_IRQn);
000012  2008              MOVS     r0,#8
000014  e003              B        |L6.30|
                  |L6.22|
;;;95     	} else if(timer == TIMER1) {
000016  4908              LDR      r1,|L6.56|
000018  4288              CMP      r0,r1
00001a  d103              BNE      |L6.36|
;;;96     		NVIC_EnableIRQ(TMR1_IRQn);
00001c  2009              MOVS     r0,#9
                  |L6.30|
00001e  f7fffffe          BL       NVIC_EnableIRQ
;;;97     	} else if(timer == TIMER2) {
;;;98     		NVIC_EnableIRQ(TMR2_IRQn);
;;;99     	} else {
;;;100    		NVIC_EnableIRQ(TMR3_IRQn);
;;;101    	}
;;;102    }
000022  bd10              POP      {r4,pc}
                  |L6.36|
000024  4905              LDR      r1,|L6.60|
000026  4288              CMP      r0,r1                 ;97
000028  d101              BNE      |L6.46|
00002a  200a              MOVS     r0,#0xa               ;98
00002c  e7f7              B        |L6.30|
                  |L6.46|
00002e  200b              MOVS     r0,#0xb               ;100
000030  e7f5              B        |L6.30|
;;;103    
                          ENDP

000032  0000              DCW      0x0000
                  |L6.52|
                          DCD      0x40010000
                  |L6.56|
                          DCD      0x40010100
                  |L6.60|
                          DCD      0x40110000

                          AREA ||i.TIMER_Init||, CODE, READONLY, ALIGN=2

                  TIMER_Init PROC
;;;29       */
;;;30     void TIMER_Init(TIMER_TypeDef *timer, uint8_t u8Prescale, uint32_t u32Compare, uint32_t u32Mode)
000000  b570              PUSH     {r4-r6,lr}
;;;31     {
;;;32     	assert_param((u32Compare > 1) && (u32Compare < 0x1000000));
;;;33     	assert_param((u32Mode & ~TIMER_CTL_MODESEL_MASK) == 0);
;;;34     
;;;35     	if(timer == TIMER0)
000002  4d0f              LDR      r5,|L7.64|
;;;36     		CLK->APBCLK |= CLK_APBCLK_TMR0_EN;
000004  4c0f              LDR      r4,|L7.68|
000006  42a8              CMP      r0,r5                 ;35
000008  d102              BNE      |L7.16|
00000a  68a5              LDR      r5,[r4,#8]
00000c  2604              MOVS     r6,#4
00000e  e00c              B        |L7.42|
                  |L7.16|
;;;37     	else if(timer == TIMER1)
000010  4d0d              LDR      r5,|L7.72|
000012  42a8              CMP      r0,r5
000014  d102              BNE      |L7.28|
;;;38     		CLK->APBCLK |= CLK_APBCLK_TMR1_EN;
000016  68a5              LDR      r5,[r4,#8]
000018  2608              MOVS     r6,#8
00001a  e006              B        |L7.42|
                  |L7.28|
;;;39     	else if(timer == TIMER2)
00001c  4d0b              LDR      r5,|L7.76|
00001e  42a8              CMP      r0,r5
;;;40     		CLK->APBCLK |= CLK_APBCLK_TMR2_EN;
;;;41     	else
;;;42     		CLK->APBCLK |= CLK_APBCLK_TMR3_EN;
000020  68a5              LDR      r5,[r4,#8]
000022  d101              BNE      |L7.40|
000024  2610              MOVS     r6,#0x10              ;40
000026  e000              B        |L7.42|
                  |L7.40|
000028  2620              MOVS     r6,#0x20
                  |L7.42|
00002a  4335              ORRS     r5,r5,r6              ;40
00002c  60a5              STR      r5,[r4,#8]            ;40
;;;43     
;;;44     	timer->CTL = 0;
00002e  2400              MOVS     r4,#0
000030  6004              STR      r4,[r0,#0]
;;;45     	timer->ISR = (TIMER_ISR_TMRIS | TIMER_ISR_TCAPIS | TIMER_ISR_TMRWAKESTS | TIMER_ISR_NCAPDETSTS);
000032  2433              MOVS     r4,#0x33
000034  6104              STR      r4,[r0,#0x10]
;;;46     	timer->PRECNT = u8Prescale;
000036  6041              STR      r1,[r0,#4]
;;;47     	timer->CMPR = u32Compare;
000038  6082              STR      r2,[r0,#8]
;;;48     	timer->CTL = u32Mode;
00003a  6003              STR      r3,[r0,#0]
;;;49             return;
;;;50     }
00003c  bd70              POP      {r4-r6,pc}
;;;51     
                          ENDP

00003e  0000              DCW      0x0000
                  |L7.64|
                          DCD      0x40010000
                  |L7.68|
                          DCD      0x50000200
                  |L7.72|
                          DCD      0x40010100
                  |L7.76|
                          DCD      0x40110000

                          AREA ||i.WDT_DeInit||, CODE, READONLY, ALIGN=2

                  WDT_DeInit PROC
;;;178      */
;;;179    void WDT_DeInit(void)
000000  b510              PUSH     {r4,lr}
;;;180    {
;;;181    
;;;182    	WDT->CTL &= ~WDT_CTL_WTE;
000002  480b              LDR      r0,|L8.48|
000004  6801              LDR      r1,[r0,#0]
000006  2208              MOVS     r2,#8
000008  4391              BICS     r1,r1,r2
00000a  6001              STR      r1,[r0,#0]
;;;183    	WDT->IER &= ~WDT_IER_WDTIE;
00000c  6841              LDR      r1,[r0,#4]
00000e  0849              LSRS     r1,r1,#1
000010  0049              LSLS     r1,r1,#1
000012  6041              STR      r1,[r0,#4]
;;;184    
;;;185    	if(!(WWDT->IER & WWDT_IER_IE))
000014  4807              LDR      r0,|L8.52|
000016  6880              LDR      r0,[r0,#8]
000018  07c0              LSLS     r0,r0,#31
00001a  d102              BNE      |L8.34|
;;;186    		NVIC_EnableIRQ(WDT_IRQn);
00001c  2001              MOVS     r0,#1
00001e  f7fffffe          BL       NVIC_EnableIRQ
                  |L8.34|
;;;187    
;;;188            CLK->APBCLK &= ~CLK_APBCLK_WDT_EN;
000022  4805              LDR      r0,|L8.56|
000024  6881              LDR      r1,[r0,#8]
000026  0849              LSRS     r1,r1,#1
000028  0049              LSLS     r1,r1,#1
00002a  6081              STR      r1,[r0,#8]
;;;189    
;;;190    }
00002c  bd10              POP      {r4,pc}
;;;191    
                          ENDP

00002e  0000              DCW      0x0000
                  |L8.48|
                          DCD      0x40004000
                  |L8.52|
                          DCD      0x40004100
                  |L8.56|
                          DCD      0x50000200

                          AREA ||i.WDT_DisableInt||, CODE, READONLY, ALIGN=2

                  WDT_DisableInt PROC
;;;210      */
;;;211    void WDT_DisableInt(void)
000000  b510              PUSH     {r4,lr}
;;;212    {
;;;213    	WDT->IER &= ~WDT_IER_WDTIE;
000002  4806              LDR      r0,|L9.28|
000004  6841              LDR      r1,[r0,#4]
000006  0849              LSRS     r1,r1,#1
000008  0049              LSLS     r1,r1,#1
00000a  6041              STR      r1,[r0,#4]
;;;214    	if(!(WWDT->IER & WWDT_IER_IE))
00000c  4804              LDR      r0,|L9.32|
00000e  6880              LDR      r0,[r0,#8]
000010  07c0              LSLS     r0,r0,#31
000012  d102              BNE      |L9.26|
;;;215    		NVIC_EnableIRQ(WDT_IRQn);
000014  2001              MOVS     r0,#1
000016  f7fffffe          BL       NVIC_EnableIRQ
                  |L9.26|
;;;216    
;;;217    }
00001a  bd10              POP      {r4,pc}
;;;218    
                          ENDP

                  |L9.28|
                          DCD      0x40004000
                  |L9.32|
                          DCD      0x40004100

                          AREA ||i.WDT_EnableInt||, CODE, READONLY, ALIGN=2

                  WDT_EnableInt PROC
;;;197      */
;;;198    void WDT_EnableInt(void)
000000  b510              PUSH     {r4,lr}
;;;199    {
;;;200    	WDT->ISR = WDT_ISR_WDTIS;
000002  4805              LDR      r0,|L10.24|
000004  2101              MOVS     r1,#1
000006  6081              STR      r1,[r0,#8]
;;;201    	WDT->IER |= WDT_IER_WDTIE;
000008  6842              LDR      r2,[r0,#4]
00000a  430a              ORRS     r2,r2,r1
00000c  6042              STR      r2,[r0,#4]
;;;202            NVIC_EnableIRQ(WDT_IRQn);
00000e  4608              MOV      r0,r1
000010  f7fffffe          BL       NVIC_EnableIRQ
;;;203    
;;;204    }
000014  bd10              POP      {r4,pc}
;;;205    
                          ENDP

000016  0000              DCW      0x0000
                  |L10.24|
                          DCD      0x40004000

                          AREA ||i.WDT_Init||, CODE, READONLY, ALIGN=2

                  WDT_Init PROC
;;;161      */
;;;162    void WDT_Init(uint32_t u32Interval, uint32_t u32Delay)
000000  b510              PUSH     {r4,lr}
;;;163    {
;;;164    	uint32_t reg;
;;;165    	assert_param((u32Interval & ~WDT_CTL_WTIS_MASK) == 0);
;;;166    	assert_param((u32Delay & ~WDT_CTL_WTRDSEL_MASK) == 0);
;;;167    
;;;168            CLK->APBCLK |= CLK_APBCLK_WDT_EN;
000002  4a07              LDR      r2,|L11.32|
000004  6893              LDR      r3,[r2,#8]
000006  2401              MOVS     r4,#1
000008  4323              ORRS     r3,r3,r4
00000a  6093              STR      r3,[r2,#8]
;;;169            reg = WDT->CTL;
00000c  4b05              LDR      r3,|L11.36|
00000e  681a              LDR      r2,[r3,#0]
;;;170            reg &= ~(WDT_CTL_WTIS_MASK | WDT_CTL_WTRDSEL_MASK);
000010  2437              MOVS     r4,#0x37
000012  0124              LSLS     r4,r4,#4
000014  43a2              BICS     r2,r2,r4
;;;171            WDT->CTL = reg | u32Interval | u32Delay;
000016  4302              ORRS     r2,r2,r0
000018  430a              ORRS     r2,r2,r1
00001a  601a              STR      r2,[r3,#0]
;;;172    }
00001c  bd10              POP      {r4,pc}
;;;173    
                          ENDP

00001e  0000              DCW      0x0000
                  |L11.32|
                          DCD      0x50000200
                  |L11.36|
                          DCD      0x40004000

                          AREA ||i.WWDT_DeInit||, CODE, READONLY, ALIGN=1

                  WWDT_DeInit PROC
;;;242      */
;;;243    void WWDT_DeInit(void)
000000  4770              BX       lr
;;;244    {
;;;245            return;
;;;246    }
;;;247    
                          ENDP


                          AREA ||i.WWDT_EnableInterrupt||, CODE, READONLY, ALIGN=2

                  WWDT_EnableInterrupt PROC
;;;274      */
;;;275    void WWDT_EnableInterrupt(void)
000000  b510              PUSH     {r4,lr}
;;;276    {
;;;277    
;;;278            WWDT->STS = WWDT_STS_IF;	// clear pending interrupt, if any
000002  4804              LDR      r0,|L13.20|
000004  2101              MOVS     r1,#1
000006  60c1              STR      r1,[r0,#0xc]
;;;279            WWDT->IER = WWDT_IER_IE;
000008  6081              STR      r1,[r0,#8]
;;;280    
;;;281            NVIC_EnableIRQ(WDT_IRQn);
00000a  4608              MOV      r0,r1
00000c  f7fffffe          BL       NVIC_EnableIRQ
;;;282    
;;;283            return;
;;;284    }
000010  bd10              POP      {r4,pc}
;;;285    
                          ENDP

000012  0000              DCW      0x0000
                  |L13.20|
                          DCD      0x40004100

                          AREA ||i.WWDT_Init||, CODE, READONLY, ALIGN=2

                  WWDT_Init PROC
;;;226      */
;;;227    void WWDT_Init(uint32_t u32Prescale, uint8_t u8Cmp)
000000  b510              PUSH     {r4,lr}
;;;228    {
;;;229            assert_param(u8Cmp < 64);
;;;230            assert_param((u32Prescale & ~WWDT_CR_PERIODSEL_MASK) == 0);
;;;231    
;;;232            CLK->APBCLK |= CLK_APBCLK_WDT_EN;
000002  4a05              LDR      r2,|L14.24|
000004  6893              LDR      r3,[r2,#8]
000006  2401              MOVS     r4,#1
000008  4323              ORRS     r3,r3,r4
00000a  6093              STR      r3,[r2,#8]
;;;233            WWDT->CR = u32Prescale | (u8Cmp << 16) | 1;
00000c  0409              LSLS     r1,r1,#16
00000e  4301              ORRS     r1,r1,r0
000010  4802              LDR      r0,|L14.28|
000012  4321              ORRS     r1,r1,r4
000014  6041              STR      r1,[r0,#4]
;;;234    
;;;235            return;
;;;236    }
000016  bd10              POP      {r4,pc}
;;;237    
                          ENDP

                  |L14.24|
                          DCD      0x50000200
                  |L14.28|
                          DCD      0x40004100

                          AREA ||i.WWDT_IsResetSource||, CODE, READONLY, ALIGN=2

                  WWDT_IsResetSource PROC
;;;256      */
;;;257    uint8_t WWDT_IsResetSource(void)
000000  4904              LDR      r1,|L15.20|
;;;258    {
;;;259            int8_t ret = (WWDT->STS & WWDT_STS_RF) ? 1 : 0;
000002  68c8              LDR      r0,[r1,#0xc]
000004  0780              LSLS     r0,r0,#30
000006  0fc0              LSRS     r0,r0,#31
;;;260    
;;;261            if(ret)
000008  d001              BEQ      |L15.14|
;;;262                    WWDT->STS = WWDT_STS_RF;
00000a  2202              MOVS     r2,#2
00000c  60ca              STR      r2,[r1,#0xc]
                  |L15.14|
;;;263    
;;;264            return(ret);
00000e  b2c0              UXTB     r0,r0
;;;265    
;;;266    }
000010  4770              BX       lr
;;;267    
                          ENDP

000012  0000              DCW      0x0000
                  |L15.20|
                          DCD      0x40004100

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_timer.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_nano1xx_timer_c_39e8134a____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___15_nano1xx_timer_c_39e8134a____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___15_nano1xx_timer_c_39e8134a____REVSH|
#line 130
|__asm___15_nano1xx_timer_c_39e8134a____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
