; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\system_nuc1xx.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_nuc1xx.d --cpu=Cortex-M0 --apcs=interwork -O0 -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\system_nuc1xx.crf ..\bsp\Cmsis\system_NUC1xx.c]
                          THUMB

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;21      *----------------------------------------------------------------------------*/
;;;22     void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
000000  b570              PUSH     {r4-r6,lr}
;;;23     {
;;;24         uint32_t u32CoreFreq, u32ClkSrc, u32Shift;
;;;25      
;;;26         u32ClkSrc = SYSCLK->CLKSEL0.HCLK_S;
000002  4820              LDR      r0,|L1.132|
000004  6900              LDR      r0,[r0,#0x10]
000006  0746              LSLS     r6,r0,#29
000008  0f76              LSRS     r6,r6,#29
;;;27         if(u32ClkSrc > sizeof(gau32ClkSrcTbl)/sizeof(gau32ClkSrcTbl[0]))
00000a  2e05              CMP      r6,#5
00000c  d900              BLS      |L1.16|
;;;28             u32ClkSrc = sizeof(gau32ClkSrcTbl)/sizeof(gau32ClkSrcTbl[0]) - 1; 
00000e  2604              MOVS     r6,#4
                  |L1.16|
;;;29         
;;;30         if(u32ClkSrc != 2)
000010  2e02              CMP      r6,#2
000012  d003              BEQ      |L1.28|
;;;31         {
;;;32             /* Use the clock sources directly */
;;;33             u32CoreFreq = gau32ClkSrcTbl[u32ClkSrc];
000014  00b0              LSLS     r0,r6,#2
000016  491c              LDR      r1,|L1.136|
000018  580d              LDR      r5,[r1,r0]
00001a  e01e              B        |L1.90|
                  |L1.28|
;;;34         }
;;;35         else
;;;36         {
;;;37             /* Use PLL */
;;;38             u32Shift = SYSCLK->PLLCON.OUT_DV;   /* OUT_DV :DEF: {1, 2, 2, 4} */
00001c  4819              LDR      r0,|L1.132|
00001e  6a00              LDR      r0,[r0,#0x20]
000020  0400              LSLS     r0,r0,#16
000022  0f84              LSRS     r4,r0,#30
;;;39             if(u32Shift > 1) u32Shift--;
000024  2c01              CMP      r4,#1
000026  d900              BLS      |L1.42|
000028  1e64              SUBS     r4,r4,#1
                  |L1.42|
;;;40             u32CoreFreq = ((SYSCLK->PLLCON.PLL_SRC)?__IRC22M:__XTAL) * (SYSCLK->PLLCON.FB_DV+2) / (SYSCLK->PLLCON.IN_DV+2) >> u32Shift;
00002a  4a16              LDR      r2,|L1.132|
00002c  6a12              LDR      r2,[r2,#0x20]
00002e  0312              LSLS     r2,r2,#12
000030  0fd2              LSRS     r2,r2,#31
000032  d001              BEQ      |L1.56|
000034  4a15              LDR      r2,|L1.140|
000036  e000              B        |L1.58|
                  |L1.56|
000038  4a15              LDR      r2,|L1.144|
                  |L1.58|
00003a  4b12              LDR      r3,|L1.132|
00003c  6a1b              LDR      r3,[r3,#0x20]
00003e  05db              LSLS     r3,r3,#23
000040  0ddb              LSRS     r3,r3,#23
000042  1c9b              ADDS     r3,r3,#2
000044  4610              MOV      r0,r2
000046  4358              MULS     r0,r3,r0
000048  4a0e              LDR      r2,|L1.132|
00004a  6a12              LDR      r2,[r2,#0x20]
00004c  0492              LSLS     r2,r2,#18
00004e  0ed2              LSRS     r2,r2,#27
000050  1c91              ADDS     r1,r2,#2
000052  f7fffffe          BL       __aeabi_uidivmod
000056  40e0              LSRS     r0,r0,r4
000058  4605              MOV      r5,r0
                  |L1.90|
;;;41         }
;;;42      
;;;43         SystemCoreClock = (u32CoreFreq/(SYSCLK->CLKDIV.HCLK_N + 1));
00005a  480a              LDR      r0,|L1.132|
00005c  6980              LDR      r0,[r0,#0x18]
00005e  0700              LSLS     r0,r0,#28
000060  0f00              LSRS     r0,r0,#28
000062  1c41              ADDS     r1,r0,#1
000064  4628              MOV      r0,r5
000066  f7fffffe          BL       __aeabi_uidivmod
00006a  490a              LDR      r1,|L1.148|
00006c  6008              STR      r0,[r1,#0]  ; SystemCoreClock
;;;44         CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
00006e  490a              LDR      r1,|L1.152|
000070  4808              LDR      r0,|L1.148|
000072  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
000074  104a              ASRS     r2,r1,#1
000076  1880              ADDS     r0,r0,r2
000078  f7fffffe          BL       __aeabi_uidivmod
00007c  4907              LDR      r1,|L1.156|
00007e  6008              STR      r0,[r1,#0]  ; CyclesPerUs
;;;45     }
000080  bd70              POP      {r4-r6,pc}
;;;46     
                          ENDP

000082  0000              DCW      0x0000
                  |L1.132|
                          DCD      0x50000200
                  |L1.136|
                          DCD      gau32ClkSrcTbl
                  |L1.140|
                          DCD      0x01518000
                  |L1.144|
                          DCD      0x00b71b00
                  |L1.148|
                          DCD      SystemCoreClock
                  |L1.152|
                          DCD      0x000f4240
                  |L1.156|
                          DCD      CyclesPerUs

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=1

                  SystemInit PROC
;;;59     /*---------------------------------------------------------------------------------------------------------*/
;;;60     void SystemInit (void)
000000  4770              BX       lr
;;;61     {
;;;62     
;;;63     }
;;;64     
                          ENDP


                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x01518000
                  CyclesPerUs
                          DCD      0x00000016
                  gau32ClkSrcTbl
                          DCD      0x00b71b00
                          DCD      0x00008000
                          DCD      0x01518000
                          DCD      0x00002710
                          DCD      0x01518000
