; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\drvpdma.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvpdma.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvpdma.crf ..\bsp\Driver\DrvPDMA.c]
                          THUMB

                          AREA ||i.DrvPDMA_CHEnableTransfer||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CHEnableTransfer PROC
;;;410    /*---------------------------------------------------------------------------------------------------------*/
;;;411    int32_t	DrvPDMA_CHEnableTransfer(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4904              LDR      r1,|L1.20|
;;;412    {
;;;413     	PDMA_TypeDef *base;
;;;414    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;415    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;416    
;;;417    	base->CSR |= 0x800001;
000006  6801              LDR      r1,[r0,#0]
000008  4a03              LDR      r2,|L1.24|
00000a  4311              ORRS     r1,r1,r2
00000c  6001              STR      r1,[r0,#0]
;;;418    
;;;419        return E_SUCCESS;
00000e  2000              MOVS     r0,#0
;;;420    }
000010  4770              BX       lr
;;;421    
                          ENDP

000012  0000              DCW      0x0000
                  |L1.20|
                          DCD      0x50008000
                  |L1.24|
                          DCD      0x00800001

                          AREA ||i.DrvPDMA_CHSoftwareReset||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CHSoftwareReset PROC
;;;387    /*---------------------------------------------------------------------------------------------------------*/
;;;388    int32_t DrvPDMA_CHSoftwareReset(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4904              LDR      r1,|L2.20|
;;;389    {
;;;390     	PDMA_TypeDef *base;
;;;391    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;392    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;393    
;;;394    	base->CSR_BITS.SW_RST = 1;
000006  6801              LDR      r1,[r0,#0]
000008  2202              MOVS     r2,#2
00000a  4311              ORRS     r1,r1,r2
00000c  6001              STR      r1,[r0,#0]
;;;395    
;;;396        return E_SUCCESS;
00000e  2000              MOVS     r0,#0
;;;397    }
000010  4770              BX       lr
;;;398    
                          ENDP

000012  0000              DCW      0x0000
                  |L2.20|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_CRCClearIntFlag||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCClearIntFlag PROC
;;;993    /*---------------------------------------------------------------------------------------------------------*/
;;;994    void DrvPDMA_CRCClearIntFlag(E_DRVPDMA_INT_FLAG eIntFlag)
000000  4902              LDR      r1,|L3.12|
;;;995    {
;;;996    	PDMACRC->DMAISR |= eIntFlag;
000002  6a4a              LDR      r2,[r1,#0x24]
000004  4302              ORRS     r2,r2,r0
000006  624a              STR      r2,[r1,#0x24]
;;;997    }
000008  4770              BX       lr
;;;998    						  
                          ENDP

00000a  0000              DCW      0x0000
                  |L3.12|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_CRCDisableInt||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCDisableInt PROC
;;;976    /*---------------------------------------------------------------------------------------------------------*/
;;;977    int32_t DrvPDMA_CRCDisableInt(E_DRVPDMA_INT_ENABLE eIntSource)
000000  4902              LDR      r1,|L4.12|
;;;978    {
;;;979    	PDMACRC->DMAIER &= ~eIntSource;
000002  6a0a              LDR      r2,[r1,#0x20]
000004  4382              BICS     r2,r2,r0
000006  620a              STR      r2,[r1,#0x20]
;;;980    
;;;981    	return E_SUCCESS;
000008  2000              MOVS     r0,#0
;;;982    }
00000a  4770              BX       lr
;;;983    
                          ENDP

                  |L4.12|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_CRCEnableInt||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCEnableInt PROC
;;;954    /*---------------------------------------------------------------------------------------------------------*/
;;;955    int32_t DrvPDMA_CRCEnableInt(E_DRVPDMA_INT_ENABLE eIntSource)
000000  4904              LDR      r1,|L5.20|
;;;956    {
;;;957    	assert_param(CHECK_CRC_INT(eIntSource));
;;;958    
;;;959    	PDMACRC->DMAIER |= eIntSource;
000002  6a0a              LDR      r2,[r1,#0x20]
000004  4302              ORRS     r2,r2,r0
000006  620a              STR      r2,[r1,#0x20]
000008  2001              MOVS     r0,#1
00000a  4903              LDR      r1,|L5.24|
00000c  0680              LSLS     r0,r0,#26
00000e  6008              STR      r0,[r1,#0]
;;;960    
;;;961        /* Enable Specified Interrupt */
;;;962    	NVIC_EnableIRQ(PDMA_IRQn);
;;;963    
;;;964        return E_SUCCESS;
000010  2000              MOVS     r0,#0
;;;965    }
000012  4770              BX       lr
;;;966    
                          ENDP

                  |L5.20|
                          DCD      0x50008e00
                  |L5.24|
                          DCD      0xe000e100

                          AREA ||i.DrvPDMA_CRCEnablelTransfer||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCEnablelTransfer PROC
;;;935    /*---------------------------------------------------------------------------------------------------------*/
;;;936    int32_t	DrvPDMA_CRCEnablelTransfer(void)
000000  4803              LDR      r0,|L6.16|
;;;937    {
;;;938    
;;;939    	PDMACRC->CTL |= 0x800001;
000002  6801              LDR      r1,[r0,#0]
000004  4a03              LDR      r2,|L6.20|
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;940    
;;;941        return E_SUCCESS;
00000a  2000              MOVS     r0,#0
;;;942    }
00000c  4770              BX       lr
;;;943    
                          ENDP

00000e  0000              DCW      0x0000
                  |L6.16|
                          DCD      0x50008e00
                  |L6.20|
                          DCD      0x00800001

                          AREA ||i.DrvPDMA_CRCGetChecksum||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCGetChecksum PROC
;;;1121   /*---------------------------------------------------------------------------------------------------------*/
;;;1122   uint32_t DrvPDMA_CRCGetChecksum(void)
000000  4902              LDR      r1,|L7.12|
;;;1123   {
;;;1124   	return PDMACRC->CHECKSUM & PDMACRC->SEED;
000002  6888              LDR      r0,[r1,#8]
000004  6849              LDR      r1,[r1,#4]
000006  4008              ANDS     r0,r0,r1
;;;1125   }
000008  4770              BX       lr
;;;1126   
                          ENDP

00000a  0000              DCW      0x0000
                  |L7.12|
                          DCD      0x50008e80

                          AREA ||i.DrvPDMA_CRCGetWriteData||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCGetWriteData PROC
;;;1089   /*---------------------------------------------------------------------------------------------------------*/
;;;1090   uint32_t DrvPDMA_CRCGetWriteData(void)
000000  4801              LDR      r0,|L8.8|
;;;1091   {
;;;1092   	return PDMACRC->WDATA;
000002  6800              LDR      r0,[r0,#0]
;;;1093   }
000004  4770              BX       lr
;;;1094   
                          ENDP

000006  0000              DCW      0x0000
                  |L8.8|
                          DCD      0x50008e80

                          AREA ||i.DrvPDMA_CRCInstallCallBack||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCInstallCallBack PROC
;;;1029   /*---------------------------------------------------------------------------------------------------------*/
;;;1030   int32_t DrvPDMA_CRCInstallCallBack(E_DRVPDMA_INT_ENABLE eIntSource, PFN_DRVPDMA_CRC_CALLBACK pfncallback)
000000  0782              LSLS     r2,r0,#30
;;;1031   {
;;;1032   	assert_param(CHECK_CRC_INT(eIntSource));
;;;1033   	assert_param(CHECK_DMA_INTCALLBACK(pfncallback));
;;;1034   
;;;1035   	if (eIntSource & 0x3)
000002  d003              BEQ      |L9.12|
;;;1036   		g_pfnPDMACRCCallback[eIntSource >> 1] = pfncallback;	       /* Install Callback funtion */
000004  0840              LSRS     r0,r0,#1
000006  4a02              LDR      r2,|L9.16|
000008  0080              LSLS     r0,r0,#2
00000a  5011              STR      r1,[r2,r0]
                  |L9.12|
;;;1037   
;;;1038       return E_SUCCESS;
00000c  2000              MOVS     r0,#0
;;;1039   }
00000e  4770              BX       lr
;;;1040   
                          ENDP

                  |L9.16|
                          DCD      ||.data||

                          AREA ||i.DrvPDMA_CRCPollInt||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCPollInt PROC
;;;1010   /*---------------------------------------------------------------------------------------------------------*/
;;;1011   int32_t	DrvPDMA_CRCPollInt(E_DRVPDMA_INT_FLAG eIntFlag)
000000  4903              LDR      r1,|L10.16|
;;;1012   {
;;;1013   	assert_param(CHECK_CRC_INT(eIntFlag));
;;;1014   
;;;1015   	return (PDMACRC->DMAISR & eIntFlag)? TRUE: FALSE;
000002  6a49              LDR      r1,[r1,#0x24]
000004  4201              TST      r1,r0
000006  d001              BEQ      |L10.12|
000008  2001              MOVS     r0,#1
;;;1016   }
00000a  4770              BX       lr
                  |L10.12|
00000c  2000              MOVS     r0,#0                 ;1015
00000e  4770              BX       lr
;;;1017   
                          ENDP

                  |L10.16|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_CRCSetSeed||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCSetSeed PROC
;;;1104   /*---------------------------------------------------------------------------------------------------------*/
;;;1105   int32_t DrvPDMA_CRCSetSeed(uint32_t u32Data)
000000  4901              LDR      r1,|L11.8|
;;;1106   {
;;;1107   	PDMACRC->SEED = u32Data;
000002  6048              STR      r0,[r1,#4]
;;;1108   
;;;1109       return E_SUCCESS;
000004  2000              MOVS     r0,#0
;;;1110   }
000006  4770              BX       lr
;;;1111   
                          ENDP

                  |L11.8|
                          DCD      0x50008e80

                          AREA ||i.DrvPDMA_CRCSetWriteData||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCSetWriteData PROC
;;;1072   /*---------------------------------------------------------------------------------------------------------*/
;;;1073   int32_t DrvPDMA_CRCSetWriteData(uint32_t u32Data)
000000  4901              LDR      r1,|L12.8|
;;;1074   {
;;;1075   	PDMACRC->WDATA = u32Data;
000002  6008              STR      r0,[r1,#0]
;;;1076   
;;;1077       return E_SUCCESS;
000004  2000              MOVS     r0,#0
;;;1078   }
000006  4770              BX       lr
;;;1079   
                          ENDP

                  |L12.8|
                          DCD      0x50008e80

                          AREA ||i.DrvPDMA_CRCSoftwareReset||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCSoftwareReset PROC
;;;917    /*---------------------------------------------------------------------------------------------------------*/
;;;918    int32_t DrvPDMA_CRCSoftwareReset(void)
000000  4803              LDR      r0,|L13.16|
;;;919    {
;;;920    	PDMACRC->CTL_BITS.RST = 1;
000002  6801              LDR      r1,[r0,#0]
000004  2202              MOVS     r2,#2
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;921    
;;;922        return E_SUCCESS;
00000a  2000              MOVS     r0,#0
;;;923    }
00000c  4770              BX       lr
;;;924    
                          ENDP

00000e  0000              DCW      0x0000
                  |L13.16|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_CRCUnInstallCallBack||, CODE, READONLY, ALIGN=2

                  DrvPDMA_CRCUnInstallCallBack PROC
;;;1052   /*---------------------------------------------------------------------------------------------------------*/
;;;1053   int32_t DrvPDMA_CRCUnInstallCallBack(E_DRVPDMA_INT_ENABLE eIntSource)
000000  0781              LSLS     r1,r0,#30
;;;1054   {
;;;1055   	assert_param(CHECK_CRC_INT(eIntSource));
;;;1056   
;;;1057   	if (eIntSource & 0x3)
000002  d004              BEQ      |L14.14|
;;;1058   		g_pfnPDMACRCCallback[eIntSource >> 1] = 0;	   /* Install Callback funtion */
000004  2100              MOVS     r1,#0
000006  0840              LSRS     r0,r0,#1
000008  4a02              LDR      r2,|L14.20|
00000a  0080              LSLS     r0,r0,#2
00000c  5011              STR      r1,[r2,r0]
                  |L14.14|
;;;1059   
;;;1060       return E_SUCCESS;
00000e  2000              MOVS     r0,#0
;;;1061   }
000010  4770              BX       lr
;;;1062   
                          ENDP

000012  0000              DCW      0x0000
                  |L14.20|
                          DCD      ||.data||

                          AREA ||i.DrvPDMA_ClearIntFlag||, CODE, READONLY, ALIGN=2

                  DrvPDMA_ClearIntFlag PROC
;;;506    /*---------------------------------------------------------------------------------------------------------*/
;;;507    void DrvPDMA_ClearIntFlag(E_DRVPDMA_CHANNEL_INDEX eChannel,E_DRVPDMA_INT_FLAG eIntFlag)
000000  4a03              LDR      r2,|L15.16|
;;;508    {
;;;509     	PDMA_TypeDef *base;
;;;510    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;511    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;512    
;;;513    	base->ISR |= eIntFlag;
000006  6a42              LDR      r2,[r0,#0x24]
000008  430a              ORRS     r2,r2,r1
00000a  6242              STR      r2,[r0,#0x24]
;;;514    }
00000c  4770              BX       lr
;;;515    						  
                          ENDP

00000e  0000              DCW      0x0000
                  |L15.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_Close||, CODE, READONLY, ALIGN=2

                  DrvPDMA_Close PROC
;;;162    /*---------------------------------------------------------------------------------------------------------*/
;;;163    void DrvPDMA_Close(void)
000000  b510              PUSH     {r4,lr}
;;;164    {
;;;165       	/* Disable All PDMA clock */
;;;166    	PDMAGCR->CSR = 0;
000002  4808              LDR      r0,|L16.36|
000004  2300              MOVS     r3,#0
000006  6003              STR      r3,[r0,#0]
;;;167    
;;;168    	/* Disable PDMA clock */
;;;169    	UNLOCKREG();
000008  4807              LDR      r0,|L16.40|
00000a  2159              MOVS     r1,#0x59
00000c  6001              STR      r1,[r0,#0]
00000e  2116              MOVS     r1,#0x16
000010  6001              STR      r1,[r0,#0]
000012  2188              MOVS     r1,#0x88
000014  6001              STR      r1,[r0,#0]
;;;170    	CLK->AHBCLK_BITS.PDMA_EN = 0;
000016  4905              LDR      r1,|L16.44|
000018  684a              LDR      r2,[r1,#4]
00001a  2402              MOVS     r4,#2
00001c  43a2              BICS     r2,r2,r4
00001e  604a              STR      r2,[r1,#4]
;;;171    	LOCKREG();
000020  6003              STR      r3,[r0,#0]
;;;172    }
000022  bd10              POP      {r4,pc}
;;;173    
                          ENDP

                  |L16.36|
                          DCD      0x50008f00
                  |L16.40|
                          DCD      0x50000100
                  |L16.44|
                          DCD      0x50000200

                          AREA ||i.DrvPDMA_DisableInt||, CODE, READONLY, ALIGN=2

                  DrvPDMA_DisableInt PROC
;;;461    
;;;462    int32_t DrvPDMA_DisableInt(E_DRVPDMA_CHANNEL_INDEX eChannel,E_DRVPDMA_INT_ENABLE eIntSource)
000000  4a03              LDR      r2,|L17.16|
;;;463    {
;;;464     	PDMA_TypeDef *base;
;;;465    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;466    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;467    
;;;468    	base->IER &= ~eIntSource;
000006  6a02              LDR      r2,[r0,#0x20]
000008  438a              BICS     r2,r2,r1
00000a  6202              STR      r2,[r0,#0x20]
;;;469    
;;;470    	return E_SUCCESS;
00000c  2000              MOVS     r0,#0
;;;471    }
00000e  4770              BX       lr
;;;472    
                          ENDP

                  |L17.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_EnableInt||, CODE, READONLY, ALIGN=2

                  DrvPDMA_EnableInt PROC
;;;434    /*---------------------------------------------------------------------------------------------------------*/
;;;435    int32_t DrvPDMA_EnableInt(E_DRVPDMA_CHANNEL_INDEX eChannel,E_DRVPDMA_INT_ENABLE eIntSource)
000000  4a05              LDR      r2,|L18.24|
;;;436    {
;;;437     	PDMA_TypeDef *base;
;;;438    	assert_param(CHECK_DMA_INT(eChannel, eIntSource));
;;;439    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;440    
;;;441    	base->IER |= eIntSource;
000006  6a02              LDR      r2,[r0,#0x20]
000008  430a              ORRS     r2,r2,r1
00000a  6202              STR      r2,[r0,#0x20]
00000c  2001              MOVS     r0,#1
00000e  4903              LDR      r1,|L18.28|
000010  0680              LSLS     r0,r0,#26
000012  6008              STR      r0,[r1,#0]
;;;442    
;;;443        /* Enable Specified Interrupt */
;;;444    	NVIC_EnableIRQ(PDMA_IRQn);
;;;445    
;;;446        return E_SUCCESS;
000014  2000              MOVS     r0,#0
;;;447    }
000016  4770              BX       lr
;;;448    
                          ENDP

                  |L18.24|
                          DCD      0x50008000
                  |L18.28|
                          DCD      0xe000e100

                          AREA ||i.DrvPDMA_GetAPBTransferWidth||, CODE, READONLY, ALIGN=2

                  DrvPDMA_GetAPBTransferWidth PROC
;;;368    /*---------------------------------------------------------------------------------------------------------*/
;;;369    int32_t DrvPDMA_GetAPBTransferWidth(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4903              LDR      r1,|L19.16|
;;;370    {
;;;371     	PDMA_TypeDef *base;
;;;372    	assert_param(CHECK_PDMA_CHANNEL(eChannel));
;;;373    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;374    
;;;375    	return (int32_t)(base->CSR_BITS.APB_TWS);	/* Get Transfer Length */
000006  6800              LDR      r0,[r0,#0]
000008  02c0              LSLS     r0,r0,#11
00000a  0f80              LSRS     r0,r0,#30
;;;376    }
00000c  4770              BX       lr
;;;377    
                          ENDP

00000e  0000              DCW      0x0000
                  |L19.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_GetCHForAPBDevice||, CODE, READONLY, ALIGN=2

                  DrvPDMA_GetCHForAPBDevice PROC
;;;744    /*---------------------------------------------------------------------------------------------------------*/
;;;745    int32_t DrvPDMA_GetCHForAPBDevice(E_DRVPDMA_APB_DEVICE eDevice,E_DRVPDMA_APB_RW eRWAPB)
000000  4916              LDR      r1,|L20.92|
;;;746    {
;;;747    	if (eDevice == PDMAGCR->PDSSR0_BITS.CH1_SEL)
000002  684a              LDR      r2,[r1,#4]
000004  04d2              LSLS     r2,r2,#19
000006  0ed2              LSRS     r2,r2,#27
000008  4282              CMP      r2,r0
00000a  d101              BNE      |L20.16|
;;;748    		return eDRVPDMA_CHANNEL_1;
00000c  2001              MOVS     r0,#1
;;;749    	else if (eDevice == PDMAGCR->PDSSR0_BITS.CH2_SEL)
;;;750    		return eDRVPDMA_CHANNEL_2;
;;;751    	else if (eDevice == PDMAGCR->PDSSR0_BITS.CH3_SEL)
;;;752    		return eDRVPDMA_CHANNEL_3;
;;;753    	else if (eDevice == PDMAGCR->PDSSR1_BITS.CH4_SEL)
;;;754    		return eDRVPDMA_CHANNEL_4;
;;;755    	else if (eDevice == PDMAGCR->PDSSR1_BITS.CH5_SEL)
;;;756    		return eDRVPDMA_CHANNEL_5;
;;;757    	else if (eDevice == PDMAGCR->PDSSR1_BITS.CH6_SEL)
;;;758    		return eDRVPDMA_CHANNEL_6;
;;;759    	else
;;;760    		return -1;
;;;761    }
00000e  4770              BX       lr
                  |L20.16|
000010  684a              LDR      r2,[r1,#4]            ;749
000012  02d2              LSLS     r2,r2,#11             ;749
000014  0ed2              LSRS     r2,r2,#27             ;749
000016  4282              CMP      r2,r0                 ;749
000018  d101              BNE      |L20.30|
00001a  2002              MOVS     r0,#2                 ;750
00001c  4770              BX       lr
                  |L20.30|
00001e  684a              LDR      r2,[r1,#4]            ;751
000020  00d2              LSLS     r2,r2,#3              ;751
000022  0ed2              LSRS     r2,r2,#27             ;751
000024  4282              CMP      r2,r0                 ;751
000026  d101              BNE      |L20.44|
000028  2003              MOVS     r0,#3                 ;752
00002a  4770              BX       lr
                  |L20.44|
00002c  688a              LDR      r2,[r1,#8]            ;753
00002e  06d2              LSLS     r2,r2,#27             ;753
000030  0ed2              LSRS     r2,r2,#27             ;753
000032  4282              CMP      r2,r0                 ;753
000034  d101              BNE      |L20.58|
000036  2004              MOVS     r0,#4                 ;754
000038  4770              BX       lr
                  |L20.58|
00003a  688a              LDR      r2,[r1,#8]            ;755
00003c  04d2              LSLS     r2,r2,#19             ;755
00003e  0ed2              LSRS     r2,r2,#27             ;755
000040  4282              CMP      r2,r0                 ;755
000042  d101              BNE      |L20.72|
000044  2005              MOVS     r0,#5                 ;756
000046  4770              BX       lr
                  |L20.72|
000048  6889              LDR      r1,[r1,#8]            ;757
00004a  02c9              LSLS     r1,r1,#11             ;757
00004c  0ec9              LSRS     r1,r1,#27             ;757
00004e  4281              CMP      r1,r0                 ;757
000050  d101              BNE      |L20.86|
000052  2006              MOVS     r0,#6                 ;758
000054  4770              BX       lr
                  |L20.86|
000056  2000              MOVS     r0,#0                 ;760
000058  43c0              MVNS     r0,r0                 ;760
00005a  4770              BX       lr
;;;762    
                          ENDP

                  |L20.92|
                          DCD      0x50008f00

                          AREA ||i.DrvPDMA_GetCurrentDestAddr||, CODE, READONLY, ALIGN=2

                  DrvPDMA_GetCurrentDestAddr PROC
;;;670    /*---------------------------------------------------------------------------------------------------------*/
;;;671    uint32_t DrvPDMA_GetCurrentDestAddr(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4902              LDR      r1,|L21.12|
;;;672    {
;;;673     	PDMA_TypeDef *base;
;;;674    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;675    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;676    
;;;677    	return base->CDAR;
000006  6980              LDR      r0,[r0,#0x18]
;;;678    }
000008  4770              BX       lr
;;;679    
                          ENDP

00000a  0000              DCW      0x0000
                  |L21.12|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_GetCurrentSourceAddr||, CODE, READONLY, ALIGN=2

                  DrvPDMA_GetCurrentSourceAddr PROC
;;;651    /*---------------------------------------------------------------------------------------------------------*/
;;;652    uint32_t DrvPDMA_GetCurrentSourceAddr(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4902              LDR      r1,|L22.12|
;;;653    {
;;;654     	PDMA_TypeDef *base;
;;;655    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;656    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;657    
;;;658    	return base->CSAR;
000006  6940              LDR      r0,[r0,#0x14]
;;;659    }
000008  4770              BX       lr
;;;660    
                          ENDP

00000a  0000              DCW      0x0000
                  |L22.12|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_GetRemainTransferCount||, CODE, READONLY, ALIGN=2

                  DrvPDMA_GetRemainTransferCount PROC
;;;689    /*---------------------------------------------------------------------------------------------------------*/
;;;690    uint32_t DrvPDMA_GetRemainTransferCount(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4902              LDR      r1,|L23.12|
;;;691    {
;;;692     	PDMA_TypeDef *base;
;;;693    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;694    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;695    
;;;696    	return base->CBCR;
000006  69c0              LDR      r0,[r0,#0x1c]
;;;697    }
000008  4770              BX       lr
;;;698    
                          ENDP

00000a  0000              DCW      0x0000
                  |L23.12|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_GetSharedBufData||, CODE, READONLY, ALIGN=2

                  DrvPDMA_GetSharedBufData PROC
;;;548    /*---------------------------------------------------------------------------------------------------------*/
;;;549    uint32_t DrvPDMA_GetSharedBufData(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4902              LDR      r1,|L24.12|
;;;550    {
;;;551     	PDMA_TypeDef *base;
;;;552    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;553    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;554    
;;;555    	return base->BUF0;
000006  3080              ADDS     r0,r0,#0x80
000008  6800              LDR      r0,[r0,#0]
;;;556    }
00000a  4770              BX       lr
;;;557    
                          ENDP

                  |L24.12|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_GetTransferLength||, CODE, READONLY, ALIGN=2

                  DrvPDMA_GetTransferLength PROC
;;;319    /*---------------------------------------------------------------------------------------------------------*/
;;;320    int32_t DrvPDMA_GetTransferLength(E_DRVPDMA_CHANNEL_INDEX eChannel, uint32_t* pu32TransferLength)
000000  4a03              LDR      r2,|L25.16|
;;;321    {
;;;322    	PDMA_TypeDef *base;
;;;323    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;324    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;325    
;;;326    	*pu32TransferLength = base->BCR;		/* Get Transfer Length */
000006  68c0              LDR      r0,[r0,#0xc]
;;;327    
;;;328        return E_SUCCESS;
000008  6008              STR      r0,[r1,#0]
00000a  2000              MOVS     r0,#0
;;;329    }
00000c  4770              BX       lr
;;;330    
                          ENDP

00000e  0000              DCW      0x0000
                  |L25.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_Init||, CODE, READONLY, ALIGN=2

                  DrvPDMA_Init PROC
;;;142    /*---------------------------------------------------------------------------------------------------------*/
;;;143    void DrvPDMA_Init(void)
000000  4807              LDR      r0,|L26.32|
;;;144    {
;;;145        UNLOCKREG();
000002  2159              MOVS     r1,#0x59
000004  6001              STR      r1,[r0,#0]
000006  2116              MOVS     r1,#0x16
000008  6001              STR      r1,[r0,#0]
00000a  2188              MOVS     r1,#0x88
00000c  6001              STR      r1,[r0,#0]
;;;146    
;;;147    	/* Enable PDMA Clock */
;;;148    	CLK->AHBCLK_BITS.PDMA_EN = 1;
00000e  4905              LDR      r1,|L26.36|
000010  684a              LDR      r2,[r1,#4]
000012  2302              MOVS     r3,#2
000014  431a              ORRS     r2,r2,r3
000016  604a              STR      r2,[r1,#4]
;;;149    
;;;150    	LOCKREG();
000018  2100              MOVS     r1,#0
00001a  6001              STR      r1,[r0,#0]
;;;151    }
00001c  4770              BX       lr
;;;152    
                          ENDP

00001e  0000              DCW      0x0000
                  |L26.32|
                          DCD      0x50000100
                  |L26.36|
                          DCD      0x50000200

                          AREA ||i.DrvPDMA_InstallCallBack||, CODE, READONLY, ALIGN=2

                  DrvPDMA_InstallCallBack PROC
;;;571    /*---------------------------------------------------------------------------------------------------------*/
;;;572    int32_t DrvPDMA_InstallCallBack(
000000  b510              PUSH     {r4,lr}
;;;573    	E_DRVPDMA_CHANNEL_INDEX eChannel,
;;;574        E_DRVPDMA_INT_ENABLE eIntSource,
;;;575    	PFN_DRVPDMA_CALLBACK pfncallback
;;;576    )
;;;577    {
;;;578    	assert_param(CHECK_DMA_INT(eChannel, eIntSource));
;;;579    	assert_param(CHECK_DMA_INTCALLBACK(pfncallback));
;;;580    
;;;581    	if (eIntSource & 0xf)
;;;582    		g_pfnPDMACallback[eChannel][eIntSource >> 1] = pfncallback;	       /* Install Callback funtion */
000002  4c08              LDR      r4,|L27.36|
000004  0140              LSLS     r0,r0,#5
000006  070b              LSLS     r3,r1,#28             ;581
000008  1900              ADDS     r0,r0,r4
00000a  2b00              CMP      r3,#0                 ;581
00000c  d003              BEQ      |L27.22|
00000e  0849              LSRS     r1,r1,#1
000010  0089              LSLS     r1,r1,#2
000012  5042              STR      r2,[r0,r1]
000014  e003              B        |L27.30|
                  |L27.22|
;;;583    	else
;;;584    		g_pfnPDMACallback[eChannel][(eIntSource>>5)+5] = pfncallback;	   /* Install Callback funtion */
000016  0949              LSRS     r1,r1,#5
000018  0089              LSLS     r1,r1,#2
00001a  1840              ADDS     r0,r0,r1
00001c  6142              STR      r2,[r0,#0x14]
                  |L27.30|
;;;585    
;;;586        return E_SUCCESS;
00001e  2000              MOVS     r0,#0
;;;587    }
000020  bd10              POP      {r4,pc}
;;;588    
                          ENDP

000022  0000              DCW      0x0000
                  |L27.36|
                          DCD      ||.bss||

                          AREA ||i.DrvPDMA_IsCHBusy||, CODE, READONLY, ALIGN=2

                  DrvPDMA_IsCHBusy PROC
;;;295    /*---------------------------------------------------------------------------------------------------------*/
;;;296    int32_t DrvPDMA_IsCHBusy(E_DRVPDMA_CHANNEL_INDEX eChannel)
000000  4903              LDR      r1,|L28.16|
;;;297    {
;;;298    	PDMA_TypeDef *base;
;;;299    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;300    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1840              ADDS     r0,r0,r1
;;;301    
;;;302    	return (base->CSR_BITS.TRIG_EN)? TRUE: FALSE;
000006  6800              LDR      r0,[r0,#0]
000008  0200              LSLS     r0,r0,#8
00000a  0fc0              LSRS     r0,r0,#31
;;;303    }
00000c  4770              BX       lr
;;;304    
                          ENDP

00000e  0000              DCW      0x0000
                  |L28.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_IsCRCBusy||, CODE, READONLY, ALIGN=2

                  DrvPDMA_IsCRCBusy PROC
;;;860    /*---------------------------------------------------------------------------------------------------------*/
;;;861    int32_t DrvPDMA_IsCRCBusy(void)
000000  4802              LDR      r0,|L29.12|
;;;862    {
;;;863    	return (PDMACRC->CTL_BITS.TRIG_EN)? TRUE: FALSE;
000002  6800              LDR      r0,[r0,#0]
000004  0200              LSLS     r0,r0,#8
000006  0fc0              LSRS     r0,r0,#31
;;;864    }
000008  4770              BX       lr
;;;865    
                          ENDP

00000a  0000              DCW      0x0000
                  |L29.12|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_IsIntEnabled||, CODE, READONLY, ALIGN=2

                  DrvPDMA_IsIntEnabled PROC
;;;485    /*---------------------------------------------------------------------------------------------------------*/
;;;486    int32_t	DrvPDMA_IsIntEnabled(E_DRVPDMA_CHANNEL_INDEX eChannel,E_DRVPDMA_INT_ENABLE eIntSource)
000000  4a03              LDR      r2,|L30.16|
;;;487    {
;;;488     	PDMA_TypeDef *base;
;;;489    	assert_param(CHECK_DMA_INT(eChannel, eIntSource));
;;;490    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;491    
;;;492    	return (base->IER & eIntSource)? TRUE: FALSE;
000006  6a00              LDR      r0,[r0,#0x20]
000008  4008              ANDS     r0,r0,r1
00000a  d000              BEQ      |L30.14|
00000c  2001              MOVS     r0,#1
                  |L30.14|
;;;493    }
00000e  4770              BX       lr
;;;494    
                          ENDP

                  |L30.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_Open||, CODE, READONLY, ALIGN=2

                  DrvPDMA_Open PROC
;;;193    /*---------------------------------------------------------------------------------------------------------*/
;;;194    int32_t DrvPDMA_Open(E_DRVPDMA_CHANNEL_INDEX eChannel,STR_PDMA_T *sParam)
000000  b570              PUSH     {r4-r6,lr}
;;;195    {
;;;196        /*-----------------------------------------------------------------------------------------------------*/
;;;197        /* Check PDMA channel                                                                                  */
;;;198        /*-----------------------------------------------------------------------------------------------------*/
;;;199    	PDMA_TypeDef *base;
;;;200    	assert_param(CHECK_PDMA_CHANNEL(eChannel));
;;;201    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
;;;202    
;;;203    	/*-----------------------------------------------------------------------------------------------------*/
;;;204        /* Set PDMA settings                                                                                   */
;;;205        /*-----------------------------------------------------------------------------------------------------*/
;;;206    	PDMAGCR->CSR |= (1<<(eChannel+8));			/* Enable Channel Clock */
000002  4d15              LDR      r5,|L31.88|
000004  4b13              LDR      r3,|L31.84|
000006  0202              LSLS     r2,r0,#8              ;201
000008  682c              LDR      r4,[r5,#0]
00000a  18d2              ADDS     r2,r2,r3              ;201
00000c  2301              MOVS     r3,#1
00000e  3008              ADDS     r0,r0,#8
000010  461e              MOV      r6,r3
000012  4086              LSLS     r6,r6,r0
000014  4334              ORRS     r4,r4,r6
000016  602c              STR      r4,[r5,#0]
;;;207    
;;;208    	base->SAR = sParam->sSrcCtrl.u32Addr;		/* Set Source Address */
000018  6808              LDR      r0,[r1,#0]
00001a  6050              STR      r0,[r2,#4]
;;;209    	base->DAR = sParam->sDestCtrl.u32Addr;		/* Set Destination Address */
00001c  6888              LDR      r0,[r1,#8]
00001e  6090              STR      r0,[r2,#8]
;;;210    	base->BCR = sParam->i32ByteCnt;				/* Set Byte Count Register */
000020  6988              LDR      r0,[r1,#0x18]
000022  60d0              STR      r0,[r2,#0xc]
;;;211    
;;;212    	if (sParam->bIsTimeOutEnable)
000024  7f08              LDRB     r0,[r1,#0x1c]
000026  2800              CMP      r0,#0
;;;213    		base->CSR = (uint32_t)sParam->sSrcCtrl.eAddrDirection |sParam->sDestCtrl.eAddrDirection|sParam->u8TransWidth|
;;;214    					sParam->u8Mode|0x1001;
;;;215    	else
;;;216    		base->CSR = (uint32_t)sParam->sSrcCtrl.eAddrDirection |sParam->sDestCtrl.eAddrDirection|sParam->u8TransWidth|
000028  7908              LDRB     r0,[r1,#4]
00002a  d008              BEQ      |L31.62|
00002c  7b0b              LDRB     r3,[r1,#0xc]          ;213
00002e  4318              ORRS     r0,r0,r3              ;213
000030  690b              LDR      r3,[r1,#0x10]         ;213
000032  7d09              LDRB     r1,[r1,#0x14]         ;213
000034  430b              ORRS     r3,r3,r1              ;213
000036  4909              LDR      r1,|L31.92|
000038  4318              ORRS     r0,r0,r3              ;213
00003a  4308              ORRS     r0,r0,r1              ;213
00003c  e006              B        |L31.76|
                  |L31.62|
00003e  7b0c              LDRB     r4,[r1,#0xc]
000040  4320              ORRS     r0,r0,r4
000042  690c              LDR      r4,[r1,#0x10]
000044  7d09              LDRB     r1,[r1,#0x14]
000046  430c              ORRS     r4,r4,r1
000048  4320              ORRS     r0,r0,r4
00004a  4318              ORRS     r0,r0,r3
                  |L31.76|
00004c  6010              STR      r0,[r2,#0]
;;;217    					sParam->u8Mode|0x1;
;;;218    
;;;219    	return E_SUCCESS;
00004e  2000              MOVS     r0,#0
;;;220    }
000050  bd70              POP      {r4-r6,pc}
;;;221    
                          ENDP

000052  0000              DCW      0x0000
                  |L31.84|
                          DCD      0x50008000
                  |L31.88|
                          DCD      0x50008f00
                  |L31.92|
                          DCD      0x00001001

                          AREA ||i.DrvPDMA_OpenCRC||, CODE, READONLY, ALIGN=2

                  DrvPDMA_OpenCRC PROC
;;;803    /*---------------------------------------------------------------------------------------------------------*/
;;;804    int32_t DrvPDMA_OpenCRC(STR_CRC_T *sParam)
000000  b510              PUSH     {r4,lr}
;;;805    {
;;;806    	uint32_t reg = 0;
;;;807    
;;;808    	/*-----------------------------------------------------------------------------------------------------*/
;;;809        /* Set CRC settings                                                                                   */
;;;810        /*-----------------------------------------------------------------------------------------------------*/
;;;811    	PDMAGCR->CSR |= (1<<24);					/* Enable CRC Clock */
000002  4a15              LDR      r2,|L32.88|
000004  6813              LDR      r3,[r2,#0]
000006  2101              MOVS     r1,#1
000008  0609              LSLS     r1,r1,#24
00000a  430b              ORRS     r3,r3,r1
00000c  6013              STR      r3,[r2,#0]
;;;812    
;;;813    	PDMACRC->DMASAR    = sParam->u32DMASrcAddr;		/* Set Source Address */
00000e  4c13              LDR      r4,|L32.92|
000010  6882              LDR      r2,[r0,#8]
000012  6062              STR      r2,[r4,#4]
;;;814    	PDMACRC->DMABCR    = sParam->u16DMAByteCnt;		/* Set Byte Count Register */
000014  8982              LDRH     r2,[r0,#0xc]
000016  60e2              STR      r2,[r4,#0xc]
;;;815    
;;;816    	reg = (sParam->u32Mode << 30) | (sParam->u32CPUWdlen << 28);
000018  7802              LDRB     r2,[r0,#0]
00001a  7843              LDRB     r3,[r0,#1]
00001c  0792              LSLS     r2,r2,#30
00001e  071b              LSLS     r3,r3,#28
000020  431a              ORRS     r2,r2,r3
;;;817    	reg |= (sParam->bIsChecksumComplement ? 0x8000000 : 0);
000022  7883              LDRB     r3,[r0,#2]
000024  2b00              CMP      r3,#0
000026  d000              BEQ      |L32.42|
000028  00cb              LSLS     r3,r1,#3
                  |L32.42|
00002a  4313              ORRS     r3,r3,r2
;;;818    	reg |= (sParam->bIsWriteDataComplement ? 0x4000000 : 0);
00002c  78c2              LDRB     r2,[r0,#3]
00002e  2a00              CMP      r2,#0
000030  d001              BEQ      |L32.54|
000032  2201              MOVS     r2,#1
000034  0692              LSLS     r2,r2,#26
                  |L32.54|
000036  431a              ORRS     r2,r2,r3
;;;819    	reg |= (sParam->bIsChecksumReverse ? 0x2000000 : 0);
000038  7903              LDRB     r3,[r0,#4]
00003a  2b00              CMP      r3,#0
00003c  d001              BEQ      |L32.66|
00003e  2301              MOVS     r3,#1
000040  065b              LSLS     r3,r3,#25
                  |L32.66|
;;;820    	reg |= (sParam->bIsWriteDataReverse ? 0x1000000 : 0);
000042  7940              LDRB     r0,[r0,#5]
000044  4313              ORRS     r3,r3,r2              ;819
000046  2800              CMP      r0,#0
000048  d100              BNE      |L32.76|
00004a  2100              MOVS     r1,#0
                  |L32.76|
00004c  4319              ORRS     r1,r1,r3
;;;821    
;;;822    	PDMACRC->CTL = reg | 0x1;
00004e  2001              MOVS     r0,#1
000050  4301              ORRS     r1,r1,r0
000052  6021              STR      r1,[r4,#0]
;;;823    
;;;824    	return E_SUCCESS;
000054  2000              MOVS     r0,#0
;;;825    }
000056  bd10              POP      {r4,pc}
;;;826    
                          ENDP

                  |L32.88|
                          DCD      0x50008f00
                  |L32.92|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_OpenVDMA||, CODE, READONLY, ALIGN=2

                  DrvPDMA_OpenVDMA PROC
;;;236    /*---------------------------------------------------------------------------------------------------------*/
;;;237    int32_t DrvPDMA_OpenVDMA(STR_VDMA_T *sParam)
000000  490e              LDR      r1,|L33.60|
;;;238    {
;;;239    	/*-----------------------------------------------------------------------------------------------------*/
;;;240        /* Set VDMA settings                                                                                   */
;;;241        /*-----------------------------------------------------------------------------------------------------*/
;;;242    	PDMAGCR->CSR |= (1<<8);					/* Enable Channel Clock */
000002  680a              LDR      r2,[r1,#0]
000004  23ff              MOVS     r3,#0xff
000006  3301              ADDS     r3,#1
000008  431a              ORRS     r2,r2,r3
00000a  600a              STR      r2,[r1,#0]
;;;243    
;;;244    	VDMA->SAR    = sParam->u32SrcAddr;		/* Set Source Address */
00000c  490c              LDR      r1,|L33.64|
00000e  6842              LDR      r2,[r0,#4]
000010  604a              STR      r2,[r1,#4]
;;;245    	VDMA->DAR    = sParam->u32DestAddr;		/* Set Destination Address */
000012  6882              LDR      r2,[r0,#8]
000014  608a              STR      r2,[r1,#8]
;;;246    	VDMA->BCR    = sParam->i32ByteCnt;		/* Set Byte Count Register */
000016  68c2              LDR      r2,[r0,#0xc]
000018  60ca              STR      r2,[r1,#0xc]
;;;247    	VDMA->DASOCR = sParam->u16Dastobl;
00001a  8a82              LDRH     r2,[r0,#0x14]
00001c  630a              STR      r2,[r1,#0x30]
;;;248    	VDMA->SASOCR = (sParam->u16Stbc << 16) | sParam->u16Sastobl;
00001e  6902              LDR      r2,[r0,#0x10]
000020  2310              MOVS     r3,#0x10
000022  41da              RORS     r2,r2,r3
000024  62ca              STR      r2,[r1,#0x2c]
;;;249    
;;;250    	if (sParam->bIsStrideEnable)
000026  7d82              LDRB     r2,[r0,#0x16]
;;;251    		VDMA->CSR = sParam->u32Dir | 0x401;
;;;252    	else
;;;253    		VDMA->CSR = sParam->u32Dir | 0x1;
000028  8800              LDRH     r0,[r0,#0]
00002a  2a00              CMP      r2,#0                 ;250
00002c  d001              BEQ      |L33.50|
00002e  4a05              LDR      r2,|L33.68|
000030  e000              B        |L33.52|
                  |L33.50|
000032  2201              MOVS     r2,#1
                  |L33.52|
000034  4310              ORRS     r0,r0,r2
000036  6008              STR      r0,[r1,#0]
;;;254    
;;;255    	return E_SUCCESS;
000038  2000              MOVS     r0,#0
;;;256    }
00003a  4770              BX       lr
;;;257    
                          ENDP

                  |L33.60|
                          DCD      0x50008f00
                  |L33.64|
                          DCD      0x50008000
                  |L33.68|
                          DCD      0x00000401

                          AREA ||i.DrvPDMA_PollInt||, CODE, READONLY, ALIGN=2

                  DrvPDMA_PollInt PROC
;;;529    /*---------------------------------------------------------------------------------------------------------*/
;;;530    int32_t	DrvPDMA_PollInt(E_DRVPDMA_CHANNEL_INDEX eChannel,E_DRVPDMA_INT_FLAG eIntFlag)
000000  4a03              LDR      r2,|L34.16|
;;;531    {
;;;532     	PDMA_TypeDef *base;
;;;533    	assert_param(CHECK_DMA_INT(eChannel, eIntFlag));
;;;534    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;535    
;;;536    	return (base->ISR & eIntFlag)? TRUE: FALSE;
000006  6a40              LDR      r0,[r0,#0x24]
000008  4008              ANDS     r0,r0,r1
00000a  d000              BEQ      |L34.14|
00000c  2001              MOVS     r0,#1
                  |L34.14|
;;;537    }
00000e  4770              BX       lr
;;;538    
                          ENDP

                  |L34.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_SetAPBTransferWidth||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetAPBTransferWidth PROC
;;;344    /*---------------------------------------------------------------------------------------------------------*/
;;;345    int32_t	DrvPDMA_SetAPBTransferWidth(E_DRVPDMA_CHANNEL_INDEX eChannel,E_DRVPDMA_TRANSFER_WIDTH eTransferWidth)
000000  4a06              LDR      r2,|L35.28|
;;;346    {
;;;347     	PDMA_TypeDef *base;
;;;348    	assert_param(CHECK_PDMA_CHANNEL(eChannel));
;;;349    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;350    
;;;351    	base->CSR_BITS.APB_TWS = eTransferWidth;	/* Set PDMA Transfer Length */
000006  6802              LDR      r2,[r0,#0]
000008  2303              MOVS     r3,#3
00000a  04db              LSLS     r3,r3,#19
00000c  0789              LSLS     r1,r1,#30
00000e  439a              BICS     r2,r2,r3
000010  0ac9              LSRS     r1,r1,#11
000012  430a              ORRS     r2,r2,r1
000014  6002              STR      r2,[r0,#0]
;;;352    
;;;353        return E_SUCCESS;     													
000016  2000              MOVS     r0,#0
;;;354    }
000018  4770              BX       lr
;;;355    
                          ENDP

00001a  0000              DCW      0x0000
                  |L35.28|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_SetCHForAPBDevice||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetCHForAPBDevice PROC
;;;715    /*---------------------------------------------------------------------------------------------------------*/
;;;716    int32_t	DrvPDMA_SetCHForAPBDevice(
000000  b510              PUSH     {r4,lr}
;;;717        E_DRVPDMA_CHANNEL_INDEX eChannel,
;;;718        E_DRVPDMA_APB_DEVICE 	eDevice,
;;;719        E_DRVPDMA_APB_RW 		eRWAPB
;;;720    )
;;;721    {
;;;722    	assert_param(CHECK_PDMA_CHANNEL(eChannel));
;;;723    
;;;724    	if (eChannel < eDRVPDMA_CHANNEL_4)
;;;725    		PDMAGCR->PDSSR0 = (PDMAGCR->PDSSR0 & ~(eDRVPDMA_NONE << (eChannel*8)))|(eDevice << (eChannel*8));
000002  4c0a              LDR      r4,|L36.44|
000004  231f              MOVS     r3,#0x1f
000006  00c2              LSLS     r2,r0,#3
000008  2804              CMP      r0,#4                 ;724
00000a  d206              BCS      |L36.26|
00000c  6860              LDR      r0,[r4,#4]
00000e  4093              LSLS     r3,r3,r2
000010  4398              BICS     r0,r0,r3
000012  4091              LSLS     r1,r1,r2
000014  4308              ORRS     r0,r0,r1
000016  6060              STR      r0,[r4,#4]
000018  e006              B        |L36.40|
                  |L36.26|
;;;726    	else
;;;727    		PDMAGCR->PDSSR1 = (PDMAGCR->PDSSR1 & ~(eDRVPDMA_NONE << ((eChannel-4)*8)))|(eDevice << ((eChannel-4)*8));
00001a  3a20              SUBS     r2,r2,#0x20
00001c  68a0              LDR      r0,[r4,#8]
00001e  4093              LSLS     r3,r3,r2
000020  4398              BICS     r0,r0,r3
000022  4091              LSLS     r1,r1,r2
000024  4308              ORRS     r0,r0,r1
000026  60a0              STR      r0,[r4,#8]
                  |L36.40|
;;;728    
;;;729        return E_SUCCESS;
000028  2000              MOVS     r0,#0
;;;730    }
00002a  bd10              POP      {r4,pc}
;;;731    
                          ENDP

                  |L36.44|
                          DCD      0x50008f00

                          AREA ||i.DrvPDMA_SetCRCCPUWriteDataLength||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetCRCCPUWriteDataLength PROC
;;;900    /*---------------------------------------------------------------------------------------------------------*/
;;;901    int32_t DrvPDMA_SetCRCCPUWriteDataLength(E_DRVPDMA_CRC_CPU_WDLEN eWdlen)
000000  4a05              LDR      r2,|L37.24|
;;;902    {
;;;903    	PDMACRC->CTL_BITS.CPU_WDLEN = eWdlen;
000002  6811              LDR      r1,[r2,#0]
000004  2303              MOVS     r3,#3
000006  071b              LSLS     r3,r3,#28
000008  0780              LSLS     r0,r0,#30
00000a  4399              BICS     r1,r1,r3
00000c  0880              LSRS     r0,r0,#2
00000e  4301              ORRS     r1,r1,r0
000010  6011              STR      r1,[r2,#0]
;;;904    
;;;905        return E_SUCCESS;     													
000012  2000              MOVS     r0,#0
;;;906    }
000014  4770              BX       lr
;;;907    
                          ENDP

000016  0000              DCW      0x0000
                  |L37.24|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_SetCRCPolynomialMode||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetCRCPolynomialMode PROC
;;;879    /*---------------------------------------------------------------------------------------------------------*/
;;;880    int32_t	DrvPDMA_SetCRCPolynomialMode(E_DRVPDMA_CRC_MODE eMode)
000000  4904              LDR      r1,|L38.20|
;;;881    {
;;;882    	PDMACRC->CTL_BITS.MODE = eMode;
000002  680a              LDR      r2,[r1,#0]
000004  0092              LSLS     r2,r2,#2
000006  0892              LSRS     r2,r2,#2
000008  0780              LSLS     r0,r0,#30
00000a  4302              ORRS     r2,r2,r0
00000c  600a              STR      r2,[r1,#0]
;;;883    
;;;884        return E_SUCCESS;     													
00000e  2000              MOVS     r0,#0
;;;885    }
000010  4770              BX       lr
;;;886    
                          ENDP

000012  0000              DCW      0x0000
                  |L38.20|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_SetCRCTransfer||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetCRCTransfer PROC
;;;839    /*---------------------------------------------------------------------------------------------------------*/
;;;840    int32_t DrvPDMA_SetCRCTransfer(uint32_t u32SrcAddr, uint16_t u16ByteCount, uint32_t u32SeedValue)
000000  4b03              LDR      r3,|L39.16|
;;;841    {
;;;842    	PDMACRC->DMASAR = u32SrcAddr;		/* Set Source Address */
000002  6058              STR      r0,[r3,#4]
;;;843    	PDMACRC->DMABCR = u16ByteCount;		/* Set Byte Count Register */
000004  60d9              STR      r1,[r3,#0xc]
;;;844    	PDMACRC->SEED   = u32SeedValue;		/* Set Seed Register */
000006  4802              LDR      r0,|L39.16|
000008  3080              ADDS     r0,r0,#0x80
00000a  6042              STR      r2,[r0,#4]
;;;845    
;;;846    	return E_SUCCESS;
00000c  2000              MOVS     r0,#0
;;;847    }
00000e  4770              BX       lr
;;;848    
                          ENDP

                  |L39.16|
                          DCD      0x50008e00

                          AREA ||i.DrvPDMA_SetTimeOutCount||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetTimeOutCount PROC
;;;630    /*---------------------------------------------------------------------------------------------------------*/
;;;631    int32_t DrvPDMA_SetTimeOutCount(E_DRVPDMA_CHANNEL_INDEX eChannel, uint32_t Count)
000000  4a02              LDR      r2,|L40.12|
;;;632    {
;;;633     	PDMA_TypeDef *base;
;;;634    	assert_param(CHECK_PDMA_CHANNEL(eChannel));
;;;635    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  0200              LSLS     r0,r0,#8
000004  1880              ADDS     r0,r0,r2
;;;636    
;;;637    	base->TCR = Count;
000006  6281              STR      r1,[r0,#0x28]
;;;638    
;;;639    	return E_SUCCESS;
000008  2000              MOVS     r0,#0
;;;640    }
00000a  4770              BX       lr
;;;641    
                          ENDP

                  |L40.12|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_SetTransferSetting||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetTransferSetting PROC
;;;269    /*---------------------------------------------------------------------------------------------------------*/
;;;270    int32_t DrvPDMA_SetTransferSetting(E_DRVPDMA_CHANNEL_INDEX eChannel, uint32_t u32SrcAddr, uint32_t u32DestAddr, uint32_t u32TransferLength)
000000  b510              PUSH     {r4,lr}
;;;271    {
;;;272    	PDMA_TypeDef *base;
;;;273    	assert_param(CHECK_DMA_CHANNEL(eChannel));
;;;274    	base = (PDMA_TypeDef *)get_channel_base(eChannel);
000002  4c04              LDR      r4,|L41.20|
000004  0200              LSLS     r0,r0,#8
000006  1900              ADDS     r0,r0,r4
;;;275    
;;;276    	base->SAR = u32SrcAddr;				/* Set Source Address */
000008  6041              STR      r1,[r0,#4]
;;;277    	base->DAR = u32DestAddr;			/* Set Destination Address */
00000a  6082              STR      r2,[r0,#8]
;;;278    	base->BCR = u32TransferLength;		/* Set Byte Count Register */
00000c  60c3              STR      r3,[r0,#0xc]
;;;279    
;;;280    	return E_SUCCESS;
00000e  2000              MOVS     r0,#0
;;;281    }
000010  bd10              POP      {r4,pc}
;;;282    
                          ENDP

000012  0000              DCW      0x0000
                  |L41.20|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_SetVDMATransferSetting||, CODE, READONLY, ALIGN=2

                  DrvPDMA_SetVDMATransferSetting PROC
;;;782    /*---------------------------------------------------------------------------------------------------------*/
;;;783    int32_t DrvPDMA_SetVDMATransferSetting(uint32_t u32Stbc, uint32_t u32Sastobl, uint32_t u32Dastobl)
000000  0403              LSLS     r3,r0,#16
;;;784    {
;;;785    	VDMA->SASOCR = (u32Stbc << 16) | u32Sastobl;
000002  4803              LDR      r0,|L42.16|
000004  430b              ORRS     r3,r3,r1
000006  62c3              STR      r3,[r0,#0x2c]
;;;786    	VDMA->DASOCR = u32Dastobl;					/* Set Destination Address Stride Offset Byte Length */
000008  6302              STR      r2,[r0,#0x30]
;;;787    	return E_SUCCESS;
00000a  2000              MOVS     r0,#0
;;;788    }
00000c  4770              BX       lr
;;;789    
                          ENDP

00000e  0000              DCW      0x0000
                  |L42.16|
                          DCD      0x50008000

                          AREA ||i.DrvPDMA_UnInstallCallBack||, CODE, READONLY, ALIGN=2

                  DrvPDMA_UnInstallCallBack PROC
;;;602    /*---------------------------------------------------------------------------------------------------------*/
;;;603    int32_t DrvPDMA_UnInstallCallBack(
000000  b510              PUSH     {r4,lr}
;;;604    	E_DRVPDMA_CHANNEL_INDEX eChannel,
;;;605        E_DRVPDMA_INT_ENABLE eIntSource
;;;606    )
;;;607    {
;;;608    	assert_param(CHECK_DMA_INT(eChannel, eIntSource));
;;;609    
;;;610    	if (eIntSource & 0xf)
;;;611    		g_pfnPDMACallback[eChannel][eIntSource >> 1] = 0;	   /* Install Callback funtion */
000002  4c08              LDR      r4,|L43.36|
000004  0140              LSLS     r0,r0,#5
000006  070a              LSLS     r2,r1,#28             ;610
000008  2300              MOVS     r3,#0
00000a  1900              ADDS     r0,r0,r4
00000c  2a00              CMP      r2,#0                 ;610
00000e  d003              BEQ      |L43.24|
000010  0849              LSRS     r1,r1,#1
000012  0089              LSLS     r1,r1,#2
000014  5043              STR      r3,[r0,r1]
000016  e003              B        |L43.32|
                  |L43.24|
;;;612    	else
;;;613    		g_pfnPDMACallback[eChannel][(eIntSource>>5)+5] = 0;	   /* Install Callback funtion */
000018  0949              LSRS     r1,r1,#5
00001a  0089              LSLS     r1,r1,#2
00001c  1840              ADDS     r0,r0,r1
00001e  6143              STR      r3,[r0,#0x14]
                  |L43.32|
;;;614    
;;;615        return E_SUCCESS;
000020  2000              MOVS     r0,#0
;;;616    }
000022  bd10              POP      {r4,pc}
;;;617    
                          ENDP

                  |L43.36|
                          DCD      ||.bss||

                          AREA ||i.PDMA_IRQHandler||, CODE, READONLY, ALIGN=2

                  PDMA_IRQHandler PROC
;;;50     /*---------------------------------------------------------------------------------------------------------*/
;;;51     void PDMA_IRQHandler(void)
000000  b4f0              PUSH     {r4-r7}
;;;52     {
;;;53         volatile int32_t  i32Channel= 0;
;;;54     	volatile uint32_t u32ISR;
;;;55     	PDMA_TypeDef *base;
;;;56     
;;;57     	u32ISR = PDMAGCR->ISR;
000002  4930              LDR      r1,|L44.196|
000004  2000              MOVS     r0,#0                 ;53
000006  68c9              LDR      r1,[r1,#0xc]
;;;58     
;;;59     	if(u32ISR & 1)  										 		/* Check INT Channel */	
000008  07ca              LSLS     r2,r1,#31
00000a  d11a              BNE      |L44.66|
;;;60     		i32Channel = 0;
;;;61     	else if (u32ISR & 0x2)
00000c  0788              LSLS     r0,r1,#30
00000e  d501              BPL      |L44.20|
;;;62     		i32Channel = 1;
000010  2001              MOVS     r0,#1
000012  e016              B        |L44.66|
                  |L44.20|
;;;63     	else if (u32ISR & 0x4)
000014  0748              LSLS     r0,r1,#29
000016  d501              BPL      |L44.28|
;;;64     		i32Channel = 2;
000018  2002              MOVS     r0,#2
00001a  e012              B        |L44.66|
                  |L44.28|
;;;65     	else if (u32ISR & 0x8)
00001c  0708              LSLS     r0,r1,#28
00001e  d501              BPL      |L44.36|
;;;66     		i32Channel = 3;
000020  2003              MOVS     r0,#3
000022  e00e              B        |L44.66|
                  |L44.36|
;;;67     	else if (u32ISR & 0x10)
000024  06c8              LSLS     r0,r1,#27
000026  d501              BPL      |L44.44|
;;;68     		i32Channel = 4;
000028  2004              MOVS     r0,#4
00002a  e00a              B        |L44.66|
                  |L44.44|
;;;69     	else if (u32ISR & 0x20)
00002c  0688              LSLS     r0,r1,#26
00002e  d501              BPL      |L44.52|
;;;70     		i32Channel = 5;
000030  2005              MOVS     r0,#5
000032  e006              B        |L44.66|
                  |L44.52|
;;;71     	else if (u32ISR & 0x40)
000034  0648              LSLS     r0,r1,#25
000036  d501              BPL      |L44.60|
;;;72     		i32Channel = 6;
000038  2006              MOVS     r0,#6
00003a  e002              B        |L44.66|
                  |L44.60|
;;;73     	else if (u32ISR & 0x10000)
00003c  03c8              LSLS     r0,r1,#15
00003e  d53f              BPL      |L44.192|
;;;74     		i32Channel = 0xE;
000040  200e              MOVS     r0,#0xe
                  |L44.66|
;;;75     	else
;;;76     		return;
;;;77     
;;;78     	base = (PDMA_TypeDef *)get_channel_base(i32Channel);
000042  4a21              LDR      r2,|L44.200|
000044  0201              LSLS     r1,r0,#8
000046  1889              ADDS     r1,r1,r2
000048  2401              MOVS     r4,#1                 ;62
00004a  2502              MOVS     r5,#2                 ;64
;;;79     	if (i32Channel < 7)
00004c  2807              CMP      r0,#7
00004e  da2a              BGE      |L44.166|
;;;80     	{
;;;81     		u32ISR = base->ISR;
000050  6a4a              LDR      r2,[r1,#0x24]
;;;82     
;;;83     		if(u32ISR & 0x01)	 										/* Check Target Abort INT and clear */
;;;84     		{
;;;85     			base->ISR = 0x01;
;;;86     			if (g_pfnPDMACallback[i32Channel][0] != 0)
000052  4b1e              LDR      r3,|L44.204|
000054  07d6              LSLS     r6,r2,#31             ;83
000056  d003              BEQ      |L44.96|
000058  624c              STR      r4,[r1,#0x24]         ;85
00005a  0140              LSLS     r0,r0,#5
00005c  5819              LDR      r1,[r3,r0]
00005e  e005              B        |L44.108|
                  |L44.96|
;;;87     	    		(*g_pfnPDMACallback[i32Channel][0])(0);							/* Target Abort callback funtion */
;;;88     		}
;;;89     		else if(u32ISR & 0x02)
000060  0794              LSLS     r4,r2,#30
000062  d508              BPL      |L44.118|
;;;90     		{																		/* Transfer Done INT and clear */
;;;91     			base->ISR = 0x2;
000064  624d              STR      r5,[r1,#0x24]
;;;92     			if (g_pfnPDMACallback[i32Channel][1] != 0)
000066  0140              LSLS     r0,r0,#5
000068  18c0              ADDS     r0,r0,r3
00006a  6841              LDR      r1,[r0,#4]
                  |L44.108|
00006c  2900              CMP      r1,#0                 ;86
00006e  d027              BEQ      |L44.192|
;;;93     	    		(*g_pfnPDMACallback[i32Channel][1])(0);
;;;94     		}
;;;95     		else if(u32ISR & 0x04)
;;;96     		{																		/* Wrap around Transfer complete and clear */
;;;97     			base->ISR = 0x04;
;;;98     			if (g_pfnPDMACallback[i32Channel][2] != 0)
;;;99     	    		(*g_pfnPDMACallback[i32Channel][2])(0);
;;;100    		}
;;;101    		else if(u32ISR & 0x10)
;;;102    		{																		/* Wrap around Transfer Half and clear */
;;;103    			base->ISR = 0x10;
;;;104    			if (g_pfnPDMACallback[i32Channel][5] != 0)
;;;105    	    		(*g_pfnPDMACallback[i32Channel][5])(0);
;;;106    		}
;;;107    		else if(u32ISR & 0x40)
;;;108    		{																		/* Transfer Timeout INT and clear */
;;;109    			base->ISR = 0x40;
;;;110    			if (g_pfnPDMACallback[i32Channel][7] != 0)
;;;111    	    		(*g_pfnPDMACallback[i32Channel][7])(0);
;;;112    		}
;;;113    	}
;;;114    	else
;;;115    	{
;;;116    		u32ISR = PDMACRC->DMAISR;
;;;117    
;;;118    		if(u32ISR & 0x01)	 										/* Check Target Abort INT and clear */
;;;119    		{
;;;120    			PDMACRC->DMAISR = 0x01;
;;;121    			if (g_pfnPDMACRCCallback[0] != 0)
;;;122    	    		(*g_pfnPDMACRCCallback[0])(0);						/* Target Abort callback funtion */
;;;123    		}
;;;124    		else if(u32ISR & 0x02)
;;;125    		{															/* Transfer Done INT and clear */
;;;126    			PDMACRC->DMAISR = 0x2;
;;;127    			if (g_pfnPDMACRCCallback[1] != 0)
;;;128    	    		(*g_pfnPDMACRCCallback[1])(0);
000070  bcf0              POP      {r4-r7}
000072  2000              MOVS     r0,#0
000074  4708              BX       r1
                  |L44.118|
000076  0754              LSLS     r4,r2,#29             ;95
000078  d505              BPL      |L44.134|
00007a  2204              MOVS     r2,#4                 ;97
00007c  624a              STR      r2,[r1,#0x24]         ;97
00007e  0140              LSLS     r0,r0,#5              ;98
000080  18c0              ADDS     r0,r0,r3              ;98
000082  6881              LDR      r1,[r0,#8]            ;98
000084  e7f2              B        |L44.108|
                  |L44.134|
000086  06d4              LSLS     r4,r2,#27             ;101
000088  d505              BPL      |L44.150|
00008a  2210              MOVS     r2,#0x10              ;103
00008c  624a              STR      r2,[r1,#0x24]         ;103
00008e  0140              LSLS     r0,r0,#5              ;104
000090  18c0              ADDS     r0,r0,r3              ;104
000092  6941              LDR      r1,[r0,#0x14]         ;104
000094  e7ea              B        |L44.108|
                  |L44.150|
000096  0652              LSLS     r2,r2,#25             ;107
000098  d512              BPL      |L44.192|
00009a  2240              MOVS     r2,#0x40              ;109
00009c  624a              STR      r2,[r1,#0x24]         ;109
00009e  0140              LSLS     r0,r0,#5              ;110
0000a0  18c0              ADDS     r0,r0,r3              ;110
0000a2  69c1              LDR      r1,[r0,#0x1c]         ;110
0000a4  e7e2              B        |L44.108|
                  |L44.166|
0000a6  490a              LDR      r1,|L44.208|
0000a8  6a48              LDR      r0,[r1,#0x24]         ;116
0000aa  4a0a              LDR      r2,|L44.212|
0000ac  07c3              LSLS     r3,r0,#31             ;118
0000ae  d002              BEQ      |L44.182|
0000b0  624c              STR      r4,[r1,#0x24]         ;120
0000b2  6811              LDR      r1,[r2,#0]            ;121  ; g_pfnPDMACRCCallback
0000b4  e7da              B        |L44.108|
                  |L44.182|
0000b6  0780              LSLS     r0,r0,#30             ;124
0000b8  d502              BPL      |L44.192|
0000ba  624d              STR      r5,[r1,#0x24]         ;126
0000bc  6851              LDR      r1,[r2,#4]            ;127  ; g_pfnPDMACRCCallback
0000be  e7d5              B        |L44.108|
                  |L44.192|
;;;129    		}
;;;130    	}
;;;131    }
0000c0  bcf0              POP      {r4-r7}
0000c2  4770              BX       lr
;;;132    
                          ENDP

                  |L44.196|
                          DCD      0x50008f00
                  |L44.200|
                          DCD      0x50008000
                  |L44.204|
                          DCD      ||.bss||
                  |L44.208|
                          DCD      0x50008e00
                  |L44.212|
                          DCD      ||.data||

                          AREA ||.bss||, DATA, NOINIT, ALIGN=2

                  g_pfnPDMACallback
                          %        224

                          AREA ||.data||, DATA, ALIGN=2

                  g_pfnPDMACRCCallback
                          DCD      0x00000000
                          DCD      0x00000000
