; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\drvrtc.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvrtc.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvrtc.crf ..\bsp\Driver\DrvRTC.c]
                          THUMB

                          AREA ||i.DrvRTC_Close||, CODE, READONLY, ALIGN=2

                  DrvRTC_Close PROC
;;;871      */
;;;872    int32_t DrvRTC_Close (void)
000000  b500              PUSH     {lr}
;;;873    {
;;;874    
;;;875        g_bIsEnableTickInt = false;
000002  4807              LDR      r0,|L1.32|
000004  2100              MOVS     r1,#0
000006  6141              STR      r1,[r0,#0x14]  ; g_bIsEnableTickInt
;;;876        g_bIsEnableAlarmInt = false;
000008  7041              STRB     r1,[r0,#1]
;;;877        g_bIsEnableSnooperInt = false;
00000a  7081              STRB     r1,[r0,#2]
00000c  2001              MOVS     r0,#1
00000e  4905              LDR      r1,|L1.36|
000010  07c0              LSLS     r0,r0,#31
000012  6008              STR      r0,[r1,#0]
;;;878        
;;;879      	NVIC_DisableIRQ(RTC_IRQn);
;;;880      
;;;881      	DrvRTC_DisableInt(DRVRTC_ALL_INT);
000014  2007              MOVS     r0,#7
000016  f7fffffe          BL       DrvRTC_DisableInt
;;;882    	
;;;883        return E_SUCCESS;
00001a  2000              MOVS     r0,#0
;;;884    }
00001c  bd00              POP      {pc}
;;;885    
                          ENDP

00001e  0000              DCW      0x0000
                  |L1.32|
                          DCD      ||.data||
                  |L1.36|
                          DCD      0xe000e180

                          AREA ||i.DrvRTC_DisableInt||, CODE, READONLY, ALIGN=2

                  DrvRTC_DisableInt PROC
;;;836      */
;;;837    int32_t DrvRTC_DisableInt(E_DRVRTC_INT_SOURCE i32IntSrc)
000000  b510              PUSH     {r4,lr}
;;;838    {
;;;839    	
;;;840    	if((i32IntSrc & DRVRTC_TICK_INT) == DRVRTC_TICK_INT	)
000002  0784              LSLS     r4,r0,#30
;;;841    	{
;;;842    		g_bIsEnableTickInt  = false;	
000004  2200              MOVS     r2,#0
000006  4b11              LDR      r3,|L2.76|
;;;843    		RTC->RIER_BITS.TIER 		= 0; 
000008  4911              LDR      r1,|L2.80|
00000a  2c00              CMP      r4,#0                 ;840
00000c  da03              BGE      |L2.22|
00000e  615a              STR      r2,[r3,#0x14]         ;842  ; g_bIsEnableTickInt
000010  6a8a              LDR      r2,[r1,#0x28]
000012  2002              MOVS     r0,#2
;;;844    		RTC->RIIR_BITS.TIS 		= 1; 
000014  e010              B        |L2.56|
                  |L2.22|
;;;845    	}
;;;846    	else if((i32IntSrc & DRVRTC_ALARM_INT) == DRVRTC_ALARM_INT )
000016  07c4              LSLS     r4,r0,#31
000018  d009              BEQ      |L2.46|
;;;847    	{
;;;848            g_bIsEnableAlarmInt = false;
00001a  705a              STRB     r2,[r3,#1]
;;;849        	RTC->RIER_BITS.AIER 		= 0; 
00001c  6a88              LDR      r0,[r1,#0x28]
00001e  0840              LSRS     r0,r0,#1
000020  0040              LSLS     r0,r0,#1
000022  6288              STR      r0,[r1,#0x28]
;;;850    		RTC->RIIR_BITS.AIS 		= 1; 
000024  6ac8              LDR      r0,[r1,#0x2c]
000026  2201              MOVS     r2,#1
000028  4310              ORRS     r0,r0,r2
00002a  62c8              STR      r0,[r1,#0x2c]
00002c  e009              B        |L2.66|
                  |L2.46|
;;;851    	}
;;;852    	else if((i32IntSrc & DRVRTC_SNOOPER_INT) == DRVRTC_SNOOPER_INT )
00002e  0740              LSLS     r0,r0,#29
000030  d509              BPL      |L2.70|
;;;853    	{
;;;854            g_bIsEnableSnooperInt = false;
000032  709a              STRB     r2,[r3,#2]
;;;855        	RTC->RIER_BITS.SNOOPIER 		= 0; 
000034  6a8a              LDR      r2,[r1,#0x28]
000036  2004              MOVS     r0,#4
                  |L2.56|
000038  4382              BICS     r2,r2,r0
00003a  628a              STR      r2,[r1,#0x28]
;;;856    		RTC->RIIR_BITS.SNOOPIS 		= 1; 
00003c  6aca              LDR      r2,[r1,#0x2c]
00003e  4302              ORRS     r2,r2,r0
000040  62ca              STR      r2,[r1,#0x2c]
                  |L2.66|
;;;857    	}
;;;858    	else
;;;859    	{
;;;860    		return E_DRVRTC_ERR_ENOTTY;
;;;861    	}
;;;862    	return E_SUCCESS;	
000042  2000              MOVS     r0,#0
;;;863    
;;;864    }
000044  bd10              POP      {r4,pc}
                  |L2.70|
000046  4803              LDR      r0,|L2.84|
000048  bd10              POP      {r4,pc}
;;;865    
                          ENDP

00004a  0000              DCW      0x0000
                  |L2.76|
                          DCD      ||.data||
                  |L2.80|
                          DCD      0x40008000
                  |L2.84|
                          DCD      0xffff9206

                          AREA ||i.DrvRTC_DisableSpareFunc||, CODE, READONLY, ALIGN=2

                  DrvRTC_DisableSpareFunc PROC
;;;705      */
;;;706    void DrvRTC_DisableSpareFunc(void)
000000  b500              PUSH     {lr}
;;;707    {
;;;708    	DrvRTC_WriteEnable();
000002  f7fffffe          BL       DrvRTC_WriteEnable
;;;709    
;;;710    	/* Disable snooper pin event detection */
;;;711    	RTC->SPRCTL_BITS.SNOOPEN = 0;
000006  4804              LDR      r0,|L3.24|
000008  6bc1              LDR      r1,[r0,#0x3c]
00000a  0849              LSRS     r1,r1,#1
00000c  0049              LSLS     r1,r1,#1
00000e  63c1              STR      r1,[r0,#0x3c]
                  |L3.16|
;;;712    	while(RTC->SPRCTL_BITS.SPRRDY!=1) ;
000010  6bc1              LDR      r1,[r0,#0x3c]
000012  0609              LSLS     r1,r1,#24
000014  d5fc              BPL      |L3.16|
;;;713    }
000016  bd00              POP      {pc}
;;;714    
                          ENDP

                  |L3.24|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_EnableInt||, CODE, READONLY, ALIGN=2

                  DrvRTC_EnableInt PROC
;;;791      */
;;;792    int32_t DrvRTC_EnableInt(E_DRVRTC_INT_SOURCE str_IntSrc, PFN_DRVRTC_CALLBACK pfncallback)
000000  b510              PUSH     {r4,lr}
;;;793    {
;;;794    	switch (str_IntSrc)
;;;795        {
;;;796    
;;;797        	case DRVRTC_TICK_INT:
;;;798            {
;;;799            	g_bIsEnableTickInt   	= true;
000002  4a12              LDR      r2,|L4.76|
;;;800       			RTC->RIER_BITS.TIER 			= 1; 
000004  4b12              LDR      r3,|L4.80|
000006  2401              MOVS     r4,#1                 ;793
000008  2801              CMP      r0,#1                 ;794
00000a  d00c              BEQ      |L4.38|
00000c  2802              CMP      r0,#2                 ;794
00000e  d003              BEQ      |L4.24|
000010  2804              CMP      r0,#4                 ;794
000012  d00e              BEQ      |L4.50|
;;;801    			g_pfnRTCCallBack_Tick  	= pfncallback;
;;;802       			break;
;;;803            }
;;;804            case DRVRTC_ALARM_INT:
;;;805            {
;;;806                g_bIsEnableAlarmInt  	= true;
;;;807        		RTC->RIER_BITS.AIER 			= 1; 
;;;808    			g_pfnRTCCallBack_Alarm 	= pfncallback;
;;;809                break;
;;;810            }
;;;811    		case DRVRTC_SNOOPER_INT:
;;;812            {
;;;813                g_bIsEnableSnooperInt  	= true;
;;;814        		RTC->RIER_BITS.SNOOPIER 			= 1; 
;;;815    			g_pfnRTCCallBack_Snooper 	= pfncallback;
;;;816                break;
;;;817            }
;;;818            default:
;;;819            {
;;;820                return E_DRVRTC_ERR_ENOTTY;
000014  480f              LDR      r0,|L4.84|
;;;821            }
;;;822        }
;;;823    	NVIC_EnableIRQ(RTC_IRQn); 
;;;824    
;;;825    	return E_SUCCESS;
;;;826    
;;;827    }
000016  bd10              POP      {r4,pc}
                  |L4.24|
000018  6154              STR      r4,[r2,#0x14]         ;799  ; g_bIsEnableTickInt
00001a  6a98              LDR      r0,[r3,#0x28]         ;800
00001c  2402              MOVS     r4,#2                 ;800
00001e  4320              ORRS     r0,r0,r4              ;800
000020  6298              STR      r0,[r3,#0x28]         ;800
000022  6051              STR      r1,[r2,#4]            ;802  ; g_pfnRTCCallBack_Tick
000024  e00b              B        |L4.62|
                  |L4.38|
000026  7054              STRB     r4,[r2,#1]            ;806
000028  6a98              LDR      r0,[r3,#0x28]         ;807
00002a  4320              ORRS     r0,r0,r4              ;807
00002c  6298              STR      r0,[r3,#0x28]         ;807
00002e  6091              STR      r1,[r2,#8]            ;809  ; g_pfnRTCCallBack_Alarm
000030  e005              B        |L4.62|
                  |L4.50|
000032  7094              STRB     r4,[r2,#2]            ;813
000034  6a98              LDR      r0,[r3,#0x28]         ;814
000036  2404              MOVS     r4,#4                 ;814
000038  4320              ORRS     r0,r0,r4              ;814
00003a  6298              STR      r0,[r3,#0x28]         ;814
00003c  60d1              STR      r1,[r2,#0xc]          ;815  ; g_pfnRTCCallBack_Snooper
                  |L4.62|
00003e  2001              MOVS     r0,#1                 ;815
000040  4905              LDR      r1,|L4.88|
000042  07c0              LSLS     r0,r0,#31             ;815
000044  6008              STR      r0,[r1,#0]            ;815
000046  2000              MOVS     r0,#0                 ;825
000048  bd10              POP      {r4,pc}
;;;828    
                          ENDP

00004a  0000              DCW      0x0000
                  |L4.76|
                          DCD      ||.data||
                  |L4.80|
                          DCD      0x40008000
                  |L4.84|
                          DCD      0xffff9206
                  |L4.88|
                          DCD      0xe000e100

                          AREA ||i.DrvRTC_EnableSpareFunc||, CODE, READONLY, ALIGN=2

                  DrvRTC_EnableSpareFunc PROC
;;;686      */
;;;687    void DrvRTC_EnableSpareFunc(E_DRVRTC_SNOOPER_EDGE eSpareEdge)
000000  b510              PUSH     {r4,lr}
;;;688    {
000002  4604              MOV      r4,r0
;;;689    	DrvRTC_WriteEnable();
000004  f7fffffe          BL       DrvRTC_WriteEnable
;;;690    
;;;691    	/* detection edge select */
;;;692    	RTC->SPRCTL_BITS.SNOOPEDGE = eSpareEdge;
000008  4909              LDR      r1,|L5.48|
00000a  6bc8              LDR      r0,[r1,#0x3c]
00000c  2202              MOVS     r2,#2
00000e  4390              BICS     r0,r0,r2
000010  07e2              LSLS     r2,r4,#31
000012  0f92              LSRS     r2,r2,#30
000014  4310              ORRS     r0,r0,r2
000016  63c8              STR      r0,[r1,#0x3c]
                  |L5.24|
;;;693    	while(RTC->SPRCTL_BITS.SPRRDY!=1) ;
000018  6bc8              LDR      r0,[r1,#0x3c]
00001a  0600              LSLS     r0,r0,#24
00001c  d5fc              BPL      |L5.24|
;;;694    	
;;;695    	/* enable snooper pin event detection */
;;;696    	RTC->SPRCTL_BITS.SNOOPEN = 1;
00001e  6bc8              LDR      r0,[r1,#0x3c]
000020  2201              MOVS     r2,#1
000022  4310              ORRS     r0,r0,r2
000024  63c8              STR      r0,[r1,#0x3c]
                  |L5.38|
;;;697    	while(RTC->SPRCTL_BITS.SPRRDY!=1) ;
000026  6bc8              LDR      r0,[r1,#0x3c]
000028  0600              LSLS     r0,r0,#24
00002a  d5fc              BPL      |L5.38|
;;;698    }
00002c  bd10              POP      {r4,pc}
;;;699    
                          ENDP

00002e  0000              DCW      0x0000
                  |L5.48|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_GetIntTick||, CODE, READONLY, ALIGN=2

                  DrvRTC_GetIntTick PROC
;;;721      */
;;;722    int32_t DrvRTC_GetIntTick(void)
000000  4801              LDR      r0,|L6.8|
;;;723    {
;;;724    	return g_u32RTC_Count;
000002  6900              LDR      r0,[r0,#0x10]  ; g_u32RTC_Count
;;;725    }
000004  4770              BX       lr
;;;726    
                          ENDP

000006  0000              DCW      0x0000
                  |L6.8|
                          DCD      ||.data||

                          AREA ||i.DrvRTC_GetVersion||, CODE, READONLY, ALIGN=2

                  DrvRTC_GetVersion PROC
;;;891      */
;;;892    int32_t DrvRTC_GetVersion (void)
000000  4800              LDR      r0,|L7.4|
;;;893    {
;;;894    	return DRVRTC_VERSION_NUM;
;;;895    }
000002  4770              BX       lr
;;;896    
                          ENDP

                  |L7.4|
                          DCD      0x00010001

                          AREA ||i.DrvRTC_Init||, CODE, READONLY, ALIGN=2

                  DrvRTC_Init PROC
;;;178      */
;;;179    int32_t DrvRTC_Init (void)
000000  b570              PUSH     {r4-r6,lr}
;;;180    {
;;;181        int32_t i32i =0;
;;;182    	volatile int32_t i32delay=1000;
;;;183    	uint32_t lock_sts = 0;
;;;184    
;;;185    	lock_sts = (GCR->RegLockAddr & 0x00000001) ? 0 : 1;  /* 0 for unlock, 1 for lock */
000002  4b1a              LDR      r3,|L8.108|
000004  217d              MOVS     r1,#0x7d              ;182
000006  6818              LDR      r0,[r3,#0]
000008  00c9              LSLS     r1,r1,#3              ;182
00000a  07c0              LSLS     r0,r0,#31
00000c  17c2              ASRS     r2,r0,#31
00000e  1c52              ADDS     r2,r2,#1
;;;186    
;;;187        /*-----------------------------------------------------------------------------------------------------*/
;;;188        /* Initial time data struct and some parameters.                                                       */
;;;189        /*-----------------------------------------------------------------------------------------------------*/
;;;190        g_pfnRTCCallBack_Alarm = NULL;
000010  4817              LDR      r0,|L8.112|
000012  2400              MOVS     r4,#0
;;;191        g_pfnRTCCallBack_Tick = NULL;
000014  6084              STR      r4,[r0,#8]  ; g_pfnRTCCallBack_Alarm
;;;192    	g_pfnRTCCallBack_Snooper = NULL;
000016  6044              STR      r4,[r0,#4]  ; g_pfnRTCCallBack_Tick
;;;193    
;;;194        g_u32RTC_Count = 0;
000018  60c4              STR      r4,[r0,#0xc]  ; g_pfnRTCCallBack_Snooper
00001a  6104              STR      r4,[r0,#0x10]  ; g_u32RTC_Count
;;;195    
;;;196    	/* un-lock */
;;;197    	if (lock_sts)	UNLOCKREG();
00001c  2a00              CMP      r2,#0
00001e  d001              BEQ      |L8.36|
000020  2059              MOVS     r0,#0x59
000022  6018              STR      r0,[r3,#0]
                  |L8.36|
000024  2016              MOVS     r0,#0x16
000026  6018              STR      r0,[r3,#0]
000028  2088              MOVS     r0,#0x88
00002a  6018              STR      r0,[r3,#0]
;;;198    	/* Enable 32K Clock */
;;;199    	CLK->PWRCTL_BITS.LXT_EN =1;
00002c  4d11              LDR      r5,|L8.116|
00002e  6828              LDR      r0,[r5,#0]
000030  2602              MOVS     r6,#2
000032  4330              ORRS     r0,r0,r6
000034  6028              STR      r0,[r5,#0]
                  |L8.54|
;;;200    	  
;;;201    	/* Waiting for 32K stable */
;;;202      	while(i32delay--);
000036  4608              MOV      r0,r1
000038  1e49              SUBS     r1,r1,#1
00003a  2800              CMP      r0,#0
00003c  d1fb              BNE      |L8.54|
;;;203    	
;;;204    	/* Enable RTC Clock */
;;;205    	CLK->APBCLK_BITS.RTC_EN =1;
00003e  68a8              LDR      r0,[r5,#8]
000040  4330              ORRS     r0,r0,r6
000042  60a8              STR      r0,[r5,#8]
;;;206    	
;;;207    	if (lock_sts)	LOCKREG();
000044  2a00              CMP      r2,#0
000046  d000              BEQ      |L8.74|
000048  601c              STR      r4,[r3,#0]
                  |L8.74|
;;;208    
;;;209        /*-----------------------------------------------------------------------------------------------------*/
;;;210        /* When RTC is power on, write 0xa5eb1357 to RTC_INIR to reset all logic.                              */
;;;211        /*-----------------------------------------------------------------------------------------------------*/
;;;212    	
;;;213    	RTC->INIR = DRVRTC_INIT_KEY;
00004a  490c              LDR      r1,|L8.124|
00004c  480a              LDR      r0,|L8.120|
00004e  6008              STR      r0,[r1,#0]
;;;214    
;;;215        for (i32i = 0 ; i32i < DRVRTC_WAIT_COUNT ; i32i++)
000050  2000              MOVS     r0,#0
                  |L8.82|
;;;216        {
;;;217    
;;;218    		if(RTC->INIR == 0x1)  /* Check RTC_INIR[0] to find out RTC reset signal */
000052  680a              LDR      r2,[r1,#0]
000054  2a01              CMP      r2,#1
000056  d003              BEQ      |L8.96|
000058  1c40              ADDS     r0,r0,#1              ;215
00005a  1c42              ADDS     r2,r0,#1              ;215
00005c  d1f9              BNE      |L8.82|
00005e  e003              B        |L8.104|
                  |L8.96|
;;;219            { 
;;;220                break;
;;;221            }
;;;222        }
;;;223    
;;;224        if (i32i == DRVRTC_WAIT_COUNT)
000060  1c40              ADDS     r0,r0,#1
000062  d001              BEQ      |L8.104|
;;;225        {
;;;226            RTCDEBUG("\nRTC: DrvRTC_Init, initial RTC FAILED!\n");
;;;227            return E_DRVRTC_ERR_EIO;
;;;228        }
;;;229    
;;;230        return E_SUCCESS;
000064  2000              MOVS     r0,#0
;;;231    }
000066  bd70              POP      {r4-r6,pc}
                  |L8.104|
000068  4805              LDR      r0,|L8.128|
00006a  bd70              POP      {r4-r6,pc}
;;;232    
                          ENDP

                  |L8.108|
                          DCD      0x50000100
                  |L8.112|
                          DCD      ||.data||
                  |L8.116|
                          DCD      0x50000200
                  |L8.120|
                          DCD      0xa5eb1357
                  |L8.124|
                          DCD      0x40008000
                  |L8.128|
                          DCD      0xffff9205

                          AREA ||i.DrvRTC_IsLeapYear||, CODE, READONLY, ALIGN=2

                  DrvRTC_IsLeapYear PROC
;;;745      */
;;;746    int32_t DrvRTC_IsLeapYear(void)
000000  4802              LDR      r0,|L9.12|
;;;747    {
;;;748    	return (RTC->LIR_BITS.LIR == 0x1)?1:0;
000002  6a40              LDR      r0,[r0,#0x24]
000004  07c0              LSLS     r0,r0,#31
000006  0fc0              LSRS     r0,r0,#31
;;;749    }
000008  4770              BX       lr
;;;750    
                          ENDP

00000a  0000              DCW      0x0000
                  |L9.12|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_Open||, CODE, READONLY, ALIGN=2

                  DrvRTC_Open PROC
;;;240      */
;;;241    int32_t DrvRTC_Open (S_DRVRTC_TIME_DATA_T *sPt)
000000  b5f8              PUSH     {r3-r7,lr}
;;;242    {
;;;243        uint32_t u32Reg;
;;;244    	
;;;245    	volatile int32_t i32delay=1000;
000002  267d              MOVS     r6,#0x7d
000004  4604              MOV      r4,r0                 ;242
000006  00f6              LSLS     r6,r6,#3
;;;246            
;;;247        /*-----------------------------------------------------------------------------------------------------*/
;;;248        /* DO BASIC JUDGEMENT TO Check RTC time data value is reasonable or not.                               */
;;;249        /*-----------------------------------------------------------------------------------------------------*/
;;;250    	assert_param(	!( ((sPt->u32Year - DRVRTC_YEAR2000) > 99)|
;;;251    							((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12))|
;;;252    							((sPt->u32cDay   == 0) || (sPt->u32cDay   > 31))));
;;;253    
;;;254    	assert_param( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) || (sPt->u8cClockDisplay==DRVRTC_CLOCK_24));
;;;255    
;;;256    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) &&
;;;257    							((sPt->u32cHour == 0) || (sPt->u32cHour > 12))));
;;;258    
;;;259    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_24) &&
;;;260    							(sPt->u32cHour > 23)));
;;;261    
;;;262    	assert_param(	!((sPt->u32cMinute > 59) |
;;;263    							(sPt->u32cSecond > 59) |
;;;264    							(sPt->u32cSecond > 59)));
;;;265    
;;;266    	assert_param( !(sPt->u32cDayOfWeek > 6) );
;;;267    
;;;268    
;;;269        /*-----------------------------------------------------------------------------------------------------*/
;;;270        /* Important, call DrvRTC_WriteEnable() before write data into any register.                              */
;;;271        /* User should be write data as soon as possible.Access enable wiil clear after 200ms                  */
;;;272    	/*-----------------------------------------------------------------------------------------------------*/
;;;273        g_u32Reg = DrvRTC_WriteEnable();
000008  f7fffffe          BL       DrvRTC_WriteEnable
00000c  4601              MOV      r1,r0
00000e  4838              LDR      r0,|L10.240|
000010  6181              STR      r1,[r0,#0x18]  ; g_u32Reg
;;;274        if (g_u32Reg != 0)
000012  6980              LDR      r0,[r0,#0x18]  ; g_u32Reg
000014  2800              CMP      r0,#0
000016  d001              BEQ      |L10.28|
;;;275        {
;;;276            return E_DRVRTC_ERR_FAILED;
000018  4836              LDR      r0,|L10.244|
;;;277        }
;;;278        
;;;279        /*-----------------------------------------------------------------------------------------------------*/
;;;280        /* Second, set RTC 24/12 hour setting                                                                  */
;;;281        /*-----------------------------------------------------------------------------------------------------*/
;;;282        if (sPt->u8cClockDisplay == DRVRTC_CLOCK_12)
;;;283        {
;;;284            DrvRTC_WriteEnable();
;;;285     		RTC->TSSR_BITS.HR24 = DRVRTC_CLOCK_12;
;;;286    
;;;287            /*-------------------------------------------------------------------------------------------------*/
;;;288            /* important, range of 12-hour PM mode is 21 upto 32                                               */
;;;289            /*-------------------------------------------------------------------------------------------------*/
;;;290            if (sPt->u8cAmPm == DRVRTC_PM)
;;;291                sPt->u32cHour += 20;
;;;292        }
;;;293        else                                                                               /* DRVRTC_CLOCK_24 */
;;;294        {
;;;295    
;;;296            DrvRTC_WriteEnable();
;;;297     		RTC->TSSR_BITS.HR24 = DRVRTC_CLOCK_24;
;;;298            RTCDEBUG ("RTC: 24-hour\n");
;;;299        }
;;;300    
;;;301        /*-----------------------------------------------------------------------------------------------------*/
;;;302        /* Set RTC Calender Loading                                                                            */
;;;303        /*-----------------------------------------------------------------------------------------------------*/
;;;304        u32Reg    = ((sPt->u32Year - DRVRTC_YEAR2000) / 10) << 20;
;;;305        u32Reg    |= (((sPt->u32Year - DRVRTC_YEAR2000) % 10) << 16);
;;;306        u32Reg    |= ((sPt->u32cMonth  / 10) << 12);
;;;307        u32Reg    |= ((sPt->u32cMonth  % 10) << 8);
;;;308        u32Reg    |= ((sPt->u32cDay    / 10) << 4);
;;;309        u32Reg    |= (sPt->u32cDay     % 10);
;;;310        g_u32Reg = u32Reg;
;;;311    	
;;;312    	DrvRTC_WriteEnable();
;;;313     	RTC->TSSR_BITS.HR24 = DRVRTC_CLOCK_24;
;;;314        RTC->CLR = (uint32_t)g_u32Reg;
;;;315    
;;;316    	/*-----------------------------------------------------------------------------------------------------*/
;;;317        /* Set RTC Time Loading                                                                                */
;;;318        /*-----------------------------------------------------------------------------------------------------*/
;;;319        u32Reg     = ((sPt->u32cHour / 10) << 20);
;;;320        u32Reg    |= ((sPt->u32cHour % 10) << 16);
;;;321        u32Reg    |= ((sPt->u32cMinute / 10) << 12);
;;;322        u32Reg    |= ((sPt->u32cMinute % 10) << 8);
;;;323        u32Reg    |= ((sPt->u32cSecond / 10) << 4);
;;;324        u32Reg    |= (sPt->u32cSecond % 10);
;;;325        g_u32Reg = u32Reg;
;;;326    
;;;327     	DrvRTC_WriteEnable();
;;;328        RTC->TLR = (uint32_t)g_u32Reg;
;;;329    
;;;330    	RTC->DWR = sPt->u32cDayOfWeek;
;;;331    
;;;332    	RTC->TTR_BITS.TWKE = sPt->u8IsEnableWakeUp;
;;;333    
;;;334    	/* Waiting for RTC settings stable */
;;;335      	while(i32delay--);
;;;336    
;;;337        return E_SUCCESS;
;;;338    }
00001a  bdf8              POP      {r3-r7,pc}
                  |L10.28|
00001c  7820              LDRB     r0,[r4,#0]            ;282
00001e  4d36              LDR      r5,|L10.248|
000020  2800              CMP      r0,#0                 ;282
000022  d058              BEQ      |L10.214|
000024  f7fffffe          BL       DrvRTC_WriteEnable
000028  6968              LDR      r0,[r5,#0x14]         ;297
00002a  2101              MOVS     r1,#1                 ;297
00002c  4308              ORRS     r0,r0,r1              ;297
00002e  6168              STR      r0,[r5,#0x14]         ;297
                  |L10.48|
000030  207d              MOVS     r0,#0x7d              ;304
000032  69e1              LDR      r1,[r4,#0x1c]         ;304
000034  0100              LSLS     r0,r0,#4              ;304
000036  1a08              SUBS     r0,r1,r0              ;304
000038  210a              MOVS     r1,#0xa               ;304
00003a  f7fffffe          BL       __aeabi_uidivmod
00003e  040f              LSLS     r7,r1,#16             ;305
000040  0500              LSLS     r0,r0,#20             ;304
000042  4307              ORRS     r7,r7,r0              ;305
000044  210a              MOVS     r1,#0xa               ;306
000046  69a0              LDR      r0,[r4,#0x18]         ;306
000048  f7fffffe          BL       __aeabi_uidivmod
00004c  0300              LSLS     r0,r0,#12             ;306
00004e  4338              ORRS     r0,r0,r7              ;306
000050  020f              LSLS     r7,r1,#8              ;307
000052  4307              ORRS     r7,r7,r0              ;307
000054  210a              MOVS     r1,#0xa               ;308
000056  6960              LDR      r0,[r4,#0x14]         ;308
000058  f7fffffe          BL       __aeabi_uidivmod
00005c  0100              LSLS     r0,r0,#4              ;308
00005e  4338              ORRS     r0,r0,r7              ;308
000060  4f23              LDR      r7,|L10.240|
000062  4301              ORRS     r1,r1,r0              ;309
000064  61b9              STR      r1,[r7,#0x18]         ;310  ; g_u32Reg
000066  f7fffffe          BL       DrvRTC_WriteEnable
00006a  6968              LDR      r0,[r5,#0x14]         ;313
00006c  2101              MOVS     r1,#1                 ;313
00006e  4308              ORRS     r0,r0,r1              ;313
000070  6168              STR      r0,[r5,#0x14]         ;313
000072  69b8              LDR      r0,[r7,#0x18]         ;314  ; g_u32Reg
000074  6128              STR      r0,[r5,#0x10]         ;314
000076  210a              MOVS     r1,#0xa               ;319
000078  68e0              LDR      r0,[r4,#0xc]          ;319
00007a  f7fffffe          BL       __aeabi_uidivmod
00007e  040a              LSLS     r2,r1,#16             ;320
000080  0500              LSLS     r0,r0,#20             ;319
000082  4302              ORRS     r2,r2,r0              ;320
000084  9200              STR      r2,[sp,#0]            ;321
000086  210a              MOVS     r1,#0xa               ;321
000088  68a0              LDR      r0,[r4,#8]            ;321
00008a  f7fffffe          BL       __aeabi_uidivmod
00008e  9a00              LDR      r2,[sp,#0]            ;321
000090  0300              LSLS     r0,r0,#12             ;321
000092  4310              ORRS     r0,r0,r2              ;321
000094  020a              LSLS     r2,r1,#8              ;322
000096  4302              ORRS     r2,r2,r0              ;322
000098  9200              STR      r2,[sp,#0]            ;323
00009a  210a              MOVS     r1,#0xa               ;323
00009c  6860              LDR      r0,[r4,#4]            ;323
00009e  f7fffffe          BL       __aeabi_uidivmod
0000a2  9a00              LDR      r2,[sp,#0]            ;323
0000a4  0100              LSLS     r0,r0,#4              ;323
0000a6  4310              ORRS     r0,r0,r2              ;323
0000a8  4301              ORRS     r1,r1,r0              ;324
0000aa  61b9              STR      r1,[r7,#0x18]         ;325  ; g_u32Reg
0000ac  f7fffffe          BL       DrvRTC_WriteEnable
0000b0  69b8              LDR      r0,[r7,#0x18]         ;328  ; g_u32Reg
0000b2  60e8              STR      r0,[r5,#0xc]          ;328
0000b4  6920              LDR      r0,[r4,#0x10]         ;330
0000b6  61a8              STR      r0,[r5,#0x18]         ;330
0000b8  6b28              LDR      r0,[r5,#0x30]         ;332
0000ba  2108              MOVS     r1,#8                 ;332
0000bc  4388              BICS     r0,r0,r1              ;332
0000be  3420              ADDS     r4,r4,#0x20           ;332
0000c0  7821              LDRB     r1,[r4,#0]            ;332
0000c2  07c9              LSLS     r1,r1,#31             ;332
0000c4  0f09              LSRS     r1,r1,#28             ;332
0000c6  4308              ORRS     r0,r0,r1              ;332
0000c8  6328              STR      r0,[r5,#0x30]         ;332
                  |L10.202|
0000ca  4635              MOV      r5,r6                 ;335
0000cc  1e76              SUBS     r6,r6,#1              ;335
0000ce  2d00              CMP      r5,#0                 ;335
0000d0  d1fb              BNE      |L10.202|
0000d2  2000              MOVS     r0,#0                 ;337
0000d4  bdf8              POP      {r3-r7,pc}
                  |L10.214|
0000d6  f7fffffe          BL       DrvRTC_WriteEnable
0000da  6968              LDR      r0,[r5,#0x14]         ;285
0000dc  0840              LSRS     r0,r0,#1              ;285
0000de  0040              LSLS     r0,r0,#1              ;285
0000e0  6168              STR      r0,[r5,#0x14]         ;285
0000e2  7860              LDRB     r0,[r4,#1]            ;290
0000e4  2802              CMP      r0,#2                 ;290
0000e6  d1a3              BNE      |L10.48|
0000e8  68e0              LDR      r0,[r4,#0xc]          ;291
0000ea  3014              ADDS     r0,r0,#0x14           ;291
0000ec  60e0              STR      r0,[r4,#0xc]          ;291
0000ee  e79f              B        |L10.48|
;;;339    
                          ENDP

                  |L10.240|
                          DCD      ||.data||
                  |L10.244|
                          DCD      0xffff9208
                  |L10.248|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_Read||, CODE, READONLY, ALIGN=2

                  DrvRTC_Read PROC
;;;348      */
;;;349    int32_t DrvRTC_Read (E_DRVRTC_TIME_SELECT eTime, S_DRVRTC_TIME_DATA_T *sPt)
000000  b510              PUSH     {r4,lr}
;;;350    {
;;;351        uint32_t u32Tmp;
;;;352        
;;;353        sPt->u8cClockDisplay = RTC->TSSR_BITS.HR24;                                 /* 12/24-hour */
000002  4b53              LDR      r3,|L11.336|
000004  695a              LDR      r2,[r3,#0x14]
000006  07d4              LSLS     r4,r2,#31
000008  0fe4              LSRS     r4,r4,#31
00000a  700c              STRB     r4,[r1,#0]
;;;354        sPt->u32cDayOfWeek   = RTC->DWR_BITS.DWR;                                   /* Day of week */
00000c  699a              LDR      r2,[r3,#0x18]
00000e  0752              LSLS     r2,r2,#29
000010  0f52              LSRS     r2,r2,#29
;;;355    
;;;356        switch (eTime)
;;;357        {
;;;358            case DRVRTC_CURRENT_TIME:										   /* Get Current Time */
;;;359            {
;;;360    			g_u32hiYear  = RTC->CLR_BITS.TEN_YEAR;
000012  610a              STR      r2,[r1,#0x10]
000014  4a4f              LDR      r2,|L11.340|
000016  2800              CMP      r0,#0                 ;356
000018  d003              BEQ      |L11.34|
00001a  2801              CMP      r0,#1                 ;356
00001c  d02f              BEQ      |L11.126|
;;;361        		g_u32loYear  = RTC->CLR_BITS.YEAR;
;;;362        		g_u32hiMonth = RTC->CLR_BITS.TEN_MON;
;;;363        		g_u32loMonth = RTC->CLR_BITS.MON;
;;;364        		g_u32hiDay   = RTC->CLR_BITS.TEN_DAY;
;;;365        		g_u32loDay   = RTC->CLR_BITS.DAY;
;;;366    
;;;367    		    g_u32hiHour =  RTC->TLR_BITS.TEN_HR;
;;;368        		g_u32loHour =  RTC->TLR_BITS.HR;
;;;369        		g_u32hiMin  =  RTC->TLR_BITS.TEN_MIN;
;;;370        		g_u32loMin  =  RTC->TLR_BITS.MIN;
;;;371        		g_u32hiSec  =  RTC->TLR_BITS.TEN_SEC;
;;;372        		g_u32loSec  =  RTC->TLR_BITS.SEC;
;;;373                break;
;;;374    		}
;;;375            case DRVRTC_ALARM_TIME:									 	/* Get Alarm Time */
;;;376            {
;;;377    			g_u32hiYear  = RTC->CAR_BITS.TEN_YEAR;
;;;378        		g_u32loYear  = RTC->CAR_BITS.YEAR;
;;;379        		g_u32hiMonth = RTC->CAR_BITS.TEN_MON;
;;;380        		g_u32loMonth = RTC->CAR_BITS.MON;
;;;381        		g_u32hiDay   = RTC->CAR_BITS.TEN_DAY;
;;;382        		g_u32loDay   = RTC->CAR_BITS.DAY;
;;;383    
;;;384    		    g_u32hiHour =  RTC->TAR_BITS.TEN_HR;
;;;385        		g_u32loHour =  RTC->TAR_BITS.HR;
;;;386        		g_u32hiMin  =  RTC->TAR_BITS.TEN_MIN;
;;;387        		g_u32loMin  =  RTC->TAR_BITS.MIN;
;;;388        		g_u32hiSec  =  RTC->TAR_BITS.TEN_SEC;
;;;389        		g_u32loSec  =  RTC->TAR_BITS.SEC;
;;;390                break;
;;;391            }
;;;392            default:
;;;393            {
;;;394                return E_DRVRTC_ERR_ENOTTY;
00001e  484e              LDR      r0,|L11.344|
;;;395            }
;;;396        }
;;;397    
;;;398        u32Tmp = (g_u32hiYear * 10);									/* Compute to 20XX year */
;;;399        u32Tmp+= g_u32loYear;
;;;400        sPt->u32Year   =   u32Tmp  + DRVRTC_YEAR2000;
;;;401        
;;;402        u32Tmp = (g_u32hiMonth * 10);									/* Compute 0~12 month */
;;;403        sPt->u32cMonth = u32Tmp + g_u32loMonth;
;;;404        
;;;405        u32Tmp = (g_u32hiDay * 10);										/* Compute 0~31 day */
;;;406        sPt->u32cDay   =  u32Tmp  + g_u32loDay;
;;;407    
;;;408        if (sPt->u8cClockDisplay == DRVRTC_CLOCK_12)					/* Compute12/24 hout */
;;;409        {
;;;410            u32Tmp = (g_u32hiHour * 10);
;;;411            u32Tmp+= g_u32loHour;
;;;412            sPt->u32cHour = u32Tmp;                                		/* AM: 1~12. PM: 21~32. */
;;;413    
;;;414            if (sPt->u32cHour >= 21)
;;;415            {
;;;416                sPt->u8cAmPm = DRVRTC_PM;
;;;417                sPt->u32cHour -= 20;
;;;418            }
;;;419            else
;;;420            {
;;;421                sPt->u8cAmPm = DRVRTC_AM;
;;;422            }
;;;423            
;;;424            u32Tmp = (g_u32hiMin  * 10);
;;;425            u32Tmp+= g_u32loMin;
;;;426            sPt->u32cMinute = u32Tmp;
;;;427            
;;;428            u32Tmp = (g_u32hiSec  * 10);
;;;429            u32Tmp+= g_u32loSec;
;;;430            sPt->u32cSecond = u32Tmp;
;;;431    
;;;432        }
;;;433        else
;;;434        {   															/* DRVRTC_CLOCK_24 */
;;;435            u32Tmp = (g_u32hiHour * 10);
;;;436            u32Tmp+= g_u32loHour;
;;;437            sPt->u32cHour   = u32Tmp;
;;;438            
;;;439            u32Tmp = (g_u32hiMin  * 10);
;;;440            u32Tmp+= g_u32loMin;
;;;441            sPt->u32cMinute = u32Tmp;
;;;442            
;;;443            u32Tmp = (g_u32hiSec  * 10);
;;;444            u32Tmp+= g_u32loSec;
;;;445            sPt->u32cSecond = u32Tmp;
;;;446        }
;;;447    
;;;448        return E_SUCCESS;
;;;449    
;;;450    }
000020  bd10              POP      {r4,pc}
                  |L11.34|
000022  6918              LDR      r0,[r3,#0x10]         ;360
000024  0200              LSLS     r0,r0,#8              ;360
000026  0f00              LSRS     r0,r0,#28             ;360
000028  61d0              STR      r0,[r2,#0x1c]         ;360  ; g_u32hiYear
00002a  6918              LDR      r0,[r3,#0x10]         ;361
00002c  0300              LSLS     r0,r0,#12             ;361
00002e  0f00              LSRS     r0,r0,#28             ;361
000030  6210              STR      r0,[r2,#0x20]         ;361  ; g_u32loYear
000032  6918              LDR      r0,[r3,#0x10]         ;362
000034  04c0              LSLS     r0,r0,#19             ;362
000036  0fc0              LSRS     r0,r0,#31             ;362
000038  6250              STR      r0,[r2,#0x24]         ;362  ; g_u32hiMonth
00003a  6918              LDR      r0,[r3,#0x10]         ;363
00003c  0500              LSLS     r0,r0,#20             ;363
00003e  0f00              LSRS     r0,r0,#28             ;363
000040  6290              STR      r0,[r2,#0x28]         ;363  ; g_u32loMonth
000042  6918              LDR      r0,[r3,#0x10]         ;364
000044  0680              LSLS     r0,r0,#26             ;364
000046  0f80              LSRS     r0,r0,#30             ;364
000048  62d0              STR      r0,[r2,#0x2c]         ;364  ; g_u32hiDay
00004a  6918              LDR      r0,[r3,#0x10]         ;365
00004c  0700              LSLS     r0,r0,#28             ;365
00004e  0f00              LSRS     r0,r0,#28             ;365
000050  6310              STR      r0,[r2,#0x30]         ;365  ; g_u32loDay
000052  68d8              LDR      r0,[r3,#0xc]          ;367
000054  0280              LSLS     r0,r0,#10             ;367
000056  0f80              LSRS     r0,r0,#30             ;367
000058  6350              STR      r0,[r2,#0x34]         ;367  ; g_u32hiHour
00005a  68d8              LDR      r0,[r3,#0xc]          ;368
00005c  0300              LSLS     r0,r0,#12             ;368
00005e  0f00              LSRS     r0,r0,#28             ;368
000060  6390              STR      r0,[r2,#0x38]         ;368  ; g_u32loHour
000062  68d8              LDR      r0,[r3,#0xc]          ;369
000064  0440              LSLS     r0,r0,#17             ;369
000066  0f40              LSRS     r0,r0,#29             ;369
000068  63d0              STR      r0,[r2,#0x3c]         ;369  ; g_u32hiMin
00006a  68d8              LDR      r0,[r3,#0xc]          ;370
00006c  0500              LSLS     r0,r0,#20             ;370
00006e  0f00              LSRS     r0,r0,#28             ;370
000070  6410              STR      r0,[r2,#0x40]         ;370  ; g_u32loMin
000072  68d8              LDR      r0,[r3,#0xc]          ;371
000074  0640              LSLS     r0,r0,#25             ;371
000076  0f40              LSRS     r0,r0,#29             ;371
000078  6450              STR      r0,[r2,#0x44]         ;371  ; g_u32hiSec
00007a  68d8              LDR      r0,[r3,#0xc]          ;372
00007c  e02c              B        |L11.216|
                  |L11.126|
00007e  6a18              LDR      r0,[r3,#0x20]         ;377
000080  0200              LSLS     r0,r0,#8              ;377
000082  0f00              LSRS     r0,r0,#28             ;377
000084  61d0              STR      r0,[r2,#0x1c]         ;377  ; g_u32hiYear
000086  6a18              LDR      r0,[r3,#0x20]         ;378
000088  0300              LSLS     r0,r0,#12             ;378
00008a  0f00              LSRS     r0,r0,#28             ;378
00008c  6210              STR      r0,[r2,#0x20]         ;378  ; g_u32loYear
00008e  6a18              LDR      r0,[r3,#0x20]         ;379
000090  04c0              LSLS     r0,r0,#19             ;379
000092  0fc0              LSRS     r0,r0,#31             ;379
000094  6250              STR      r0,[r2,#0x24]         ;379  ; g_u32hiMonth
000096  6a18              LDR      r0,[r3,#0x20]         ;380
000098  0500              LSLS     r0,r0,#20             ;380
00009a  0f00              LSRS     r0,r0,#28             ;380
00009c  6290              STR      r0,[r2,#0x28]         ;380  ; g_u32loMonth
00009e  6a18              LDR      r0,[r3,#0x20]         ;381
0000a0  0680              LSLS     r0,r0,#26             ;381
0000a2  0f80              LSRS     r0,r0,#30             ;381
0000a4  62d0              STR      r0,[r2,#0x2c]         ;381  ; g_u32hiDay
0000a6  6a18              LDR      r0,[r3,#0x20]         ;382
0000a8  0700              LSLS     r0,r0,#28             ;382
0000aa  0f00              LSRS     r0,r0,#28             ;382
0000ac  6310              STR      r0,[r2,#0x30]         ;382  ; g_u32loDay
0000ae  69d8              LDR      r0,[r3,#0x1c]         ;384
0000b0  0280              LSLS     r0,r0,#10             ;384
0000b2  0f80              LSRS     r0,r0,#30             ;384
0000b4  6350              STR      r0,[r2,#0x34]         ;384  ; g_u32hiHour
0000b6  69d8              LDR      r0,[r3,#0x1c]         ;385
0000b8  0300              LSLS     r0,r0,#12             ;385
0000ba  0f00              LSRS     r0,r0,#28             ;385
0000bc  6390              STR      r0,[r2,#0x38]         ;385  ; g_u32loHour
0000be  69d8              LDR      r0,[r3,#0x1c]         ;386
0000c0  0440              LSLS     r0,r0,#17             ;386
0000c2  0f40              LSRS     r0,r0,#29             ;386
0000c4  63d0              STR      r0,[r2,#0x3c]         ;386  ; g_u32hiMin
0000c6  69d8              LDR      r0,[r3,#0x1c]         ;387
0000c8  0500              LSLS     r0,r0,#20             ;387
0000ca  0f00              LSRS     r0,r0,#28             ;387
0000cc  6410              STR      r0,[r2,#0x40]         ;387  ; g_u32loMin
0000ce  69d8              LDR      r0,[r3,#0x1c]         ;388
0000d0  0640              LSLS     r0,r0,#25             ;388
0000d2  0f40              LSRS     r0,r0,#29             ;388
0000d4  6450              STR      r0,[r2,#0x44]         ;388  ; g_u32hiSec
0000d6  69d8              LDR      r0,[r3,#0x1c]         ;389
                  |L11.216|
0000d8  0700              LSLS     r0,r0,#28             ;372
0000da  0f00              LSRS     r0,r0,#28             ;372
0000dc  6490              STR      r0,[r2,#0x48]         ;372  ; g_u32loSec
0000de  69d0              LDR      r0,[r2,#0x1c]         ;398  ; g_u32hiYear
0000e0  230a              MOVS     r3,#0xa               ;398
0000e2  4358              MULS     r0,r3,r0              ;398
0000e4  6a13              LDR      r3,[r2,#0x20]         ;399  ; g_u32loYear
0000e6  18c0              ADDS     r0,r0,r3              ;399
0000e8  237d              MOVS     r3,#0x7d              ;400
0000ea  011b              LSLS     r3,r3,#4              ;400
0000ec  18c0              ADDS     r0,r0,r3              ;400
0000ee  61c8              STR      r0,[r1,#0x1c]         ;402
0000f0  6a50              LDR      r0,[r2,#0x24]         ;402  ; g_u32hiMonth
0000f2  230a              MOVS     r3,#0xa               ;402
0000f4  4358              MULS     r0,r3,r0              ;402
0000f6  6a93              LDR      r3,[r2,#0x28]         ;403  ; g_u32loMonth
0000f8  18c0              ADDS     r0,r0,r3              ;403
0000fa  6188              STR      r0,[r1,#0x18]         ;405
0000fc  6ad0              LDR      r0,[r2,#0x2c]         ;405  ; g_u32hiDay
0000fe  230a              MOVS     r3,#0xa               ;405
000100  4358              MULS     r0,r3,r0              ;405
000102  6b13              LDR      r3,[r2,#0x30]         ;406  ; g_u32loDay
000104  18c0              ADDS     r0,r0,r3              ;406
000106  6148              STR      r0,[r1,#0x14]         ;408
000108  6b50              LDR      r0,[r2,#0x34]         ;435  ; g_u32hiHour
00010a  2c00              CMP      r4,#0                 ;408
00010c  d004              BEQ      |L11.280|
00010e  230a              MOVS     r3,#0xa               ;435
000110  4358              MULS     r0,r3,r0              ;435
000112  6b93              LDR      r3,[r2,#0x38]         ;436  ; g_u32loHour
000114  18c0              ADDS     r0,r0,r3              ;436
000116  e009              B        |L11.300|
                  |L11.280|
000118  230a              MOVS     r3,#0xa               ;410
00011a  4358              MULS     r0,r3,r0              ;410
00011c  6b93              LDR      r3,[r2,#0x38]         ;411  ; g_u32loHour
00011e  18c0              ADDS     r0,r0,r3              ;411
000120  60c8              STR      r0,[r1,#0xc]          ;414
000122  2815              CMP      r0,#0x15              ;414
000124  d304              BCC      |L11.304|
000126  2302              MOVS     r3,#2                 ;416
000128  704b              STRB     r3,[r1,#1]            ;416
00012a  3814              SUBS     r0,r0,#0x14           ;417
                  |L11.300|
00012c  60c8              STR      r0,[r1,#0xc]          ;437
00012e  e001              B        |L11.308|
                  |L11.304|
000130  2001              MOVS     r0,#1                 ;421
000132  7048              STRB     r0,[r1,#1]            ;421
                  |L11.308|
000134  6bd0              LDR      r0,[r2,#0x3c]         ;424  ; g_u32hiMin
000136  230a              MOVS     r3,#0xa               ;424
000138  4358              MULS     r0,r3,r0              ;424
00013a  6c13              LDR      r3,[r2,#0x40]         ;425  ; g_u32loMin
00013c  18c0              ADDS     r0,r0,r3              ;425
00013e  6088              STR      r0,[r1,#8]            ;428
000140  6c50              LDR      r0,[r2,#0x44]         ;428  ; g_u32hiSec
000142  230a              MOVS     r3,#0xa               ;428
000144  6c92              LDR      r2,[r2,#0x48]         ;429  ; g_u32loSec
000146  4358              MULS     r0,r3,r0              ;428
000148  1880              ADDS     r0,r0,r2              ;429
00014a  6048              STR      r0,[r1,#4]            ;448
00014c  2000              MOVS     r0,#0                 ;448
00014e  bd10              POP      {r4,pc}
;;;451    
                          ENDP

                  |L11.336|
                          DCD      0x40008000
                  |L11.340|
                          DCD      ||.data||
                  |L11.344|
                          DCD      0xffff9206

                          AREA ||i.DrvRTC_ResetIntTick||, CODE, READONLY, ALIGN=2

                  DrvRTC_ResetIntTick PROC
;;;732      */
;;;733    void DrvRTC_ResetIntTick(void)
000000  4901              LDR      r1,|L12.8|
;;;734    {
;;;735    	g_u32RTC_Count = 0;
000002  2000              MOVS     r0,#0
000004  6108              STR      r0,[r1,#0x10]  ; g_u32RTC_Count
;;;736    }
000006  4770              BX       lr
;;;737    
                          ENDP

                  |L12.8|
                          DCD      ||.data||

                          AREA ||i.DrvRTC_SetFrequencyCompensation||, CODE, READONLY, ALIGN=2

                  DrvRTC_SetFrequencyCompensation PROC
;;;98       */
;;;99     int32_t DrvRTC_SetFrequencyCompensation(int32_t i32FrequencyX100)
000000  b570              PUSH     {r4-r6,lr}
;;;100    {
;;;101        int32_t i32RegInt,i32RegFra ;
;;;102    
;;;103    	/* Compute Interger and Fraction for RTC register*/
;;;104        i32RegInt = (i32FrequencyX100/100) - DRVRTC_FCR_REFERENCE;
000002  2164              MOVS     r1,#0x64
000004  f7fffffe          BL       __aeabi_idivmod
000008  4a0c              LDR      r2,|L13.60|
00000a  1884              ADDS     r4,r0,r2
;;;105        i32RegFra = (((i32FrequencyX100%100)) * 60) / 100;
00000c  203c              MOVS     r0,#0x3c
00000e  4348              MULS     r0,r1,r0
000010  2164              MOVS     r1,#0x64
000012  f7fffffe          BL       __aeabi_idivmod
000016  4605              MOV      r5,r0
;;;106        
;;;107    	/* Judge Interger part is reasonable */
;;;108        if ( (i32RegInt < 0) | (i32RegInt > 15) )
000018  0fe0              LSRS     r0,r4,#31
00001a  2c0f              CMP      r4,#0xf
00001c  dd01              BLE      |L13.34|
00001e  2101              MOVS     r1,#1
000020  e000              B        |L13.36|
                  |L13.34|
000022  2100              MOVS     r1,#0
                  |L13.36|
000024  4308              ORRS     r0,r0,r1
000026  d001              BEQ      |L13.44|
;;;109        {
;;;110            return E_DRVRTC_ERR_FCR_VALUE ;
000028  4805              LDR      r0,|L13.64|
;;;111        }
;;;112    	
;;;113    	DrvRTC_WriteEnable();
;;;114    
;;;115    	RTC->FCR = (uint32_t)((i32RegInt<<8) | i32RegFra);
;;;116    
;;;117        return E_SUCCESS;
;;;118    }
00002a  bd70              POP      {r4-r6,pc}
                  |L13.44|
00002c  f7fffffe          BL       DrvRTC_WriteEnable
000030  0220              LSLS     r0,r4,#8              ;115
000032  4904              LDR      r1,|L13.68|
000034  4328              ORRS     r0,r0,r5              ;115
000036  6088              STR      r0,[r1,#8]            ;115
000038  2000              MOVS     r0,#0                 ;117
00003a  bd70              POP      {r4-r6,pc}
;;;119    
                          ENDP

                  |L13.60|
                          DCD      0xffff8007
                  |L13.64|
                          DCD      0xffff9204
                  |L13.68|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_SetTickMode||, CODE, READONLY, ALIGN=2

                  DrvRTC_SetTickMode PROC
;;;762      */
;;;763    int32_t DrvRTC_SetTickMode(uint8_t ucMode)
000000  b510              PUSH     {r4,lr}
;;;764    {
000002  4604              MOV      r4,r0
;;;765        g_u32RTC_Count = 0;
000004  490b              LDR      r1,|L14.52|
000006  2000              MOVS     r0,#0
000008  6108              STR      r0,[r1,#0x10]  ; g_u32RTC_Count
;;;766    	
;;;767        if (DrvRTC_WriteEnable() != 0)   				/* Write PASSWORD to access enable*/
00000a  f7fffffe          BL       DrvRTC_WriteEnable
00000e  2800              CMP      r0,#0
000010  d001              BEQ      |L14.22|
;;;768        {
;;;769        	return E_DRVRTC_ERR_EIO ;
000012  4809              LDR      r0,|L14.56|
;;;770        }
;;;771        
;;;772    	if (ucMode > DRVRTC_TICK_1_128_SEC)             /* Tick mode 0 to 7 */
;;;773        {
;;;774        	return E_DRVRTC_ERR_ENOTTY ;
;;;775        }
;;;776                
;;;777      	RTC->TTR_BITS.TTR = ucMode;            
;;;778    
;;;779    	return E_SUCCESS;
;;;780    
;;;781    }
000014  bd10              POP      {r4,pc}
                  |L14.22|
000016  2c07              CMP      r4,#7                 ;772
000018  d902              BLS      |L14.32|
00001a  4807              LDR      r0,|L14.56|
00001c  1c40              ADDS     r0,r0,#1              ;774
00001e  bd10              POP      {r4,pc}
                  |L14.32|
000020  4806              LDR      r0,|L14.60|
000022  6b01              LDR      r1,[r0,#0x30]         ;777
000024  0762              LSLS     r2,r4,#29             ;777
000026  08c9              LSRS     r1,r1,#3              ;777
000028  00c9              LSLS     r1,r1,#3              ;777
00002a  0f52              LSRS     r2,r2,#29             ;777
00002c  4311              ORRS     r1,r1,r2              ;777
00002e  6301              STR      r1,[r0,#0x30]         ;777
000030  2000              MOVS     r0,#0                 ;779
000032  bd10              POP      {r4,pc}
;;;782    
                          ENDP

                  |L14.52|
                          DCD      ||.data||
                  |L14.56|
                          DCD      0xffff9205
                  |L14.60|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_SpareRegsAccess||, CODE, READONLY, ALIGN=2

                  DrvRTC_SpareRegsAccess PROC
;;;623      */
;;;624    int32_t DrvRTC_SpareRegsAccess (int32_t sparenum, int32_t value, int32_t wrsel)
000000  b5f0              PUSH     {r4-r7,lr}
;;;625    {
000002  4606              MOV      r6,r0
000004  460f              MOV      r7,r1
000006  4614              MOV      r4,r2
;;;626    	uint32_t ret = E_SUCCESS;
000008  2500              MOVS     r5,#0
;;;627    
;;;628    	DrvRTC_WriteEnable();
00000a  f7fffffe          BL       DrvRTC_WriteEnable
;;;629    
;;;630    	if(wrsel==0)
;;;631    		while(RTC->SPRCTL_BITS.SPRRDY!=1) ;
00000e  494e              LDR      r1,|L15.328|
000010  2c00              CMP      r4,#0                 ;630
000012  d102              BNE      |L15.26|
                  |L15.20|
000014  6bc8              LDR      r0,[r1,#0x3c]
000016  0600              LSLS     r0,r0,#24
000018  d5fc              BPL      |L15.20|
                  |L15.26|
;;;632    	
;;;633    	if(sparenum==0)
;;;634    		(wrsel==1) ? (RTC->SPR0=value) : (ret=RTC->SPR0);
00001a  484b              LDR      r0,|L15.328|
00001c  3040              ADDS     r0,r0,#0x40
00001e  2e00              CMP      r6,#0                 ;633
000020  d02a              BEQ      |L15.120|
;;;635    	if(sparenum==1)
000022  2e01              CMP      r6,#1
000024  d072              BEQ      |L15.268|
;;;636    		(wrsel==1) ? (RTC->SPR1=value) : (ret=RTC->SPR1);
;;;637    	if(sparenum==2)
000026  2e02              CMP      r6,#2
000028  d02e              BEQ      |L15.136|
;;;638    		(wrsel==1) ? (RTC->SPR2=value) : (ret=RTC->SPR2);
;;;639    	if(sparenum==3)
00002a  2e03              CMP      r6,#3
00002c  d06f              BEQ      |L15.270|
;;;640    		(wrsel==1) ? (RTC->SPR3=value) : (ret=RTC->SPR3);
;;;641    	if(sparenum==4)
00002e  2e04              CMP      r6,#4
000030  d032              BEQ      |L15.152|
;;;642    		(wrsel==1) ? (RTC->SPR4=value) : (ret=RTC->SPR4);
;;;643    	if(sparenum==5)
000032  2e05              CMP      r6,#5
000034  d036              BEQ      |L15.164|
;;;644    		(wrsel==1) ? (RTC->SPR5=value) : (ret=RTC->SPR5);
;;;645    	if(sparenum==6)
000036  2e06              CMP      r6,#6
000038  d03a              BEQ      |L15.176|
;;;646    		(wrsel==1) ? (RTC->SPR6=value) : (ret=RTC->SPR6);
;;;647    	if(sparenum==7)
00003a  2e07              CMP      r6,#7
00003c  d03e              BEQ      |L15.188|
;;;648    		(wrsel==1) ? (RTC->SPR7=value) : (ret=RTC->SPR7);
;;;649    	if(sparenum==8)
00003e  2e08              CMP      r6,#8
000040  d042              BEQ      |L15.200|
;;;650    		(wrsel==1) ? (RTC->SPR8=value) : (ret=RTC->SPR8);
;;;651    	if(sparenum==9)
000042  2e09              CMP      r6,#9
000044  d046              BEQ      |L15.212|
;;;652    		(wrsel==1) ? (RTC->SPR9=value) : (ret=RTC->SPR9);
;;;653    	if(sparenum==10)
000046  2e0a              CMP      r6,#0xa
000048  d04a              BEQ      |L15.224|
;;;654    		(wrsel==1) ? (RTC->SPR10=value) : (ret=RTC->SPR10);
;;;655    	if(sparenum==11)
00004a  2e0b              CMP      r6,#0xb
00004c  d04e              BEQ      |L15.236|
;;;656    		(wrsel==1) ? (RTC->SPR11=value) : (ret=RTC->SPR11);
;;;657    	if(sparenum==12)
00004e  2e0c              CMP      r6,#0xc
000050  d052              BEQ      |L15.248|
;;;658    		(wrsel==1) ? (RTC->SPR12=value) : (ret=RTC->SPR12);
;;;659    	if(sparenum==13)
000052  2e0d              CMP      r6,#0xd
000054  d056              BEQ      |L15.260|
;;;660    		(wrsel==1) ? (RTC->SPR13=value) : (ret=RTC->SPR13);
;;;661    	if(sparenum==14)
000056  2e0e              CMP      r6,#0xe
000058  d05c              BEQ      |L15.276|
;;;662    		(wrsel==1) ? (RTC->SPR14=value) : (ret=RTC->SPR14);
;;;663    	if(sparenum==15)
00005a  2e0f              CMP      r6,#0xf
00005c  d060              BEQ      |L15.288|
;;;664    		(wrsel==1) ? (RTC->SPR15=value) : (ret=RTC->SPR15);
;;;665    	if(sparenum==16)
;;;666    		(wrsel==1) ? (RTC->SPR16=value) : (ret=RTC->SPR16);
00005e  483a              LDR      r0,|L15.328|
000060  3080              ADDS     r0,r0,#0x80
000062  2e10              CMP      r6,#0x10              ;665
000064  d008              BEQ      |L15.120|
;;;667    	if(sparenum==17)
000066  2e11              CMP      r6,#0x11
000068  d062              BEQ      |L15.304|
;;;668    		(wrsel==1) ? (RTC->SPR17=value) : (ret=RTC->SPR17);
;;;669    	if(sparenum==18)
00006a  2e12              CMP      r6,#0x12
00006c  d00c              BEQ      |L15.136|
;;;670    		(wrsel==1) ? (RTC->SPR18=value) : (ret=RTC->SPR18);
;;;671    	if(sparenum==19)
00006e  2e13              CMP      r6,#0x13
000070  d067              BEQ      |L15.322|
;;;672    		(wrsel==1) ? (RTC->SPR19=value) : (ret=RTC->SPR19);
;;;673    
;;;674    	if(wrsel==1)
000072  2c01              CMP      r4,#1
000074  d060              BEQ      |L15.312|
000076  e062              B        |L15.318|
                  |L15.120|
000078  2c01              CMP      r4,#1                 ;634
00007a  d057              BEQ      |L15.300|
00007c  6805              LDR      r5,[r0,#0]            ;666
00007e  e05e              B        |L15.318|
                  |L15.128|
000080  6047              STR      r7,[r0,#4]            ;636
000082  e059              B        |L15.312|
                  |L15.132|
000084  6845              LDR      r5,[r0,#4]            ;636
000086  e05a              B        |L15.318|
                  |L15.136|
000088  2c01              CMP      r4,#1                 ;638
00008a  d054              BEQ      |L15.310|
00008c  6885              LDR      r5,[r0,#8]            ;670
00008e  e056              B        |L15.318|
                  |L15.144|
000090  60c7              STR      r7,[r0,#0xc]          ;640
000092  e051              B        |L15.312|
                  |L15.148|
000094  68c5              LDR      r5,[r0,#0xc]          ;640
000096  e052              B        |L15.318|
                  |L15.152|
000098  2c01              CMP      r4,#1                 ;642
00009a  d001              BEQ      |L15.160|
00009c  6905              LDR      r5,[r0,#0x10]         ;642
00009e  e04e              B        |L15.318|
                  |L15.160|
0000a0  6107              STR      r7,[r0,#0x10]         ;642
0000a2  e049              B        |L15.312|
                  |L15.164|
0000a4  2c01              CMP      r4,#1                 ;644
0000a6  d001              BEQ      |L15.172|
0000a8  6945              LDR      r5,[r0,#0x14]         ;644
0000aa  e048              B        |L15.318|
                  |L15.172|
0000ac  6147              STR      r7,[r0,#0x14]         ;644
0000ae  e043              B        |L15.312|
                  |L15.176|
0000b0  2c01              CMP      r4,#1                 ;646
0000b2  d001              BEQ      |L15.184|
0000b4  6985              LDR      r5,[r0,#0x18]         ;646
0000b6  e042              B        |L15.318|
                  |L15.184|
0000b8  6187              STR      r7,[r0,#0x18]         ;646
0000ba  e03d              B        |L15.312|
                  |L15.188|
0000bc  2c01              CMP      r4,#1                 ;648
0000be  d001              BEQ      |L15.196|
0000c0  69c5              LDR      r5,[r0,#0x1c]         ;648
0000c2  e03c              B        |L15.318|
                  |L15.196|
0000c4  61c7              STR      r7,[r0,#0x1c]         ;648
0000c6  e037              B        |L15.312|
                  |L15.200|
0000c8  2c01              CMP      r4,#1                 ;650
0000ca  d001              BEQ      |L15.208|
0000cc  6a05              LDR      r5,[r0,#0x20]         ;650
0000ce  e036              B        |L15.318|
                  |L15.208|
0000d0  6207              STR      r7,[r0,#0x20]         ;650
0000d2  e031              B        |L15.312|
                  |L15.212|
0000d4  2c01              CMP      r4,#1                 ;652
0000d6  d001              BEQ      |L15.220|
0000d8  6a45              LDR      r5,[r0,#0x24]         ;652
0000da  e030              B        |L15.318|
                  |L15.220|
0000dc  6247              STR      r7,[r0,#0x24]         ;652
0000de  e02b              B        |L15.312|
                  |L15.224|
0000e0  2c01              CMP      r4,#1                 ;654
0000e2  d001              BEQ      |L15.232|
0000e4  6a85              LDR      r5,[r0,#0x28]         ;654
0000e6  e02a              B        |L15.318|
                  |L15.232|
0000e8  6287              STR      r7,[r0,#0x28]         ;654
0000ea  e025              B        |L15.312|
                  |L15.236|
0000ec  2c01              CMP      r4,#1                 ;656
0000ee  d001              BEQ      |L15.244|
0000f0  6ac5              LDR      r5,[r0,#0x2c]         ;656
0000f2  e024              B        |L15.318|
                  |L15.244|
0000f4  62c7              STR      r7,[r0,#0x2c]         ;656
0000f6  e01f              B        |L15.312|
                  |L15.248|
0000f8  2c01              CMP      r4,#1                 ;658
0000fa  d001              BEQ      |L15.256|
0000fc  6b05              LDR      r5,[r0,#0x30]         ;658
0000fe  e01e              B        |L15.318|
                  |L15.256|
000100  6307              STR      r7,[r0,#0x30]         ;658
000102  e019              B        |L15.312|
                  |L15.260|
000104  2c01              CMP      r4,#1                 ;660
000106  d003              BEQ      |L15.272|
000108  6b45              LDR      r5,[r0,#0x34]         ;660
00010a  e018              B        |L15.318|
                  |L15.268|
00010c  e010              B        |L15.304|
                  |L15.270|
00010e  e018              B        |L15.322|
                  |L15.272|
000110  6347              STR      r7,[r0,#0x34]         ;660
000112  e011              B        |L15.312|
                  |L15.276|
000114  2c01              CMP      r4,#1                 ;662
000116  d001              BEQ      |L15.284|
000118  6b85              LDR      r5,[r0,#0x38]         ;662
00011a  e010              B        |L15.318|
                  |L15.284|
00011c  6387              STR      r7,[r0,#0x38]         ;662
00011e  e00b              B        |L15.312|
                  |L15.288|
000120  2c01              CMP      r4,#1                 ;664
000122  d001              BEQ      |L15.296|
000124  6bc5              LDR      r5,[r0,#0x3c]         ;664
000126  e00a              B        |L15.318|
                  |L15.296|
000128  63c7              STR      r7,[r0,#0x3c]         ;664
00012a  e005              B        |L15.312|
                  |L15.300|
00012c  6007              STR      r7,[r0,#0]            ;666
00012e  e003              B        |L15.312|
                  |L15.304|
000130  2c01              CMP      r4,#1                 ;668
000132  d1a7              BNE      |L15.132|
000134  e7a4              B        |L15.128|
                  |L15.310|
000136  6087              STR      r7,[r0,#8]            ;670
                  |L15.312|
;;;675    		while(RTC->SPRCTL_BITS.SPRRDY!=1) ;
000138  6bc8              LDR      r0,[r1,#0x3c]
00013a  0600              LSLS     r0,r0,#24
00013c  d5fc              BPL      |L15.312|
                  |L15.318|
;;;676    	
;;;677    	return ret;
00013e  4628              MOV      r0,r5
;;;678    
;;;679    }
000140  bdf0              POP      {r4-r7,pc}
                  |L15.322|
000142  2c01              CMP      r4,#1                 ;672
000144  d1a6              BNE      |L15.148|
000146  e7a3              B        |L15.144|
;;;680    
                          ENDP

                  |L15.328|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_Write||, CODE, READONLY, ALIGN=2

                  DrvRTC_Write PROC
;;;462      */
;;;463    int32_t DrvRTC_Write(E_DRVRTC_TIME_SELECT eTime, S_DRVRTC_TIME_DATA_T *sPt)
000000  b5f8              PUSH     {r3-r7,lr}
;;;464    {
000002  4607              MOV      r7,r0
000004  460c              MOV      r4,r1
;;;465        uint32_t u32Reg;
;;;466        /*-----------------------------------------------------------------------------------------------------*/
;;;467        /* Check RTC time data value is reasonable or not.                                                     */
;;;468        /*-----------------------------------------------------------------------------------------------------*/
;;;469    	assert_param(	!( ((sPt->u32Year - DRVRTC_YEAR2000) > 99)|
;;;470    							((sPt->u32cMonth == 0) || (sPt->u32cMonth > 12))|
;;;471    							((sPt->u32cDay   == 0) || (sPt->u32cDay   > 31))));
;;;472    
;;;473    	assert_param( !( (sPt->u32cMonth == 0) || (sPt->u32cMonth > 12) ));
;;;474        
;;;475    	assert_param( !( (sPt->u32cDay == 0) || (sPt->u32cDay > 31) ));
;;;476    
;;;477    	assert_param( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) || (sPt->u8cClockDisplay==DRVRTC_CLOCK_24));
;;;478    
;;;479    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_12) &&
;;;480    							((sPt->u32cHour == 0) || (sPt->u32cHour > 12))));
;;;481    
;;;482    	assert_param(	!( (sPt->u8cClockDisplay==DRVRTC_CLOCK_24) &&
;;;483    							(sPt->u32cHour > 23)));
;;;484    
;;;485    	assert_param( !(sPt->u32cMinute > 59));
;;;486    	assert_param( !(sPt->u32cSecond > 59));
;;;487    	assert_param( !(sPt->u32cDayOfWeek > 6));
;;;488    
;;;489    
;;;490        /*-----------------------------------------------------------------------------------------------------*/
;;;491        /* Important, call DrvRTC_Open() before write data into any register.                                     */
;;;492        /*-----------------------------------------------------------------------------------------------------*/
;;;493        g_u32Reg = DrvRTC_WriteEnable();
000006  f7fffffe          BL       DrvRTC_WriteEnable
00000a  4d5b              LDR      r5,|L16.376|
00000c  61a8              STR      r0,[r5,#0x18]  ; g_u32Reg
;;;494        if (g_u32Reg != 0)
00000e  69a8              LDR      r0,[r5,#0x18]  ; g_u32Reg
000010  2800              CMP      r0,#0
000012  d001              BEQ      |L16.24|
;;;495        {
;;;496            return E_DRVRTC_ERR_FAILED;
000014  4859              LDR      r0,|L16.380|
;;;497        }
;;;498    
;;;499        switch (eTime)
;;;500        {
;;;501    
;;;502            case DRVRTC_CURRENT_TIME:
;;;503                /*---------------------------------------------------------------------------------------------*/
;;;504                /* Second, set RTC time data.                                                                  */
;;;505                /*---------------------------------------------------------------------------------------------*/
;;;506    
;;;507                if (sPt->u8cClockDisplay == DRVRTC_CLOCK_12)
;;;508                {
;;;509                    g_chHourMode = DRVRTC_CLOCK_12;
;;;510    				RTC->TSSR_BITS.HR24 = DRVRTC_CLOCK_12;
;;;511                    RTCDEBUG ("RTC: 12-hour\n");
;;;512                    /*-----------------------------------------------------------------------------------------*/
;;;513                    /* important, range of 12-hour PM mode is 21 upto 32                                       */
;;;514                    /*-----------------------------------------------------------------------------------------*/
;;;515                    if (sPt->u8cAmPm == DRVRTC_PM)
;;;516                        sPt->u32cHour += 20;
;;;517                }
;;;518                else                                                                  /* DRVRTC_CLOCK_24 */
;;;519                {
;;;520                    g_chHourMode = DRVRTC_CLOCK_24;
;;;521        			RTC->TSSR_BITS.HR24 = DRVRTC_CLOCK_24;
;;;522                    RTCDEBUG ("RTC: 24-hour\n");
;;;523                }
;;;524    
;;;525      			RTC->DWR_BITS.DWR = sPt->u32cDayOfWeek;
;;;526    
;;;527    		    
;;;528    			/*---------------------------------------------------------------------------------------------*/
;;;529                /* Second, set RTC time data.                                                                  */
;;;530                /*---------------------------------------------------------------------------------------------*/
;;;531    
;;;532    			u32Reg     = ((sPt->u32Year - DRVRTC_YEAR2000) / 10) << 20;
;;;533    		    u32Reg    |= (((sPt->u32Year - DRVRTC_YEAR2000) % 10) << 16);
;;;534    		    u32Reg    |= ((sPt->u32cMonth  / 10) << 12);
;;;535    		    u32Reg    |= ((sPt->u32cMonth  % 10) << 8);
;;;536    		    u32Reg    |= ((sPt->u32cDay    / 10) << 4);
;;;537    		    u32Reg    |= (sPt->u32cDay     % 10);
;;;538                g_u32Reg = u32Reg;
;;;539    			DrvRTC_WriteEnable();
;;;540              
;;;541    			RTC->CLR = (uint32_t)g_u32Reg;
;;;542    			RTCDEBUG ("RTC: REG_RTC_CLR[0x%08x]\n", RTC->CLR);  
;;;543                
;;;544    		    u32Reg     = ((sPt->u32cHour / 10) << 20);
;;;545    		    u32Reg    |= ((sPt->u32cHour % 10) << 16);
;;;546    		    u32Reg    |= ((sPt->u32cMinute / 10) << 12);
;;;547    		    u32Reg    |= ((sPt->u32cMinute % 10) << 8);
;;;548    		    u32Reg    |= ((sPt->u32cSecond / 10) << 4);
;;;549    		    u32Reg    |= (sPt->u32cSecond % 10);
;;;550    			g_u32Reg = u32Reg;
;;;551    		
;;;552    			DrvRTC_WriteEnable();
;;;553               	RTC->TLR = (uint32_t)g_u32Reg;
;;;554    			RTCDEBUG ("RTC: REG_RTC_TLR[0x%08x]\n", RTC->TLR);   
;;;555    			
;;;556                return E_SUCCESS;
;;;557    
;;;558    
;;;559             case DRVRTC_ALARM_TIME:
;;;560    
;;;561                g_pfnRTCCallBack_Alarm = NULL;                                /* Initial call back function.*/
;;;562                
;;;563    			/*---------------------------------------------------------------------------------------------*/
;;;564                /* Set Calender alarm time data.                                                               */
;;;565                /*---------------------------------------------------------------------------------------------*/
;;;566    		    u32Reg     = ((sPt->u32Year - DRVRTC_YEAR2000) / 10) << 20;
;;;567    		    u32Reg    |= (((sPt->u32Year - DRVRTC_YEAR2000) % 10) << 16);
;;;568    		    u32Reg    |= ((sPt->u32cMonth  / 10) << 12);
;;;569    		    u32Reg    |= ((sPt->u32cMonth  % 10) << 8);
;;;570    		    u32Reg    |= ((sPt->u32cDay    / 10) << 4);
;;;571    		    u32Reg    |= (sPt->u32cDay     % 10);
;;;572                g_u32Reg = u32Reg;
;;;573    			DrvRTC_WriteEnable();
;;;574    			
;;;575    			RTC->CAR = (uint32_t)g_u32Reg;
;;;576    			RTCDEBUG ("RTC: REG_RTC_CAR[0x%08x]\n", RTC->CAR);  
;;;577    			
;;;578    						 
;;;579                if (g_chHourMode == DRVRTC_CLOCK_12)
;;;580                {
;;;581                    if (sPt->u8cAmPm == DRVRTC_PM)       /* important, range of 12-hour PM mode is 21 upto 32 */
;;;582                        sPt->u32cHour += 20;
;;;583                }
;;;584    
;;;585    			/*---------------------------------------------------------------------------------------------*/
;;;586                /* Set Time alarm time data.                                                                   */
;;;587                /*---------------------------------------------------------------------------------------------*/
;;;588    		    u32Reg     = ((sPt->u32cHour / 10) << 20);
;;;589    		    u32Reg    |= ((sPt->u32cHour % 10) << 16);
;;;590    		    u32Reg    |= ((sPt->u32cMinute / 10) << 12);
;;;591    		    u32Reg    |= ((sPt->u32cMinute % 10) << 8);
;;;592    		    u32Reg    |= ((sPt->u32cSecond / 10) << 4);
;;;593    		    u32Reg    |= (sPt->u32cSecond % 10);
;;;594    
;;;595    			g_u32Reg = u32Reg;
;;;596                DrvRTC_WriteEnable();
;;;597               	RTC->TAR = (uint32_t)g_u32Reg;
;;;598    			RTCDEBUG ("RTC: REG_RTC_TAR[0x%08x]\n", RTC->TAR);   
;;;599    
;;;600    			/*---------------------------------------------------------------------------------------------*/
;;;601                /* Finally, enable alarm interrupt.                                                            */
;;;602                /*---------------------------------------------------------------------------------------------*/
;;;603    			DrvRTC_EnableInt(DRVRTC_ALARM_INT,NULL);
;;;604                
;;;605    			RTC->TTR_BITS.TWKE = sPt->u8IsEnableWakeUp;
;;;606    			return E_SUCCESS;
;;;607    
;;;608    
;;;609    	        default:
;;;610    	        {
;;;611    	            return E_DRVRTC_ERR_ENOTTY;
;;;612    	        }
;;;613        }
;;;614    
;;;615    }
000016  bdf8              POP      {r3-r7,pc}
                  |L16.24|
000018  207d              MOVS     r0,#0x7d              ;532
00001a  2100              MOVS     r1,#0                 ;464
00001c  0100              LSLS     r0,r0,#4              ;532
00001e  4e58              LDR      r6,|L16.384|
000020  2f00              CMP      r7,#0                 ;499
000022  d004              BEQ      |L16.46|
000024  2f01              CMP      r7,#1                 ;499
000026  d056              BEQ      |L16.214|
000028  4854              LDR      r0,|L16.380|
00002a  1e80              SUBS     r0,r0,#2              ;611
00002c  bdf8              POP      {r3-r7,pc}
                  |L16.46|
00002e  7822              LDRB     r2,[r4,#0]            ;507
000030  2a00              CMP      r2,#0                 ;507
000032  d044              BEQ      |L16.190|
000034  2101              MOVS     r1,#1                 ;520
000036  7029              STRB     r1,[r5,#0]            ;520
000038  6972              LDR      r2,[r6,#0x14]         ;521
00003a  430a              ORRS     r2,r2,r1              ;521
00003c  6172              STR      r2,[r6,#0x14]         ;521
                  |L16.62|
00003e  69b1              LDR      r1,[r6,#0x18]         ;525
000040  6922              LDR      r2,[r4,#0x10]         ;525
000042  08c9              LSRS     r1,r1,#3              ;525
000044  00c9              LSLS     r1,r1,#3              ;525
000046  0752              LSLS     r2,r2,#29             ;525
000048  0f52              LSRS     r2,r2,#29             ;525
00004a  4311              ORRS     r1,r1,r2              ;525
00004c  61b1              STR      r1,[r6,#0x18]         ;525
00004e  69e1              LDR      r1,[r4,#0x1c]         ;532
000050  1a08              SUBS     r0,r1,r0              ;532
000052  210a              MOVS     r1,#0xa               ;532
000054  f7fffffe          BL       __aeabi_uidivmod
000058  040f              LSLS     r7,r1,#16             ;533
00005a  0500              LSLS     r0,r0,#20             ;532
00005c  4307              ORRS     r7,r7,r0              ;533
00005e  210a              MOVS     r1,#0xa               ;534
000060  69a0              LDR      r0,[r4,#0x18]         ;534
000062  f7fffffe          BL       __aeabi_uidivmod
000066  0300              LSLS     r0,r0,#12             ;534
000068  4338              ORRS     r0,r0,r7              ;534
00006a  020f              LSLS     r7,r1,#8              ;535
00006c  4307              ORRS     r7,r7,r0              ;535
00006e  210a              MOVS     r1,#0xa               ;536
000070  6960              LDR      r0,[r4,#0x14]         ;536
000072  f7fffffe          BL       __aeabi_uidivmod
000076  0100              LSLS     r0,r0,#4              ;536
000078  4338              ORRS     r0,r0,r7              ;536
00007a  4301              ORRS     r1,r1,r0              ;537
00007c  61a9              STR      r1,[r5,#0x18]         ;538  ; g_u32Reg
00007e  f7fffffe          BL       DrvRTC_WriteEnable
000082  69a8              LDR      r0,[r5,#0x18]         ;541  ; g_u32Reg
000084  6130              STR      r0,[r6,#0x10]         ;541
000086  210a              MOVS     r1,#0xa               ;544
000088  68e0              LDR      r0,[r4,#0xc]          ;544
00008a  f7fffffe          BL       __aeabi_uidivmod
00008e  040f              LSLS     r7,r1,#16             ;545
000090  0500              LSLS     r0,r0,#20             ;544
000092  4307              ORRS     r7,r7,r0              ;545
000094  210a              MOVS     r1,#0xa               ;546
000096  68a0              LDR      r0,[r4,#8]            ;546
000098  f7fffffe          BL       __aeabi_uidivmod
00009c  0300              LSLS     r0,r0,#12             ;546
00009e  4338              ORRS     r0,r0,r7              ;546
0000a0  020f              LSLS     r7,r1,#8              ;547
0000a2  4307              ORRS     r7,r7,r0              ;547
0000a4  210a              MOVS     r1,#0xa               ;548
0000a6  6860              LDR      r0,[r4,#4]            ;548
0000a8  f7fffffe          BL       __aeabi_uidivmod
0000ac  0100              LSLS     r0,r0,#4              ;548
0000ae  4338              ORRS     r0,r0,r7              ;548
0000b0  4301              ORRS     r1,r1,r0              ;549
0000b2  61a9              STR      r1,[r5,#0x18]         ;550  ; g_u32Reg
0000b4  f7fffffe          BL       DrvRTC_WriteEnable
0000b8  69a8              LDR      r0,[r5,#0x18]         ;553  ; g_u32Reg
0000ba  60f0              STR      r0,[r6,#0xc]          ;553
0000bc  e059              B        |L16.370|
                  |L16.190|
0000be  7029              STRB     r1,[r5,#0]            ;509
0000c0  6971              LDR      r1,[r6,#0x14]         ;510
0000c2  0849              LSRS     r1,r1,#1              ;510
0000c4  0049              LSLS     r1,r1,#1              ;510
0000c6  6171              STR      r1,[r6,#0x14]         ;510
0000c8  7861              LDRB     r1,[r4,#1]            ;515
0000ca  2902              CMP      r1,#2                 ;515
0000cc  d1b7              BNE      |L16.62|
0000ce  68e1              LDR      r1,[r4,#0xc]          ;516
0000d0  3114              ADDS     r1,r1,#0x14           ;516
0000d2  60e1              STR      r1,[r4,#0xc]          ;516
0000d4  e7b3              B        |L16.62|
                  |L16.214|
0000d6  60a9              STR      r1,[r5,#8]            ;566  ; g_pfnRTCCallBack_Alarm
0000d8  69e1              LDR      r1,[r4,#0x1c]         ;566
0000da  1a08              SUBS     r0,r1,r0              ;566
0000dc  210a              MOVS     r1,#0xa               ;566
0000de  f7fffffe          BL       __aeabi_uidivmod
0000e2  040f              LSLS     r7,r1,#16             ;567
0000e4  0500              LSLS     r0,r0,#20             ;566
0000e6  4307              ORRS     r7,r7,r0              ;567
0000e8  210a              MOVS     r1,#0xa               ;568
0000ea  69a0              LDR      r0,[r4,#0x18]         ;568
0000ec  f7fffffe          BL       __aeabi_uidivmod
0000f0  0300              LSLS     r0,r0,#12             ;568
0000f2  4338              ORRS     r0,r0,r7              ;568
0000f4  020f              LSLS     r7,r1,#8              ;569
0000f6  4307              ORRS     r7,r7,r0              ;569
0000f8  210a              MOVS     r1,#0xa               ;570
0000fa  6960              LDR      r0,[r4,#0x14]         ;570
0000fc  f7fffffe          BL       __aeabi_uidivmod
000100  0100              LSLS     r0,r0,#4              ;570
000102  4338              ORRS     r0,r0,r7              ;570
000104  4301              ORRS     r1,r1,r0              ;571
000106  61a9              STR      r1,[r5,#0x18]         ;572  ; g_u32Reg
000108  f7fffffe          BL       DrvRTC_WriteEnable
00010c  69a8              LDR      r0,[r5,#0x18]         ;575  ; g_u32Reg
00010e  6230              STR      r0,[r6,#0x20]         ;575
000110  7828              LDRB     r0,[r5,#0]            ;579  ; g_chHourMode
000112  2800              CMP      r0,#0                 ;579
000114  d105              BNE      |L16.290|
000116  7860              LDRB     r0,[r4,#1]            ;581
000118  2802              CMP      r0,#2                 ;581
00011a  d102              BNE      |L16.290|
00011c  68e0              LDR      r0,[r4,#0xc]          ;582
00011e  3014              ADDS     r0,r0,#0x14           ;582
000120  60e0              STR      r0,[r4,#0xc]          ;582
                  |L16.290|
000122  210a              MOVS     r1,#0xa               ;588
000124  68e0              LDR      r0,[r4,#0xc]          ;588
000126  f7fffffe          BL       __aeabi_uidivmod
00012a  040f              LSLS     r7,r1,#16             ;589
00012c  0500              LSLS     r0,r0,#20             ;588
00012e  4307              ORRS     r7,r7,r0              ;589
000130  210a              MOVS     r1,#0xa               ;590
000132  68a0              LDR      r0,[r4,#8]            ;590
000134  f7fffffe          BL       __aeabi_uidivmod
000138  0300              LSLS     r0,r0,#12             ;590
00013a  4338              ORRS     r0,r0,r7              ;590
00013c  020f              LSLS     r7,r1,#8              ;591
00013e  4307              ORRS     r7,r7,r0              ;591
000140  210a              MOVS     r1,#0xa               ;592
000142  6860              LDR      r0,[r4,#4]            ;592
000144  f7fffffe          BL       __aeabi_uidivmod
000148  0100              LSLS     r0,r0,#4              ;592
00014a  4338              ORRS     r0,r0,r7              ;592
00014c  4301              ORRS     r1,r1,r0              ;593
00014e  61a9              STR      r1,[r5,#0x18]         ;595  ; g_u32Reg
000150  f7fffffe          BL       DrvRTC_WriteEnable
000154  69a8              LDR      r0,[r5,#0x18]         ;597  ; g_u32Reg
000156  61f0              STR      r0,[r6,#0x1c]         ;597
000158  2100              MOVS     r1,#0                 ;603
00015a  2001              MOVS     r0,#1                 ;603
00015c  f7fffffe          BL       DrvRTC_EnableInt
000160  6b30              LDR      r0,[r6,#0x30]         ;605
000162  2108              MOVS     r1,#8                 ;605
000164  4388              BICS     r0,r0,r1              ;605
000166  3420              ADDS     r4,r4,#0x20           ;605
000168  7821              LDRB     r1,[r4,#0]            ;605
00016a  07c9              LSLS     r1,r1,#31             ;605
00016c  0f09              LSRS     r1,r1,#28             ;605
00016e  4308              ORRS     r0,r0,r1              ;605
000170  6330              STR      r0,[r6,#0x30]         ;605
                  |L16.370|
000172  2000              MOVS     r0,#0                 ;606
000174  bdf8              POP      {r3-r7,pc}
;;;616    
                          ENDP

000176  0000              DCW      0x0000
                  |L16.376|
                          DCD      ||.data||
                  |L16.380|
                          DCD      0xffff9208
                  |L16.384|
                          DCD      0x40008000

                          AREA ||i.DrvRTC_WriteEnable||, CODE, READONLY, ALIGN=2

                  DrvRTC_WriteEnable PROC
;;;126      */
;;;127    int32_t DrvRTC_WriteEnable (void)
000000  b510              PUSH     {r4,lr}
;;;128    {
;;;129        int32_t i32i = 0;
;;;130    
;;;131    	int i32retry = 100;
;;;132        
;;;133    	/*-------------------------------------------------------------------------------------------------*/
;;;134        /* After 200ms, Access enable wiil auto-clear. As soon as possible to do your setting              */
;;;135        /*-------------------------------------------------------------------------------------------------*/
;;;136    	RETRY:
;;;137    
;;;138    	i32i = 0;
;;;139    	
;;;140    	RTC->AER_BITS.AER = DRVRTC_WRITE_KEY;
000002  4a0e              LDR      r2,|L17.60|
000004  4b0e              LDR      r3,|L17.64|
000006  2164              MOVS     r1,#0x64              ;131
                  |L17.8|
000008  6854              LDR      r4,[r2,#4]
00000a  2000              MOVS     r0,#0                 ;138
00000c  0c24              LSRS     r4,r4,#16
00000e  0424              LSLS     r4,r4,#16
000010  18e4              ADDS     r4,r4,r3
000012  6054              STR      r4,[r2,#4]
                  |L17.20|
;;;141    	
;;;142        for (i32i = 0 ; i32i < DRVRTC_WAIT_COUNT ; i32i++)
;;;143    	{
;;;144            /*-------------------------------------------------------------------------------------------------*/
;;;145            /* check RTC_AER[16] to find out RTC write enable                                                  */
;;;146            /*-------------------------------------------------------------------------------------------------*/
;;;147     		RTC->AER_BITS.AER = DRVRTC_WRITE_KEY;
000014  6854              LDR      r4,[r2,#4]
000016  0c24              LSRS     r4,r4,#16
000018  0424              LSLS     r4,r4,#16
00001a  18e4              ADDS     r4,r4,r3
00001c  6054              STR      r4,[r2,#4]
;;;148    		
;;;149    		if (RTC->AER_BITS.ENF ==1)	
00001e  6854              LDR      r4,[r2,#4]
000020  03e4              LSLS     r4,r4,#15
000022  d403              BMI      |L17.44|
000024  1c40              ADDS     r0,r0,#1              ;142
000026  1c44              ADDS     r4,r0,#1              ;142
000028  d1f4              BNE      |L17.20|
00002a  e003              B        |L17.52|
                  |L17.44|
;;;150    		    break;
;;;151    	}
;;;152    
;;;153    	
;;;154    	if (i32i == DRVRTC_WAIT_COUNT)
00002c  1c40              ADDS     r0,r0,#1
00002e  d001              BEQ      |L17.52|
;;;155        {
;;;156            RTCDEBUG ("\nRTC: DrvRTC_WriteEnable, set write enable FAILED!\n");
;;;157    
;;;158    		i32retry--;
;;;159    
;;;160            if(!i32retry)
;;;161    	   		return E_DRVRTC_ERR_FAILED;
;;;162    						
;;;163    		goto RETRY;
;;;164        }
;;;165    
;;;166        
;;;167    	return E_SUCCESS;
000030  2000              MOVS     r0,#0
;;;168    }
000032  bd10              POP      {r4,pc}
                  |L17.52|
000034  1e49              SUBS     r1,r1,#1              ;158
000036  d1e7              BNE      |L17.8|
000038  4802              LDR      r0,|L17.68|
00003a  bd10              POP      {r4,pc}
;;;169    
                          ENDP

                  |L17.60|
                          DCD      0x40008000
                  |L17.64|
                          DCD      0x0000a965
                  |L17.68|
                          DCD      0xffff9208

                          AREA ||i.RTC_IRQHandler||, CODE, READONLY, ALIGN=2

                  RTC_IRQHandler PROC
;;;53       */
;;;54     void RTC_IRQHandler(void)
000000  b570              PUSH     {r4-r6,lr}
;;;55     { 
;;;56        
;;;57     	if ( (RTC->RIER_BITS.TIER) && (RTC->RIIR_BITS.TIS==0x1) )		/* tick interrupt occurred */
000002  4c15              LDR      r4,|L18.88|
000004  6aa0              LDR      r0,[r4,#0x28]
;;;58     	{
;;;59      		  RTC->RIIR = 0x2;
;;;60     		  
;;;61     		  g_u32RTC_Count++;                                            /* maintain RTC tick count */
000006  4d15              LDR      r5,|L18.92|
000008  0780              LSLS     r0,r0,#30             ;57
00000a  d50b              BPL      |L18.36|
00000c  6ae0              LDR      r0,[r4,#0x2c]         ;57
00000e  0780              LSLS     r0,r0,#30             ;57
000010  d508              BPL      |L18.36|
000012  2002              MOVS     r0,#2                 ;59
000014  62e0              STR      r0,[r4,#0x2c]         ;59
000016  6928              LDR      r0,[r5,#0x10]  ; g_u32RTC_Count
000018  1c40              ADDS     r0,r0,#1
00001a  6128              STR      r0,[r5,#0x10]  ; g_u32RTC_Count
;;;62     
;;;63               if (g_pfnRTCCallBack_Tick != NULL)                           /* execute tick callback function */
00001c  6868              LDR      r0,[r5,#4]  ; g_pfnRTCCallBack_Tick
00001e  2800              CMP      r0,#0
000020  d000              BEQ      |L18.36|
;;;64               {
;;;65                   g_pfnRTCCallBack_Tick();
000022  4780              BLX      r0
                  |L18.36|
;;;66               }
;;;67     
;;;68         }
;;;69     
;;;70      	if ( (RTC->RIER_BITS.AIER) && (RTC->RIIR_BITS.AIS==0x1) )		/* alarm interrupt occurred */
000024  6aa0              LDR      r0,[r4,#0x28]
000026  07c0              LSLS     r0,r0,#31
000028  d008              BEQ      |L18.60|
00002a  6ae0              LDR      r0,[r4,#0x2c]
00002c  07c0              LSLS     r0,r0,#31
00002e  d005              BEQ      |L18.60|
;;;71         {          
;;;72     		  RTC->RIIR = 0x1;
000030  2001              MOVS     r0,#1
000032  62e0              STR      r0,[r4,#0x2c]
;;;73     		  
;;;74     		  if (g_pfnRTCCallBack_Alarm != NULL) 	                       /* execute alarm callback function */
000034  68a8              LDR      r0,[r5,#8]  ; g_pfnRTCCallBack_Alarm
000036  2800              CMP      r0,#0
000038  d000              BEQ      |L18.60|
;;;75               {
;;;76                   g_pfnRTCCallBack_Alarm();
00003a  4780              BLX      r0
                  |L18.60|
;;;77               }
;;;78         }
;;;79     
;;;80     	if ( (RTC->RIER_BITS.SNOOPIER) && (RTC->RIIR_BITS.SNOOPIS==0x1) )	/* snooper interrupt occurred */
00003c  6aa0              LDR      r0,[r4,#0x28]
00003e  0740              LSLS     r0,r0,#29
000040  d508              BPL      |L18.84|
000042  6ae0              LDR      r0,[r4,#0x2c]
000044  0740              LSLS     r0,r0,#29
000046  d505              BPL      |L18.84|
;;;81         {          
;;;82     		  RTC->RIIR = 0x4;
000048  2004              MOVS     r0,#4
00004a  62e0              STR      r0,[r4,#0x2c]
;;;83     		  
;;;84     		  if (g_pfnRTCCallBack_Snooper != NULL) 	                       /* execute alarm callback function */
00004c  68e8              LDR      r0,[r5,#0xc]  ; g_pfnRTCCallBack_Snooper
00004e  2800              CMP      r0,#0
000050  d000              BEQ      |L18.84|
;;;85               {
;;;86                   g_pfnRTCCallBack_Snooper();
000052  4780              BLX      r0
                  |L18.84|
;;;87               }
;;;88         }
;;;89     }
000054  bd70              POP      {r4-r6,pc}
;;;90     
                          ENDP

000056  0000              DCW      0x0000
                  |L18.88|
                          DCD      0x40008000
                  |L18.92|
                          DCD      ||.data||

                          AREA ||.data||, DATA, ALIGN=2

                  g_chHourMode
000000  00                DCB      0x00
                  g_bIsEnableAlarmInt
000001  00                DCB      0x00
                  g_bIsEnableSnooperInt
000002  0000              DCB      0x00,0x00
                  g_pfnRTCCallBack_Tick
                          DCD      0x00000000
                  g_pfnRTCCallBack_Alarm
                          DCD      0x00000000
                  g_pfnRTCCallBack_Snooper
                          DCD      0x00000000
                  g_u32RTC_Count
                          DCD      0x00000000
                  g_bIsEnableTickInt
                          DCD      0x00000000
                  g_u32Reg
                          DCD      0x00000000
                  g_u32hiYear
                          DCD      0x00000000
                  g_u32loYear
                          DCD      0x00000000
                  g_u32hiMonth
                          DCD      0x00000000
                  g_u32loMonth
                          DCD      0x00000000
                  g_u32hiDay
                          DCD      0x00000000
                  g_u32loDay
                          DCD      0x00000000
                  g_u32hiHour
                          DCD      0x00000000
                  g_u32loHour
                          DCD      0x00000000
                  g_u32hiMin
                          DCD      0x00000000
                  g_u32loMin
                          DCD      0x00000000
                  g_u32hiSec
                          DCD      0x00000000
                  g_u32loSec
                          DCD      0x00000000
