; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\drvspi.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvspi.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvspi.crf ..\bsp\Driver\DrvSPI.c]
                          THUMB

                          AREA ||i.DrvSPI_3WireAbort||, CODE, READONLY, ALIGN=2

                  DrvSPI_3WireAbort PROC
;;;788      */
;;;789    void DrvSPI_3WireAbort(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;790    {
;;;791        SPI_PORT[eSpiPort]->SSR_BITS.SLV_ABORT = 1;
000002  4804              LDR      r0,|L1.20|
000004  5840              LDR      r0,[r0,r1]
000006  68c1              LDR      r1,[r0,#0xc]
000008  22ff              MOVS     r2,#0xff
00000a  3201              ADDS     r2,#1
00000c  4311              ORRS     r1,r1,r2
00000e  60c1              STR      r1,[r0,#0xc]
;;;792    }
000010  4770              BX       lr
;;;793    
                          ENDP

000012  0000              DCW      0x0000
                  |L1.20|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_ClearRxFIFO||, CODE, READONLY, ALIGN=2

                  DrvSPI_ClearRxFIFO PROC
;;;933      */
;;;934    void DrvSPI_ClearRxFIFO(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;935    {
;;;936    	SPI_PORT[eSpiPort]->FF_CTL_BITS.RX_CLR = 1;
000002  4803              LDR      r0,|L2.16|
000004  5840              LDR      r0,[r0,r1]
000006  6bc1              LDR      r1,[r0,#0x3c]
000008  2201              MOVS     r2,#1
00000a  4311              ORRS     r1,r1,r2
00000c  63c1              STR      r1,[r0,#0x3c]
;;;937    }
00000e  4770              BX       lr
;;;938    
                          ENDP

                  |L2.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_ClearTxFIFO||, CODE, READONLY, ALIGN=2

                  DrvSPI_ClearTxFIFO PROC
;;;923      */
;;;924    void DrvSPI_ClearTxFIFO(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;925    {
;;;926    	SPI_PORT[eSpiPort]->FF_CTL_BITS.TX_CLR = 1;
000002  4803              LDR      r0,|L3.16|
000004  5840              LDR      r0,[r0,r1]
000006  6bc1              LDR      r1,[r0,#0x3c]
000008  2202              MOVS     r2,#2
00000a  4311              ORRS     r1,r1,r2
00000c  63c1              STR      r1,[r0,#0x3c]
;;;927    }
00000e  4770              BX       lr
;;;928    
                          ENDP

                  |L3.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Close||, CODE, READONLY, ALIGN=2

                  DrvSPI_Close PROC
;;;257      
;;;258    void DrvSPI_Close(E_DRVSPI_PORT eSpiPort)
000000  b570              PUSH     {r4-r6,lr}
;;;259    {
;;;260    	int32_t i32TimeOut;
;;;261    	
;;;262    	g_sSpiHandler[eSpiPort].bBusy = FALSE;
000002  2114              MOVS     r1,#0x14
000004  4b1d              LDR      r3,|L4.124|
000006  2200              MOVS     r2,#0
000008  4341              MULS     r1,r0,r1
00000a  545a              STRB     r2,[r3,r1]
;;;263    	g_sSpiHandler[eSpiPort].pfncallback = NULL;
00000c  18c9              ADDS     r1,r1,r3
;;;264    	g_sSpiHandler[eSpiPort].u32userData = 0;
00000e  604a              STR      r2,[r1,#4]
;;;265    	g_sSpiHandler[eSpiPort].pfn3WireStartCallBack = NULL;
000010  608a              STR      r2,[r1,#8]
;;;266        g_sSpiHandler[eSpiPort].u32ThreeWireStartUserData = 0;
000012  60ca              STR      r2,[r1,#0xc]
;;;267        
;;;268    	/* Wait SPIMS Busy */
;;;269    	i32TimeOut = 0x10000;
000014  610a              STR      r2,[r1,#0x10]
000016  2101              MOVS     r1,#1
000018  0409              LSLS     r1,r1,#16
;;;270    	while(SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY == 1)
00001a  0082              LSLS     r2,r0,#2
00001c  333c              ADDS     r3,r3,#0x3c
00001e  589a              LDR      r2,[r3,r2]
;;;271    	{
;;;272    		if(i32TimeOut-- <= 0)
;;;273    			break;
000020  e003              B        |L4.42|
                  |L4.34|
000022  460b              MOV      r3,r1                 ;272
000024  1e49              SUBS     r1,r1,#1              ;272
000026  2b00              CMP      r3,#0                 ;272
000028  dd02              BLE      |L4.48|
                  |L4.42|
00002a  6813              LDR      r3,[r2,#0]            ;270
00002c  07db              LSLS     r3,r3,#31             ;270
00002e  d1f8              BNE      |L4.34|
                  |L4.48|
;;;274    	}
;;;275       
;;;276       if(eSpiPort == eDRVSPI_PORT0)
;;;277    	{
;;;278    		NVIC_DisableIRQ(SPI0_IRQn);
;;;279    		GCR->IPRST_CTL2_BITS.SPI0_RST	=1;
000030  2405              MOVS     r4,#5
000032  0724              LSLS     r4,r4,#28
;;;280    		GCR->IPRST_CTL2_BITS.SPI0_RST	=0;
;;;281    		CLK->APBCLK_BITS.SPI0_EN        =0;
000034  4d12              LDR      r5,|L4.128|
000036  2800              CMP      r0,#0                 ;276
000038  d009              BEQ      |L4.78|
;;;282    	}
;;;283    	else if(eSpiPort == eDRVSPI_PORT1)
00003a  2801              CMP      r0,#1
00003c  d00e              BEQ      |L4.92|
;;;284    	{
;;;285    		NVIC_DisableIRQ(SPI1_IRQn);
;;;286    		GCR->IPRST_CTL2_BITS.SPI1_RST	=1;
;;;287    		GCR->IPRST_CTL2_BITS.SPI1_RST	=0;
;;;288    		CLK->APBCLK_BITS.SPI1_EN        =0;
;;;289    	}
;;;290    	else if(eSpiPort == eDRVSPI_PORT2)
00003e  2802              CMP      r0,#2
000040  d11a              BNE      |L4.120|
;;;291    	{
;;;292    		NVIC_DisableIRQ(SPI2_IRQn);
000042  2010              MOVS     r0,#0x10
000044  f7fffffe          BL       NVIC_DisableIRQ
;;;293    		GCR->IPRST_CTL2_BITS.SPI2_RST	=1;
000048  68e1              LDR      r1,[r4,#0xc]
00004a  0168              LSLS     r0,r5,#5
;;;294    		GCR->IPRST_CTL2_BITS.SPI2_RST	=0;
;;;295    		CLK->APBCLK_BITS.SPI2_EN        =0;
00004c  e00c              B        |L4.104|
                  |L4.78|
00004e  200e              MOVS     r0,#0xe               ;278
000050  f7fffffe          BL       NVIC_DisableIRQ
000054  68e1              LDR      r1,[r4,#0xc]          ;279
000056  2001              MOVS     r0,#1                 ;279
000058  0300              LSLS     r0,r0,#12             ;279
00005a  e005              B        |L4.104|
                  |L4.92|
00005c  200f              MOVS     r0,#0xf               ;285
00005e  f7fffffe          BL       NVIC_DisableIRQ
000062  68e1              LDR      r1,[r4,#0xc]          ;286
000064  2001              MOVS     r0,#1                 ;286
000066  0340              LSLS     r0,r0,#13             ;286
                  |L4.104|
000068  4301              ORRS     r1,r1,r0              ;279
00006a  60e1              STR      r1,[r4,#0xc]          ;279
00006c  68e1              LDR      r1,[r4,#0xc]          ;280
00006e  4381              BICS     r1,r1,r0              ;280
000070  60e1              STR      r1,[r4,#0xc]          ;280
000072  68a9              LDR      r1,[r5,#8]            ;281
000074  4381              BICS     r1,r1,r0              ;281
000076  60a9              STR      r1,[r5,#8]            ;281
                  |L4.120|
;;;296    	}      
;;;297    }
000078  bd70              POP      {r4-r6,pc}
;;;298    
                          ENDP

00007a  0000              DCW      0x0000
                  |L4.124|
                          DCD      ||.bss||
                  |L4.128|
                          DCD      0x50000200

                          AREA ||i.DrvSPI_Clr3WireStartIntFlag||, CODE, READONLY, ALIGN=2

                  DrvSPI_Clr3WireStartIntFlag PROC
;;;842      */
;;;843    void DrvSPI_Clr3WireStartIntFlag(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;844    {
;;;845        SPI_PORT[eSpiPort]->STATUS_BITS.SLV_START_INTSTS = 1;
000002  4803              LDR      r0,|L5.16|
000004  5840              LDR      r0,[r0,r1]
000006  6841              LDR      r1,[r0,#4]
000008  2240              MOVS     r2,#0x40
00000a  4311              ORRS     r1,r1,r2
00000c  6041              STR      r1,[r0,#4]
;;;846    }
00000e  4770              BX       lr
;;;847    
                          ENDP

                  |L5.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_ClrGo||, CODE, READONLY, ALIGN=2

                  DrvSPI_ClrGo PROC
;;;741      */
;;;742    void DrvSPI_ClrGo(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;743    {
;;;744    	SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY = 0;
000002  4803              LDR      r0,|L6.16|
000004  5840              LDR      r0,[r0,r1]
000006  6801              LDR      r1,[r0,#0]
000008  0849              LSRS     r1,r1,#1
00000a  0049              LSLS     r1,r1,#1
00000c  6001              STR      r1,[r0,#0]
;;;745    }
00000e  4770              BX       lr
;;;746    
                          ENDP

                  |L6.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_ClrIntFlag||, CODE, READONLY, ALIGN=2

                  DrvSPI_ClrIntFlag PROC
;;;649      */
;;;650    void DrvSPI_ClrIntFlag(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;651    {
;;;652    	SPI_PORT[eSpiPort]->STATUS_BITS.INTSTS = 1;
000002  4803              LDR      r0,|L7.16|
000004  5840              LDR      r0,[r0,r1]
000006  6841              LDR      r1,[r0,#4]
000008  2280              MOVS     r2,#0x80
00000a  4311              ORRS     r1,r1,r2
00000c  6041              STR      r1,[r0,#4]
;;;653    }
00000e  4770              BX       lr
;;;654    
                          ENDP

                  |L7.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_ClrSS||, CODE, READONLY, ALIGN=2

                  DrvSPI_ClrSS PROC
;;;478      */
;;;479    void DrvSPI_ClrSS(E_DRVSPI_PORT eSpiPort, E_DRVSPI_SLAVE_SEL eSlaveSel)
000000  0082              LSLS     r2,r0,#2
;;;480    {
;;;481    	uint32_t u32Reg;
;;;482    	
;;;483    	u32Reg = SPI_PORT[eSpiPort]->SSR_BITS.SSR;
000002  4806              LDR      r0,|L8.28|
000004  5880              LDR      r0,[r0,r2]
000006  68c2              LDR      r2,[r0,#0xc]
000008  0792              LSLS     r2,r2,#30
00000a  0f92              LSRS     r2,r2,#30
;;;484    	u32Reg = u32Reg & (~eSlaveSel);
00000c  438a              BICS     r2,r2,r1
;;;485    	SPI_PORT[eSpiPort]->SSR_BITS.SSR = u32Reg;
00000e  68c1              LDR      r1,[r0,#0xc]
000010  0889              LSRS     r1,r1,#2
000012  0089              LSLS     r1,r1,#2
000014  4311              ORRS     r1,r1,r2
000016  60c1              STR      r1,[r0,#0xc]
;;;486    }
000018  4770              BX       lr
;;;487    
                          ENDP

00001a  0000              DCW      0x0000
                  |L8.28|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Disable3Wire||, CODE, READONLY, ALIGN=2

                  DrvSPI_Disable3Wire PROC
;;;776      */
;;;777    void DrvSPI_Disable3Wire(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;778    {
;;;779        SPI_PORT[eSpiPort]->SSR_BITS.NOSLVSEL = 0;
000002  4803              LDR      r0,|L9.16|
000004  5840              LDR      r0,[r0,r1]
000006  68c1              LDR      r1,[r0,#0xc]
000008  2220              MOVS     r2,#0x20
00000a  4391              BICS     r1,r1,r2
00000c  60c1              STR      r1,[r0,#0xc]
;;;780    }
00000e  4770              BX       lr
;;;781    
                          ENDP

                  |L9.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Disable3WireStartInt||, CODE, READONLY, ALIGN=2

                  DrvSPI_Disable3WireStartInt PROC
;;;817      */
;;;818    void DrvSPI_Disable3WireStartInt(E_DRVSPI_PORT eSpiPort)
000000  2114              MOVS     r1,#0x14
;;;819    {
;;;820        g_sSpiHandler[eSpiPort].pfn3WireStartCallBack = NULL;
000002  4b0a              LDR      r3,|L10.44|
000004  b510              PUSH     {r4,lr}               ;819
000006  4341              MULS     r1,r0,r1
000008  2200              MOVS     r2,#0
00000a  18c9              ADDS     r1,r1,r3
;;;821        g_sSpiHandler[eSpiPort].u32ThreeWireStartUserData = 0;
00000c  60ca              STR      r2,[r1,#0xc]
;;;822        
;;;823        SPI_PORT[eSpiPort]->SSR_BITS.SSTA_INTEN = 0;
00000e  610a              STR      r2,[r1,#0x10]
000010  0082              LSLS     r2,r0,#2
000012  4619              MOV      r1,r3
000014  313c              ADDS     r1,r1,#0x3c
000016  5889              LDR      r1,[r1,r2]
000018  68ca              LDR      r2,[r1,#0xc]
00001a  2301              MOVS     r3,#1
00001c  025b              LSLS     r3,r3,#9
00001e  439a              BICS     r2,r2,r3
000020  60ca              STR      r2,[r1,#0xc]
;;;824        NVIC_DisableIRQ((IRQn_Type)(SPI0_IRQn+(uint32_t)eSpiPort));   
000022  300e              ADDS     r0,r0,#0xe
000024  b240              SXTB     r0,r0
000026  f7fffffe          BL       NVIC_DisableIRQ
;;;825    }
00002a  bd10              POP      {r4,pc}
;;;826    
                          ENDP

                  |L10.44|
                          DCD      ||.bss||

                          AREA ||i.DrvSPI_DisableAutoSS||, CODE, READONLY, ALIGN=2

                  DrvSPI_DisableAutoSS PROC
;;;451      */
;;;452    void DrvSPI_DisableAutoSS(E_DRVSPI_PORT eSpiPort)
000000  b510              PUSH     {r4,lr}
;;;453    {
;;;454        SPI_PORT[eSpiPort]->SSR_BITS.AUTOSS = 0;
000002  4b06              LDR      r3,|L11.28|
000004  0080              LSLS     r0,r0,#2
000006  5819              LDR      r1,[r3,r0]
000008  68ca              LDR      r2,[r1,#0xc]
00000a  2408              MOVS     r4,#8
00000c  43a2              BICS     r2,r2,r4
00000e  60ca              STR      r2,[r1,#0xc]
;;;455        SPI_PORT[eSpiPort]->SSR_BITS.SSR = eDRVSPI_NONE;
000010  5818              LDR      r0,[r3,r0]
000012  68c1              LDR      r1,[r0,#0xc]
000014  0889              LSRS     r1,r1,#2
000016  0089              LSLS     r1,r1,#2
000018  60c1              STR      r1,[r0,#0xc]
;;;456    }
00001a  bd10              POP      {r4,pc}
;;;457    
                          ENDP

                  |L11.28|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_DisableInt||, CODE, READONLY, ALIGN=2

                  DrvSPI_DisableInt PROC
;;;623      */
;;;624    void DrvSPI_DisableInt(E_DRVSPI_PORT eSpiPort)
000000  2114              MOVS     r1,#0x14
;;;625    {
;;;626    	g_sSpiHandler[eSpiPort].pfncallback = NULL;
000002  4b0a              LDR      r3,|L12.44|
000004  b510              PUSH     {r4,lr}               ;625
000006  4341              MULS     r1,r0,r1
000008  2200              MOVS     r2,#0
00000a  18c9              ADDS     r1,r1,r3
;;;627    	g_sSpiHandler[eSpiPort].u32userData = 0;
00000c  604a              STR      r2,[r1,#4]
;;;628    	
;;;629    	SPI_PORT[eSpiPort]->CTL_BITS.INTEN = 0;
00000e  608a              STR      r2,[r1,#8]
000010  0082              LSLS     r2,r0,#2
000012  4619              MOV      r1,r3
000014  313c              ADDS     r1,r1,#0x3c
000016  5889              LDR      r1,[r1,r2]
000018  680a              LDR      r2,[r1,#0]
00001a  2301              MOVS     r3,#1
00001c  045b              LSLS     r3,r3,#17
00001e  439a              BICS     r2,r2,r3
000020  600a              STR      r2,[r1,#0]
;;;630    	
;;;631    	NVIC_DisableIRQ((IRQn_Type)(SPI0_IRQn+(uint32_t)eSpiPort));
000022  300e              ADDS     r0,r0,#0xe
000024  b240              SXTB     r0,r0
000026  f7fffffe          BL       NVIC_DisableIRQ
;;;632    }
00002a  bd10              POP      {r4,pc}
;;;633    
                          ENDP

                  |L12.44|
                          DCD      ||.bss||

                          AREA ||i.DrvSPI_DumpRxRegister||, CODE, READONLY, ALIGN=2

                  DrvSPI_DumpRxRegister PROC
;;;695      */
;;;696    uint32_t DrvSPI_DumpRxRegister(E_DRVSPI_PORT eSpiPort, uint32_t *pu32Buf, uint32_t u32DataCount)
000000  4603              MOV      r3,r0
;;;697    {
000002  4610              MOV      r0,r2
000004  b510              PUSH     {r4,lr}
;;;698    	assert_param(SPI_CHECK_SET_DATAREG_NUM);
;;;699    	
;;;700    	pu32Buf[0] = SPI_PORT[eSpiPort]->RX0;
000006  4a05              LDR      r2,|L13.28|
000008  009b              LSLS     r3,r3,#2
00000a  58d4              LDR      r4,[r2,r3]
00000c  6924              LDR      r4,[r4,#0x10]
;;;701    	
;;;702    	if(u32DataCount == 2)
00000e  600c              STR      r4,[r1,#0]
000010  2802              CMP      r0,#2
000012  d102              BNE      |L13.26|
;;;703    		pu32Buf[1] = SPI_PORT[eSpiPort]->RX1;
000014  58d2              LDR      r2,[r2,r3]
000016  6952              LDR      r2,[r2,#0x14]
000018  604a              STR      r2,[r1,#4]
                  |L13.26|
;;;704    	
;;;705        return u32DataCount;
;;;706    }
00001a  bd10              POP      {r4,pc}
;;;707    
                          ENDP

                  |L13.28|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Enable3Wire||, CODE, READONLY, ALIGN=2

                  DrvSPI_Enable3Wire PROC
;;;766      */
;;;767    void DrvSPI_Enable3Wire(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;768    {
;;;769        SPI_PORT[eSpiPort]->SSR_BITS.NOSLVSEL = 1;
000002  4803              LDR      r0,|L14.16|
000004  5840              LDR      r0,[r0,r1]
000006  68c1              LDR      r1,[r0,#0xc]
000008  2220              MOVS     r2,#0x20
00000a  4311              ORRS     r1,r1,r2
00000c  60c1              STR      r1,[r0,#0xc]
;;;770    }
00000e  4770              BX       lr
;;;771    
                          ENDP

                  |L14.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Enable3WireStartInt||, CODE, READONLY, ALIGN=2

                  DrvSPI_Enable3WireStartInt PROC
;;;800      */
;;;801    void DrvSPI_Enable3WireStartInt(E_DRVSPI_PORT eSpiPort, PFN_DRVSPI_CALLBACK pfnCallback, uint32_t u32UserData)
000000  b510              PUSH     {r4,lr}
;;;802    {    
;;;803        assert_param(SPI_CHECK_CALLBACK_PR);
;;;804        g_sSpiHandler[eSpiPort].pfn3WireStartCallBack = pfnCallback;
000002  2314              MOVS     r3,#0x14
000004  4c19              LDR      r4,|L15.108|
000006  4343              MULS     r3,r0,r3
000008  191b              ADDS     r3,r3,r4
;;;805        g_sSpiHandler[eSpiPort].u32ThreeWireStartUserData = u32UserData;
;;;806            
;;;807        SPI_PORT[eSpiPort]->SSR_BITS.SSTA_INTEN = 1;
00000a  611a              STR      r2,[r3,#0x10]
00000c  60d9              STR      r1,[r3,#0xc]
00000e  0082              LSLS     r2,r0,#2
000010  4621              MOV      r1,r4
000012  313c              ADDS     r1,r1,#0x3c
000014  5889              LDR      r1,[r1,r2]
000016  68ca              LDR      r2,[r1,#0xc]
000018  2301              MOVS     r3,#1
00001a  025b              LSLS     r3,r3,#9
00001c  431a              ORRS     r2,r2,r3
00001e  60ca              STR      r2,[r1,#0xc]
;;;808        
;;;809        NVIC_SetPriority((IRQn_Type)(SPI0_IRQn+(uint32_t)eSpiPort), (1<<__NVIC_PRIO_BITS) - 2);
000020  300e              ADDS     r0,r0,#0xe
000022  b240              SXTB     r0,r0
000024  0781              LSLS     r1,r0,#30
000026  0ecb              LSRS     r3,r1,#27
000028  21ff              MOVS     r1,#0xff
00002a  4099              LSLS     r1,r1,r3
00002c  2280              MOVS     r2,#0x80
00002e  409a              LSLS     r2,r2,r3
000030  2800              CMP      r0,#0
000032  da0b              BGE      |L15.76|
000034  0703              LSLS     r3,r0,#28
000036  0f1b              LSRS     r3,r3,#28
000038  3b08              SUBS     r3,r3,#8
00003a  089c              LSRS     r4,r3,#2
00003c  4b0c              LDR      r3,|L15.112|
00003e  00a4              LSLS     r4,r4,#2
000040  18e3              ADDS     r3,r4,r3
000042  69dc              LDR      r4,[r3,#0x1c]
000044  438c              BICS     r4,r4,r1
000046  4314              ORRS     r4,r4,r2
000048  61dc              STR      r4,[r3,#0x1c]
00004a  e007              B        |L15.92|
                  |L15.76|
00004c  0884              LSRS     r4,r0,#2
00004e  4b09              LDR      r3,|L15.116|
000050  00a4              LSLS     r4,r4,#2
000052  18e3              ADDS     r3,r4,r3
000054  681c              LDR      r4,[r3,#0]
000056  438c              BICS     r4,r4,r1
000058  4314              ORRS     r4,r4,r2
00005a  601c              STR      r4,[r3,#0]
                  |L15.92|
00005c  06c1              LSLS     r1,r0,#27
00005e  0ec9              LSRS     r1,r1,#27
000060  2001              MOVS     r0,#1
000062  4088              LSLS     r0,r0,r1
000064  4904              LDR      r1,|L15.120|
000066  6008              STR      r0,[r1,#0]
;;;810        NVIC_EnableIRQ((IRQn_Type)(SPI0_IRQn+(uint32_t)eSpiPort));   
;;;811    }   
000068  bd10              POP      {r4,pc}
;;;812    
                          ENDP

00006a  0000              DCW      0x0000
                  |L15.108|
                          DCD      ||.bss||
                  |L15.112|
                          DCD      0xe000ed00
                  |L15.116|
                          DCD      0xe000e400
                  |L15.120|
                          DCD      0xe000e100

                          AREA ||i.DrvSPI_EnableAutoSS||, CODE, READONLY, ALIGN=2

                  DrvSPI_EnableAutoSS PROC
;;;440      */
;;;441    void DrvSPI_EnableAutoSS(E_DRVSPI_PORT eSpiPort, E_DRVSPI_SLAVE_SEL eSlaveSel)
000000  b530              PUSH     {r4,r5,lr}
;;;442    {
;;;443        SPI_PORT[eSpiPort]->SSR_BITS.AUTOSS = 1;
000002  4b08              LDR      r3,|L16.36|
000004  0080              LSLS     r0,r0,#2
000006  581a              LDR      r2,[r3,r0]
000008  68d4              LDR      r4,[r2,#0xc]
00000a  2508              MOVS     r5,#8
00000c  432c              ORRS     r4,r4,r5
00000e  60d4              STR      r4,[r2,#0xc]
;;;444        SPI_PORT[eSpiPort]->SSR_BITS.SSR = eSlaveSel;
000010  5818              LDR      r0,[r3,r0]
000012  68c2              LDR      r2,[r0,#0xc]
000014  0789              LSLS     r1,r1,#30
000016  0892              LSRS     r2,r2,#2
000018  0092              LSLS     r2,r2,#2
00001a  0f89              LSRS     r1,r1,#30
00001c  430a              ORRS     r2,r2,r1
00001e  60c2              STR      r2,[r0,#0xc]
;;;445    }
000020  bd30              POP      {r4,r5,pc}
;;;446    
                          ENDP

000022  0000              DCW      0x0000
                  |L16.36|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_EnableInt||, CODE, READONLY, ALIGN=2

                  DrvSPI_EnableInt PROC
;;;606      */
;;;607    void DrvSPI_EnableInt(E_DRVSPI_PORT eSpiPort, PFN_DRVSPI_CALLBACK pfnCallback, uint32_t u32UserData)
000000  b510              PUSH     {r4,lr}
;;;608    {
;;;609    	assert_param(SPI_CHECK_CALLBACK_PR);
;;;610    	
;;;611    	g_sSpiHandler[eSpiPort].pfncallback = pfnCallback;
000002  2314              MOVS     r3,#0x14
000004  4c0a              LDR      r4,|L17.48|
000006  4343              MULS     r3,r0,r3
000008  191b              ADDS     r3,r3,r4
;;;612    	g_sSpiHandler[eSpiPort].u32userData = u32UserData;
;;;613    		
;;;614    	SPI_PORT[eSpiPort]->CTL_BITS.INTEN = 1;
00000a  609a              STR      r2,[r3,#8]
00000c  6059              STR      r1,[r3,#4]
00000e  0082              LSLS     r2,r0,#2
000010  4621              MOV      r1,r4
000012  313c              ADDS     r1,r1,#0x3c
000014  5889              LDR      r1,[r1,r2]
000016  680a              LDR      r2,[r1,#0]
000018  2301              MOVS     r3,#1
00001a  045b              LSLS     r3,r3,#17
00001c  431a              ORRS     r2,r2,r3
00001e  600a              STR      r2,[r1,#0]
;;;615    	
;;;616    	NVIC_EnableIRQ((IRQn_Type)(SPI0_IRQn+(uint32_t)eSpiPort));
000020  300e              ADDS     r0,r0,#0xe
000022  06c1              LSLS     r1,r0,#27
000024  0ec9              LSRS     r1,r1,#27
000026  2001              MOVS     r0,#1
000028  4088              LSLS     r0,r0,r1
00002a  4902              LDR      r1,|L17.52|
00002c  6008              STR      r0,[r1,#0]
;;;617    }	
00002e  bd10              POP      {r4,pc}
;;;618    
                          ENDP

                  |L17.48|
                          DCD      ||.bss||
                  |L17.52|
                          DCD      0xe000e100

                          AREA ||i.DrvSPI_FIFORead16||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFORead16 PROC
;;;1058     */
;;;1059   int32_t DrvSPI_FIFORead16(E_DRVSPI_PORT eSpiPort, uint16_t *pu16RxBuf, uint32_t u32ReadLength)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1060   {
;;;1061   	uint32_t  u32Count, u32delayno;
;;;1062   		 	
;;;1063   	for (u32Count=0; u32Count<u32ReadLength; u32Count++)
000002  2300              MOVS     r3,#0
;;;1064       {
;;;1065       	u32delayno = 0;
;;;1066   	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY == 1)  /* Wait Rx is not empty and Time-out manner */
000004  0087              LSLS     r7,r0,#2
;;;1067           {
;;;1068          	    u32delayno++;
;;;1069          	    if ( u32delayno >= 0x40000000 )     	    
000006  2601              MOVS     r6,#1
000008  07b6              LSLS     r6,r6,#30
00000a  e010              B        |L18.46|
                  |L18.12|
00000c  4c0a              LDR      r4,|L18.56|
00000e  2000              MOVS     r0,#0                 ;1065
000010  59e4              LDR      r4,[r4,r7]            ;1066
;;;1070          	       return E_DRVSPI_ERR_TIMEOUT;   
000012  e005              B        |L18.32|
                  |L18.20|
000014  1c40              ADDS     r0,r0,#1              ;1068
000016  42b0              CMP      r0,r6                 ;1069
000018  d302              BCC      |L18.32|
00001a  2000              MOVS     r0,#0
00001c  43c0              MVNS     r0,r0
;;;1071   				   
;;;1072           }
;;;1073           pu16RxBuf[u32Count] = SPI_PORT[eSpiPort]->RX0;
;;;1074       }
;;;1075       
;;;1076       return E_SUCCESS;
;;;1077   }
00001e  bdf0              POP      {r4-r7,pc}
                  |L18.32|
000020  6865              LDR      r5,[r4,#4]            ;1066
000022  07ed              LSLS     r5,r5,#31             ;1066
000024  d1f6              BNE      |L18.20|
000026  6920              LDR      r0,[r4,#0x10]         ;1073
000028  005c              LSLS     r4,r3,#1              ;1073
00002a  5308              STRH     r0,[r1,r4]            ;1073
00002c  1c5b              ADDS     r3,r3,#1              ;1063
                  |L18.46|
00002e  4293              CMP      r3,r2                 ;1063
000030  d3ec              BCC      |L18.12|
000032  2000              MOVS     r0,#0                 ;1076
000034  bdf0              POP      {r4-r7,pc}
;;;1078   
                          ENDP

000036  0000              DCW      0x0000
                  |L18.56|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFORead32||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFORead32 PROC
;;;1086     */
;;;1087   int32_t DrvSPI_FIFORead32(E_DRVSPI_PORT eSpiPort, uint32_t *pu32RxBuf, uint32_t u32ReadLength)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1088   {
;;;1089   	uint32_t  u32Count, u32delayno;
;;;1090   		 	
;;;1091   	for (u32Count=0; u32Count<u32ReadLength; u32Count++)
000002  2300              MOVS     r3,#0
;;;1092       {
;;;1093       	u32delayno = 0;
;;;1094   	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY == 1)  /* Wait Rx is not empty and Time-out manner */
000004  0087              LSLS     r7,r0,#2
;;;1095           {
;;;1096          	    u32delayno++;
;;;1097          	    if ( u32delayno >= 0x40000000 )     	    
000006  2601              MOVS     r6,#1
000008  07b6              LSLS     r6,r6,#30
00000a  e010              B        |L19.46|
                  |L19.12|
00000c  4c0a              LDR      r4,|L19.56|
00000e  2000              MOVS     r0,#0                 ;1093
000010  59e4              LDR      r4,[r4,r7]            ;1094
;;;1098          	       return E_DRVSPI_ERR_TIMEOUT;   
000012  e005              B        |L19.32|
                  |L19.20|
000014  1c40              ADDS     r0,r0,#1              ;1096
000016  42b0              CMP      r0,r6                 ;1097
000018  d302              BCC      |L19.32|
00001a  2000              MOVS     r0,#0
00001c  43c0              MVNS     r0,r0
;;;1099   				   
;;;1100           }
;;;1101           pu32RxBuf[u32Count] = SPI_PORT[eSpiPort]->RX0;
;;;1102       }
;;;1103       
;;;1104       return E_SUCCESS;
;;;1105   }
00001e  bdf0              POP      {r4-r7,pc}
                  |L19.32|
000020  6865              LDR      r5,[r4,#4]            ;1094
000022  07ed              LSLS     r5,r5,#31             ;1094
000024  d1f6              BNE      |L19.20|
000026  6920              LDR      r0,[r4,#0x10]         ;1101
000028  009c              LSLS     r4,r3,#2              ;1101
00002a  5108              STR      r0,[r1,r4]            ;1101
00002c  1c5b              ADDS     r3,r3,#1              ;1091
                  |L19.46|
00002e  4293              CMP      r3,r2                 ;1091
000030  d3ec              BCC      |L19.12|
000032  2000              MOVS     r0,#0                 ;1104
000034  bdf0              POP      {r4-r7,pc}
;;;1106   
                          ENDP

000036  0000              DCW      0x0000
                  |L19.56|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFORead8||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFORead8 PROC
;;;1030     */
;;;1031   int32_t DrvSPI_FIFORead8(E_DRVSPI_PORT eSpiPort, uint8_t *pu8RxBuf, uint32_t u32ReadLength)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1032   {
;;;1033   	uint32_t  u32Count, u32delayno;
;;;1034   		 	
;;;1035   	for (u32Count=0; u32Count<u32ReadLength; u32Count++)
000002  2300              MOVS     r3,#0
;;;1036       {
;;;1037       	u32delayno = 0;
;;;1038   	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY == 1)  /* Wait Rx is not empty and Time-out manner */
000004  0087              LSLS     r7,r0,#2
;;;1039           {
;;;1040          	    u32delayno++;
;;;1041          	    if ( u32delayno >= 0x40000000 )     	    
000006  2601              MOVS     r6,#1
000008  07b6              LSLS     r6,r6,#30
00000a  e00f              B        |L20.44|
                  |L20.12|
00000c  4c09              LDR      r4,|L20.52|
00000e  2000              MOVS     r0,#0                 ;1037
000010  59e4              LDR      r4,[r4,r7]            ;1038
;;;1042          	       return E_DRVSPI_ERR_TIMEOUT;   
000012  e005              B        |L20.32|
                  |L20.20|
000014  1c40              ADDS     r0,r0,#1              ;1040
000016  42b0              CMP      r0,r6                 ;1041
000018  d302              BCC      |L20.32|
00001a  2000              MOVS     r0,#0
00001c  43c0              MVNS     r0,r0
;;;1043   				   
;;;1044           }
;;;1045           pu8RxBuf[u32Count] = SPI_PORT[eSpiPort]->RX0;
;;;1046       }
;;;1047       
;;;1048       return E_SUCCESS;
;;;1049   }
00001e  bdf0              POP      {r4-r7,pc}
                  |L20.32|
000020  6865              LDR      r5,[r4,#4]            ;1038
000022  07ed              LSLS     r5,r5,#31             ;1038
000024  d1f6              BNE      |L20.20|
000026  6920              LDR      r0,[r4,#0x10]         ;1045
000028  54c8              STRB     r0,[r1,r3]            ;1045
00002a  1c5b              ADDS     r3,r3,#1              ;1035
                  |L20.44|
00002c  4293              CMP      r3,r2                 ;1035
00002e  d3ed              BCC      |L20.12|
000030  2000              MOVS     r0,#0                 ;1048
000032  bdf0              POP      {r4-r7,pc}
;;;1050   
                          ENDP

                  |L20.52|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFOReadWrite16||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFOReadWrite16 PROC
;;;1164     */  
;;;1165   int32_t DrvSPI_FIFOReadWrite16(E_DRVSPI_PORT eSpiPort, uint16_t *pu16TxBuf, uint32_t *pu16RxBuf, uint32_t u32Length)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1166   {
;;;1167   	uint32_t  u32Count, u32RxCount = 0;
000002  2400              MOVS     r4,#0
000004  468c              MOV      r12,r1                ;1166
;;;1168   	 
;;;1169   	for (u32Count=0; u32Count<u32Length; u32Count++)
000006  4625              MOV      r5,r4
;;;1170       {    	
;;;1171   	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.TX_FULL == 1)  /* if Tx is full, process Rx */
;;;1172           {
;;;1173          	    while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1174      	    		pu16RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;				   
000008  0080              LSLS     r0,r0,#2
00000a  4920              LDR      r1,|L21.140|
00000c  e024              B        |L21.88|
                  |L21.14|
00000e  6936              LDR      r6,[r6,#0x10]
000010  00a7              LSLS     r7,r4,#2
000012  51d6              STR      r6,[r2,r7]
000014  1c64              ADDS     r4,r4,#1
                  |L21.22|
000016  580e              LDR      r6,[r1,r0]            ;1173
000018  6877              LDR      r7,[r6,#4]            ;1173
00001a  07ff              LSLS     r7,r7,#31             ;1173
00001c  d0f7              BEQ      |L21.14|
                  |L21.30|
00001e  580e              LDR      r6,[r1,r0]            ;1171
000020  6876              LDR      r6,[r6,#4]            ;1171
000022  0736              LSLS     r6,r6,#28             ;1171
000024  d4f7              BMI      |L21.22|
;;;1175           }
;;;1176           
;;;1177           if(pu16TxBuf == NULL)
000026  4666              MOV      r6,r12
000028  2e00              CMP      r6,#0
00002a  d009              BEQ      |L21.64|
;;;1178           	SPI_PORT[eSpiPort]->TX0 = 0xFFFFFFFF;
;;;1179           else
;;;1180           	SPI_PORT[eSpiPort]->TX0 = pu16TxBuf[u32Count];
00002c  006e              LSLS     r6,r5,#1
00002e  4667              MOV      r7,r12
000030  5bbe              LDRH     r6,[r7,r6]
                  |L21.50|
000032  580f              LDR      r7,[r1,r0]
000034  623e              STR      r6,[r7,#0x20]
;;;1181   
;;;1182           if(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)	/* check if rx has something */
000036  580e              LDR      r6,[r1,r0]
000038  6876              LDR      r6,[r6,#4]
00003a  07f6              LSLS     r6,r6,#31
00003c  d007              BEQ      |L21.78|
00003e  e00a              B        |L21.86|
                  |L21.64|
000040  2600              MOVS     r6,#0                 ;1178
000042  43f6              MVNS     r6,r6                 ;1178
000044  e7f5              B        |L21.50|
                  |L21.70|
;;;1183       	{
;;;1184       		while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1185       			pu16RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
000046  6936              LDR      r6,[r6,#0x10]
000048  00a7              LSLS     r7,r4,#2
00004a  51d6              STR      r6,[r2,r7]
00004c  1c64              ADDS     r4,r4,#1
                  |L21.78|
00004e  580e              LDR      r6,[r1,r0]            ;1184
000050  6877              LDR      r7,[r6,#4]            ;1184
000052  07ff              LSLS     r7,r7,#31             ;1184
000054  d0f7              BEQ      |L21.70|
                  |L21.86|
000056  1c6d              ADDS     r5,r5,#1              ;1169
                  |L21.88|
000058  429d              CMP      r5,r3                 ;1169
00005a  d3e0              BCC      |L21.30|
00005c  e007              B        |L21.110|
                  |L21.94|
;;;1186       	}
;;;1187       }
;;;1188       
;;;1189       // SPI is still in progress, check Rx if something is in FIFO 
;;;1190       while(SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY == 1)
;;;1191       {
;;;1192       	while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1193       		pu16RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
00005e  691b              LDR      r3,[r3,#0x10]
000060  00a5              LSLS     r5,r4,#2
000062  5153              STR      r3,[r2,r5]
000064  1c64              ADDS     r4,r4,#1
                  |L21.102|
000066  580b              LDR      r3,[r1,r0]            ;1192
000068  685d              LDR      r5,[r3,#4]            ;1192
00006a  07ed              LSLS     r5,r5,#31             ;1192
00006c  d0f7              BEQ      |L21.94|
                  |L21.110|
00006e  580b              LDR      r3,[r1,r0]            ;1190
000070  681b              LDR      r3,[r3,#0]            ;1190
000072  07db              LSLS     r3,r3,#31             ;1190
000074  d1f7              BNE      |L21.102|
000076  e003              B        |L21.128|
                  |L21.120|
;;;1194       }
;;;1195       
;;;1196       // SPI is finisned, but still need to check FIFO status
;;;1197       while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1198       	pu16RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
000078  691b              LDR      r3,[r3,#0x10]
00007a  00a5              LSLS     r5,r4,#2
00007c  5153              STR      r3,[r2,r5]
00007e  1c64              ADDS     r4,r4,#1
                  |L21.128|
000080  580b              LDR      r3,[r1,r0]            ;1197
000082  685d              LDR      r5,[r3,#4]            ;1197
000084  07ed              LSLS     r5,r5,#31             ;1197
000086  d0f7              BEQ      |L21.120|
;;;1199       		
;;;1200       return E_SUCCESS;
000088  2000              MOVS     r0,#0
;;;1201   }
00008a  bdf0              POP      {r4-r7,pc}
;;;1202   
                          ENDP

                  |L21.140|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFOReadWrite32||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFOReadWrite32 PROC
;;;1212     */  
;;;1213   int32_t DrvSPI_FIFOReadWrite32(E_DRVSPI_PORT eSpiPort, uint32_t *pu32TxBuf, uint32_t *pu32RxBuf, uint32_t u32Length)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1214   {
;;;1215   	uint32_t  u32Count, u32RxCount = 0;
000002  2400              MOVS     r4,#0
000004  468c              MOV      r12,r1                ;1214
;;;1216   	 
;;;1217   	for (u32Count=0; u32Count<u32Length; u32Count++)
000006  4625              MOV      r5,r4
;;;1218       {    	
;;;1219   	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.TX_FULL == 1)  /* if Tx is full, process Rx */
;;;1220           {
;;;1221          	    while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1222      	    		pu32RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;				   
000008  0080              LSLS     r0,r0,#2
00000a  4920              LDR      r1,|L22.140|
00000c  e024              B        |L22.88|
                  |L22.14|
00000e  6936              LDR      r6,[r6,#0x10]
000010  00a7              LSLS     r7,r4,#2
000012  51d6              STR      r6,[r2,r7]
000014  1c64              ADDS     r4,r4,#1
                  |L22.22|
000016  580e              LDR      r6,[r1,r0]            ;1221
000018  6877              LDR      r7,[r6,#4]            ;1221
00001a  07ff              LSLS     r7,r7,#31             ;1221
00001c  d0f7              BEQ      |L22.14|
                  |L22.30|
00001e  580e              LDR      r6,[r1,r0]            ;1219
000020  6876              LDR      r6,[r6,#4]            ;1219
000022  0736              LSLS     r6,r6,#28             ;1219
000024  d4f7              BMI      |L22.22|
;;;1223           }
;;;1224           
;;;1225           if(pu32TxBuf == NULL)
000026  4666              MOV      r6,r12
000028  2e00              CMP      r6,#0
00002a  d009              BEQ      |L22.64|
;;;1226           	SPI_PORT[eSpiPort]->TX0 = 0xFFFFFFFF;
;;;1227           else
;;;1228           	SPI_PORT[eSpiPort]->TX0 = pu32TxBuf[u32Count];
00002c  00ae              LSLS     r6,r5,#2
00002e  4667              MOV      r7,r12
000030  59be              LDR      r6,[r7,r6]
                  |L22.50|
000032  580f              LDR      r7,[r1,r0]
000034  623e              STR      r6,[r7,#0x20]
;;;1229   
;;;1230           if(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)	/* check if rx has something */
000036  580e              LDR      r6,[r1,r0]
000038  6876              LDR      r6,[r6,#4]
00003a  07f6              LSLS     r6,r6,#31
00003c  d007              BEQ      |L22.78|
00003e  e00a              B        |L22.86|
                  |L22.64|
000040  2600              MOVS     r6,#0                 ;1226
000042  43f6              MVNS     r6,r6                 ;1226
000044  e7f5              B        |L22.50|
                  |L22.70|
;;;1231       	{
;;;1232       		while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1233       			pu32RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
000046  6936              LDR      r6,[r6,#0x10]
000048  00a7              LSLS     r7,r4,#2
00004a  51d6              STR      r6,[r2,r7]
00004c  1c64              ADDS     r4,r4,#1
                  |L22.78|
00004e  580e              LDR      r6,[r1,r0]            ;1232
000050  6877              LDR      r7,[r6,#4]            ;1232
000052  07ff              LSLS     r7,r7,#31             ;1232
000054  d0f7              BEQ      |L22.70|
                  |L22.86|
000056  1c6d              ADDS     r5,r5,#1              ;1217
                  |L22.88|
000058  429d              CMP      r5,r3                 ;1217
00005a  d3e0              BCC      |L22.30|
00005c  e007              B        |L22.110|
                  |L22.94|
;;;1234       	}
;;;1235       }
;;;1236       
;;;1237       // SPI is still in progress, check Rx if something is in FIFO 
;;;1238       while(SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY == 1)
;;;1239       {
;;;1240       	while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1241       		pu32RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
00005e  691b              LDR      r3,[r3,#0x10]
000060  00a5              LSLS     r5,r4,#2
000062  5153              STR      r3,[r2,r5]
000064  1c64              ADDS     r4,r4,#1
                  |L22.102|
000066  580b              LDR      r3,[r1,r0]            ;1240
000068  685d              LDR      r5,[r3,#4]            ;1240
00006a  07ed              LSLS     r5,r5,#31             ;1240
00006c  d0f7              BEQ      |L22.94|
                  |L22.110|
00006e  580b              LDR      r3,[r1,r0]            ;1238
000070  681b              LDR      r3,[r3,#0]            ;1238
000072  07db              LSLS     r3,r3,#31             ;1238
000074  d1f7              BNE      |L22.102|
000076  e003              B        |L22.128|
                  |L22.120|
;;;1242       }
;;;1243       
;;;1244       // SPI is finisned, but still need to check FIFO status
;;;1245       while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1246       	pu32RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
000078  691b              LDR      r3,[r3,#0x10]
00007a  00a5              LSLS     r5,r4,#2
00007c  5153              STR      r3,[r2,r5]
00007e  1c64              ADDS     r4,r4,#1
                  |L22.128|
000080  580b              LDR      r3,[r1,r0]            ;1245
000082  685d              LDR      r5,[r3,#4]            ;1245
000084  07ed              LSLS     r5,r5,#31             ;1245
000086  d0f7              BEQ      |L22.120|
;;;1247       		
;;;1248       return E_SUCCESS;
000088  2000              MOVS     r0,#0
;;;1249   }
00008a  bdf0              POP      {r4-r7,pc}
;;;1250   
                          ENDP

                  |L22.140|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFOReadWrite8||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFOReadWrite8 PROC
;;;1116     */  
;;;1117   int32_t DrvSPI_FIFOReadWrite8(E_DRVSPI_PORT eSpiPort, uint8_t *pu8TxBuf, uint8_t *pu8RxBuf, uint32_t u32Length)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1118   {
;;;1119   	uint32_t  u32Count, u32RxCount = 0;
000002  2400              MOVS     r4,#0
000004  468c              MOV      r12,r1                ;1118
;;;1120   	 
;;;1121   	for (u32Count=0; u32Count<u32Length; u32Count++)
000006  4625              MOV      r5,r4
;;;1122       {    	
;;;1123   	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.TX_FULL == 1)  /* if Tx is full, process Rx */
;;;1124           {
;;;1125          	    while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1126      	    		pu8RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;				   
000008  0080              LSLS     r0,r0,#2
00000a  4f1d              LDR      r7,|L23.128|
00000c  e020              B        |L23.80|
                  |L23.14|
00000e  6936              LDR      r6,[r6,#0x10]
000010  5516              STRB     r6,[r2,r4]
000012  1c64              ADDS     r4,r4,#1
                  |L23.20|
000014  583e              LDR      r6,[r7,r0]            ;1125
000016  6871              LDR      r1,[r6,#4]            ;1125
000018  07c9              LSLS     r1,r1,#31             ;1125
00001a  d0f8              BEQ      |L23.14|
                  |L23.28|
00001c  5839              LDR      r1,[r7,r0]            ;1123
00001e  6849              LDR      r1,[r1,#4]            ;1123
000020  0709              LSLS     r1,r1,#28             ;1123
000022  d4f7              BMI      |L23.20|
;;;1127           }
;;;1128           
;;;1129           if(pu8TxBuf == NULL)
000024  4661              MOV      r1,r12
000026  2900              CMP      r1,#0
000028  d007              BEQ      |L23.58|
;;;1130           	SPI_PORT[eSpiPort]->TX0 = 0xFFFFFFFF;
;;;1131           else
;;;1132           	SPI_PORT[eSpiPort]->TX0 = pu8TxBuf[u32Count];
00002a  5d49              LDRB     r1,[r1,r5]
                  |L23.44|
00002c  583e              LDR      r6,[r7,r0]
00002e  6231              STR      r1,[r6,#0x20]
;;;1133   
;;;1134           if(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)	/* check if rx has something */
000030  5839              LDR      r1,[r7,r0]
000032  6849              LDR      r1,[r1,#4]
000034  07c9              LSLS     r1,r1,#31
000036  d006              BEQ      |L23.70|
000038  e009              B        |L23.78|
                  |L23.58|
00003a  2100              MOVS     r1,#0                 ;1130
00003c  43c9              MVNS     r1,r1                 ;1130
00003e  e7f5              B        |L23.44|
                  |L23.64|
;;;1135       	{
;;;1136       		while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1137       			pu8RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
000040  6909              LDR      r1,[r1,#0x10]
000042  5511              STRB     r1,[r2,r4]
000044  1c64              ADDS     r4,r4,#1
                  |L23.70|
000046  5839              LDR      r1,[r7,r0]            ;1136
000048  684e              LDR      r6,[r1,#4]            ;1136
00004a  07f6              LSLS     r6,r6,#31             ;1136
00004c  d0f8              BEQ      |L23.64|
                  |L23.78|
00004e  1c6d              ADDS     r5,r5,#1              ;1121
                  |L23.80|
000050  429d              CMP      r5,r3                 ;1121
000052  d3e3              BCC      |L23.28|
000054  e006              B        |L23.100|
                  |L23.86|
;;;1138       	}
;;;1139       }
;;;1140       
;;;1141       // SPI is still in progress, check Rx if something is in FIFO 
;;;1142       while(SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY == 1)
;;;1143       {
;;;1144       	while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1145       		pu8RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
000056  6909              LDR      r1,[r1,#0x10]
000058  5511              STRB     r1,[r2,r4]
00005a  1c64              ADDS     r4,r4,#1
                  |L23.92|
00005c  5839              LDR      r1,[r7,r0]            ;1144
00005e  684b              LDR      r3,[r1,#4]            ;1144
000060  07db              LSLS     r3,r3,#31             ;1144
000062  d0f8              BEQ      |L23.86|
                  |L23.100|
000064  5839              LDR      r1,[r7,r0]            ;1142
000066  6809              LDR      r1,[r1,#0]            ;1142
000068  07c9              LSLS     r1,r1,#31             ;1142
00006a  d1f7              BNE      |L23.92|
00006c  e002              B        |L23.116|
                  |L23.110|
;;;1146       }
;;;1147       
;;;1148       // SPI is finisned, but still need to check FIFO status
;;;1149       while(SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY != 1)
;;;1150       	pu8RxBuf[u32RxCount++] = SPI_PORT[eSpiPort]->RX0;
00006e  6909              LDR      r1,[r1,#0x10]
000070  5511              STRB     r1,[r2,r4]
000072  1c64              ADDS     r4,r4,#1
                  |L23.116|
000074  5839              LDR      r1,[r7,r0]            ;1149
000076  684b              LDR      r3,[r1,#4]            ;1149
000078  07db              LSLS     r3,r3,#31             ;1149
00007a  d0f8              BEQ      |L23.110|
;;;1151       		
;;;1152       return E_SUCCESS;
00007c  2000              MOVS     r0,#0
;;;1153   }
00007e  bdf0              POP      {r4-r7,pc}
;;;1154   
                          ENDP

                  |L23.128|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFOWrite16||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFOWrite16 PROC
;;;974      */
;;;975    int32_t DrvSPI_FIFOWrite16(E_DRVSPI_PORT eSpiPort, uint16_t *pu16TxBuf, uint32_t u32WriteLength)
000000  b5f0              PUSH     {r4-r7,lr}
;;;976    {
;;;977    	uint32_t  u32Count, u32delayno;
;;;978    	 
;;;979    	for (u32Count=0; u32Count<u32WriteLength; u32Count++)
000002  2300              MOVS     r3,#0
;;;980        {
;;;981        	u32delayno = 0;
;;;982    	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.TX_FULL == 1)  /* Wait Tx is empty and Time-out manner */
000004  0087              LSLS     r7,r0,#2
;;;983            {
;;;984           	    u32delayno++;
;;;985           	    if ( u32delayno >= 0x40000000 )     	    
000006  2601              MOVS     r6,#1
000008  07b6              LSLS     r6,r6,#30
00000a  e010              B        |L24.46|
                  |L24.12|
00000c  4c0a              LDR      r4,|L24.56|
00000e  2000              MOVS     r0,#0                 ;981
000010  59e4              LDR      r4,[r4,r7]            ;982
;;;986           	       return E_DRVSPI_ERR_TIMEOUT;   
000012  e005              B        |L24.32|
                  |L24.20|
000014  1c40              ADDS     r0,r0,#1              ;984
000016  42b0              CMP      r0,r6                 ;985
000018  d302              BCC      |L24.32|
00001a  2000              MOVS     r0,#0
00001c  43c0              MVNS     r0,r0
;;;987    				   
;;;988            }
;;;989            SPI_PORT[eSpiPort]->TX0 = pu16TxBuf[u32Count];
;;;990        }
;;;991        
;;;992        return E_SUCCESS;
;;;993    }
00001e  bdf0              POP      {r4-r7,pc}
                  |L24.32|
000020  6865              LDR      r5,[r4,#4]            ;982
000022  072d              LSLS     r5,r5,#28             ;982
000024  d4f6              BMI      |L24.20|
000026  0058              LSLS     r0,r3,#1              ;989
000028  5a08              LDRH     r0,[r1,r0]            ;989
00002a  6220              STR      r0,[r4,#0x20]         ;989
00002c  1c5b              ADDS     r3,r3,#1              ;979
                  |L24.46|
00002e  4293              CMP      r3,r2                 ;979
000030  d3ec              BCC      |L24.12|
000032  2000              MOVS     r0,#0                 ;992
000034  bdf0              POP      {r4-r7,pc}
;;;994    
                          ENDP

000036  0000              DCW      0x0000
                  |L24.56|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFOWrite32||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFOWrite32 PROC
;;;1002     */
;;;1003   int32_t DrvSPI_FIFOWrite32(E_DRVSPI_PORT eSpiPort, uint32_t *pu32TxBuf, uint32_t u32WriteLength)
000000  b5f0              PUSH     {r4-r7,lr}
;;;1004   {
;;;1005   	uint32_t  u32Count, u32delayno;
;;;1006   	 
;;;1007   	for (u32Count=0; u32Count<u32WriteLength; u32Count++)
000002  2300              MOVS     r3,#0
;;;1008       {
;;;1009       	u32delayno = 0;
;;;1010   	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.TX_FULL == 1)  /* Wait Tx is empty and Time-out manner */
000004  0087              LSLS     r7,r0,#2
;;;1011           {
;;;1012          	    u32delayno++;
;;;1013          	    if ( u32delayno >= 0x40000000 )     	    
000006  2601              MOVS     r6,#1
000008  07b6              LSLS     r6,r6,#30
00000a  e010              B        |L25.46|
                  |L25.12|
00000c  4c0a              LDR      r4,|L25.56|
00000e  2000              MOVS     r0,#0                 ;1009
000010  59e4              LDR      r4,[r4,r7]            ;1010
;;;1014          	       return E_DRVSPI_ERR_TIMEOUT;   
000012  e005              B        |L25.32|
                  |L25.20|
000014  1c40              ADDS     r0,r0,#1              ;1012
000016  42b0              CMP      r0,r6                 ;1013
000018  d302              BCC      |L25.32|
00001a  2000              MOVS     r0,#0
00001c  43c0              MVNS     r0,r0
;;;1015   				   
;;;1016           }
;;;1017           SPI_PORT[eSpiPort]->TX0 = pu32TxBuf[u32Count];
;;;1018       }
;;;1019       
;;;1020       return E_SUCCESS;
;;;1021   }
00001e  bdf0              POP      {r4-r7,pc}
                  |L25.32|
000020  6865              LDR      r5,[r4,#4]            ;1010
000022  072d              LSLS     r5,r5,#28             ;1010
000024  d4f6              BMI      |L25.20|
000026  0098              LSLS     r0,r3,#2              ;1017
000028  5808              LDR      r0,[r1,r0]            ;1017
00002a  6220              STR      r0,[r4,#0x20]         ;1017
00002c  1c5b              ADDS     r3,r3,#1              ;1007
                  |L25.46|
00002e  4293              CMP      r3,r2                 ;1007
000030  d3ec              BCC      |L25.12|
000032  2000              MOVS     r0,#0                 ;1020
000034  bdf0              POP      {r4-r7,pc}
;;;1022   
                          ENDP

000036  0000              DCW      0x0000
                  |L25.56|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_FIFOWrite8||, CODE, READONLY, ALIGN=2

                  DrvSPI_FIFOWrite8 PROC
;;;946      */
;;;947    int32_t DrvSPI_FIFOWrite8(E_DRVSPI_PORT eSpiPort, uint8_t *pu8TxBuf, uint32_t u32WriteLength)
000000  b5f0              PUSH     {r4-r7,lr}
;;;948    {
;;;949    	uint32_t  u32Count, u32delayno;
;;;950    	 
;;;951    	for (u32Count=0; u32Count<u32WriteLength; u32Count++)
000002  2300              MOVS     r3,#0
;;;952        {
;;;953        	u32delayno = 0;
;;;954    	   	while (SPI_PORT[eSpiPort]->STATUS_BITS.TX_FULL == 1)  /* Wait Tx is empty and Time-out manner */
000004  0087              LSLS     r7,r0,#2
;;;955            {
;;;956           	    u32delayno++;
;;;957           	    if ( u32delayno >= 0x40000000 )     	    
000006  2601              MOVS     r6,#1
000008  07b6              LSLS     r6,r6,#30
00000a  e00f              B        |L26.44|
                  |L26.12|
00000c  4c09              LDR      r4,|L26.52|
00000e  2000              MOVS     r0,#0                 ;953
000010  59e4              LDR      r4,[r4,r7]            ;954
;;;958           	       return E_DRVSPI_ERR_TIMEOUT;   
000012  e005              B        |L26.32|
                  |L26.20|
000014  1c40              ADDS     r0,r0,#1              ;956
000016  42b0              CMP      r0,r6                 ;957
000018  d302              BCC      |L26.32|
00001a  2000              MOVS     r0,#0
00001c  43c0              MVNS     r0,r0
;;;959    				   
;;;960            }
;;;961            SPI_PORT[eSpiPort]->TX0 = pu8TxBuf[u32Count];
;;;962        }
;;;963        
;;;964        return E_SUCCESS;
;;;965    }
00001e  bdf0              POP      {r4-r7,pc}
                  |L26.32|
000020  6865              LDR      r5,[r4,#4]            ;954
000022  072d              LSLS     r5,r5,#28             ;954
000024  d4f6              BMI      |L26.20|
000026  5cc8              LDRB     r0,[r1,r3]            ;961
000028  6220              STR      r0,[r4,#0x20]         ;961
00002a  1c5b              ADDS     r3,r3,#1              ;951
                  |L26.44|
00002c  4293              CMP      r3,r2                 ;951
00002e  d3ed              BCC      |L26.12|
000030  2000              MOVS     r0,#0                 ;964
000032  bdf0              POP      {r4-r7,pc}
;;;966    
                          ENDP

                  |L26.52|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Get3WireStartIntFlag||, CODE, READONLY, ALIGN=2

                  DrvSPI_Get3WireStartIntFlag PROC
;;;832      */
;;;833    uint32_t DrvSPI_Get3WireStartIntFlag(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L27.16|
;;;834    {
;;;835        return (SPI_PORT[eSpiPort]->STATUS_BITS.SLV_START_INTSTS);
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6840              LDR      r0,[r0,#4]
000008  0640              LSLS     r0,r0,#25
00000a  0fc0              LSRS     r0,r0,#31
;;;836    }
00000c  4770              BX       lr
;;;837    
                          ENDP

00000e  0000              DCW      0x0000
                  |L27.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_GetClock1Freq||, CODE, READONLY, ALIGN=2

                  DrvSPI_GetClock1Freq PROC
;;;559      */
;;;560    uint32_t DrvSPI_GetClock1Freq(E_DRVSPI_PORT eSpiPort)
000000  b510              PUSH     {r4,lr}
;;;561    {
000002  4604              MOV      r4,r0
;;;562    	uint32_t u32Div;
;;;563    	uint32_t u32ApbClock;
;;;564    
;;;565    	u32ApbClock = DrvSYS_GetHCLKFreq();
000004  f7fffffe          BL       DrvSYS_GetHCLKFreq
;;;566    	u32Div = SPI_PORT[eSpiPort]->CLKDIV_BITS.DIVIDER1;
000008  4a05              LDR      r2,|L28.32|
00000a  00a1              LSLS     r1,r4,#2
00000c  5851              LDR      r1,[r2,r1]
00000e  6889              LDR      r1,[r1,#8]
000010  0649              LSLS     r1,r1,#25
000012  0e49              LSRS     r1,r1,#25
;;;567    	
;;;568    	if(u32Div == 0)	return u32ApbClock;
000014  d002              BEQ      |L28.28|
;;;569    	else return ((u32ApbClock >> 1) / u32Div);   /* SPI_CLK = APB_CLK / (Divider * 2) */
000016  0840              LSRS     r0,r0,#1
000018  f7fffffe          BL       __aeabi_uidivmod
                  |L28.28|
;;;570    }
00001c  bd10              POP      {r4,pc}
;;;571    
                          ENDP

00001e  0000              DCW      0x0000
                  |L28.32|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_GetClock2Freq||, CODE, READONLY, ALIGN=2

                  DrvSPI_GetClock2Freq PROC
;;;576      */
;;;577    uint32_t DrvSPI_GetClock2Freq(E_DRVSPI_PORT eSpiPort)
000000  b510              PUSH     {r4,lr}
;;;578    {
000002  4604              MOV      r4,r0
;;;579    	uint32_t u32Div;
;;;580    	uint32_t u32ApbClock;
;;;581    
;;;582    	u32ApbClock = DrvSYS_GetHCLKFreq();
000004  f7fffffe          BL       DrvSYS_GetHCLKFreq
;;;583    	u32Div = SPI_PORT[eSpiPort]->CLKDIV_BITS.DIVIDER2;
000008  4a05              LDR      r2,|L29.32|
00000a  00a1              LSLS     r1,r4,#2
00000c  5851              LDR      r1,[r2,r1]
00000e  6889              LDR      r1,[r1,#8]
;;;584    	return ((u32ApbClock >> 1) / (u32Div + 1));   /* SPI_CLK = APB_CLK / ((Divider + 1) * 2) */
000010  0840              LSRS     r0,r0,#1
000012  0209              LSLS     r1,r1,#8              ;583
000014  0e09              LSRS     r1,r1,#24             ;583
000016  1c49              ADDS     r1,r1,#1
000018  f7fffffe          BL       __aeabi_uidivmod
;;;585    }
00001c  bd10              POP      {r4,pc}
;;;586    
                          ENDP

00001e  0000              DCW      0x0000
                  |L29.32|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_GetIntFlag||, CODE, READONLY, ALIGN=2

                  DrvSPI_GetIntFlag PROC
;;;639      */
;;;640    uint32_t DrvSPI_GetIntFlag(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L30.16|
;;;641    {
;;;642    	return (SPI_PORT[eSpiPort]->STATUS_BITS.INTSTS);
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6840              LDR      r0,[r0,#4]
000008  0600              LSLS     r0,r0,#24
00000a  0fc0              LSRS     r0,r0,#31
;;;643    }
00000c  4770              BX       lr
;;;644    
                          ENDP

00000e  0000              DCW      0x0000
                  |L30.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_GetLevelTriggerStatus||, CODE, READONLY, ALIGN=2

                  DrvSPI_GetLevelTriggerStatus PROC
;;;429      */
;;;430    uint8_t DrvSPI_GetLevelTriggerStatus(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L31.16|
;;;431    {
;;;432    	return (SPI_PORT[eSpiPort]->STATUS_BITS.SBLQ_FLAG?TRUE:FALSE) ;
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6840              LDR      r0,[r0,#4]
000008  06c0              LSLS     r0,r0,#27
00000a  0fc0              LSRS     r0,r0,#31
;;;433    }
00000c  4770              BX       lr
;;;434    
                          ENDP

00000e  0000              DCW      0x0000
                  |L31.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Init||, CODE, READONLY, ALIGN=2

                  DrvSPI_Init PROC
;;;118      
;;;119    void DrvSPI_Init(void)
000000  b510              PUSH     {r4,lr}
;;;120    {
;;;121    	memset(g_sSpiHandler, 0, sizeof(g_sSpiHandler));
000002  213c              MOVS     r1,#0x3c
000004  4805              LDR      r0,|L32.28|
000006  f7fffffe          BL       __aeabi_memclr4
;;;122    	SPI_PORT[0] = SPI0;
00000a  4804              LDR      r0,|L32.28|
00000c  4904              LDR      r1,|L32.32|
00000e  303c              ADDS     r0,r0,#0x3c
;;;123    	SPI_PORT[1] = SPI1;
000010  6001              STR      r1,[r0,#0]  ; SPI_PORT
000012  4904              LDR      r1,|L32.36|
;;;124    	SPI_PORT[2] = SPI2;
000014  6041              STR      r1,[r0,#4]  ; SPI_PORT
000016  4904              LDR      r1,|L32.40|
000018  6081              STR      r1,[r0,#8]  ; SPI_PORT
;;;125    }
00001a  bd10              POP      {r4,pc}
;;;126    
                          ENDP

                  |L32.28|
                          DCD      ||.bss||
                  |L32.32|
                          DCD      0x40030000
                  |L32.36|
                          DCD      0x40130000
                  |L32.40|
                          DCD      0x400d0000

                          AREA ||i.DrvSPI_IsBusy||, CODE, READONLY, ALIGN=2

                  DrvSPI_IsBusy PROC
;;;493      */
;;;494    uint8_t DrvSPI_IsBusy(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L33.16|
;;;495    {
;;;496        return ((SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY)?TRUE:FALSE);
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6800              LDR      r0,[r0,#0]
000008  07c0              LSLS     r0,r0,#31
00000a  0fc0              LSRS     r0,r0,#31
;;;497    }
00000c  4770              BX       lr
;;;498    
                          ENDP

00000e  0000              DCW      0x0000
                  |L33.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_IsRxEmpty||, CODE, READONLY, ALIGN=2

                  DrvSPI_IsRxEmpty PROC
;;;880      */
;;;881    uint8_t DrvSPI_IsRxEmpty(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L34.16|
;;;882    {
;;;883        return ((SPI_PORT[eSpiPort]->STATUS_BITS.RX_EMPTY)?TRUE:FALSE);
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6840              LDR      r0,[r0,#4]
000008  07c0              LSLS     r0,r0,#31
00000a  0fc0              LSRS     r0,r0,#31
;;;884    }
00000c  4770              BX       lr
;;;885    
                          ENDP

00000e  0000              DCW      0x0000
                  |L34.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_IsRxFull||, CODE, READONLY, ALIGN=2

                  DrvSPI_IsRxFull PROC
;;;891      */
;;;892    uint8_t DrvSPI_IsRxFull(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L35.16|
;;;893    {
;;;894        return ((SPI_PORT[eSpiPort]->STATUS_BITS.RX_FULL)?TRUE:FALSE);
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6840              LDR      r0,[r0,#4]
000008  0780              LSLS     r0,r0,#30
00000a  0fc0              LSRS     r0,r0,#31
;;;895    }
00000c  4770              BX       lr
;;;896    
                          ENDP

00000e  0000              DCW      0x0000
                  |L35.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_IsTxEmpty||, CODE, READONLY, ALIGN=2

                  DrvSPI_IsTxEmpty PROC
;;;902      */
;;;903    uint8_t DrvSPI_IsTxEmpty(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L36.16|
;;;904    {
;;;905        return ((SPI_PORT[eSpiPort]->STATUS_BITS.TX_EMPTY)?TRUE:FALSE);
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6840              LDR      r0,[r0,#4]
000008  0740              LSLS     r0,r0,#29
00000a  0fc0              LSRS     r0,r0,#31
;;;906    }
00000c  4770              BX       lr
;;;907    
                          ENDP

00000e  0000              DCW      0x0000
                  |L36.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_IsTxFull||, CODE, READONLY, ALIGN=2

                  DrvSPI_IsTxFull PROC
;;;913      */
;;;914    uint8_t DrvSPI_IsTxFull(E_DRVSPI_PORT eSpiPort)
000000  4903              LDR      r1,|L37.16|
;;;915    {
;;;916        return ((SPI_PORT[eSpiPort]->STATUS_BITS.TX_FULL)?TRUE:FALSE);
000002  0080              LSLS     r0,r0,#2
000004  5808              LDR      r0,[r1,r0]
000006  6840              LDR      r0,[r0,#4]
000008  0700              LSLS     r0,r0,#28
00000a  0fc0              LSRS     r0,r0,#31
;;;917    }
00000c  4770              BX       lr
;;;918    
                          ENDP

00000e  0000              DCW      0x0000
                  |L37.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_Open||, CODE, READONLY, ALIGN=2

                  DrvSPI_Open PROC
;;;181    */
;;;182    int32_t DrvSPI_Open(E_DRVSPI_PORT eSpiPort, E_DRVSPI_MODE eMode, E_DRVSPI_TRANS_TYPE eType, int32_t i32BitLength)
000000  b5f0              PUSH     {r4-r7,lr}
;;;183    {
000002  468c              MOV      r12,r1
;;;184    	int32_t i32TimeOut;
;;;185    	
;;;186    	assert_param(SPI_CHECK_INUSE(eSpiPort));
;;;187                
;;;188        /* Bit length 8 ~ 32 */
;;;189        assert_param(SPI_CHECK_BIT_LENGTH);
;;;190        	
;;;191    	if(eSpiPort == eDRVSPI_PORT0)
;;;192    	{
;;;193    		//enable SPI0 clock
;;;194    		CLK->APBCLK_BITS.SPI0_EN        =1;
;;;195    		
;;;196    		//SPI0 reset
;;;197    		GCR->IPRST_CTL2_BITS.SPI0_RST	=1;
000004  2105              MOVS     r1,#5
000006  4c2b              LDR      r4,|L38.180|
000008  0709              LSLS     r1,r1,#28
00000a  2800              CMP      r0,#0                 ;191
00000c  d004              BEQ      |L38.24|
;;;198    		GCR->IPRST_CTL2_BITS.SPI0_RST	=0;			
;;;199    	}
;;;200    	else if(eSpiPort == eDRVSPI_PORT1)
00000e  2801              CMP      r0,#1
000010  d006              BEQ      |L38.32|
;;;201    	{
;;;202    		//enable SPI1 clock
;;;203    		CLK->APBCLK_BITS.SPI1_EN        =1;
;;;204    		
;;;205    		//SPI1 reset
;;;206    		GCR->IPRST_CTL2_BITS.SPI1_RST	=1;
;;;207    		GCR->IPRST_CTL2_BITS.SPI1_RST	=0;		
;;;208    	}
;;;209    	else if(eSpiPort == eDRVSPI_PORT2)
000012  2802              CMP      r0,#2
000014  d008              BEQ      |L38.40|
000016  e01c              B        |L38.82|
                  |L38.24|
000018  68a6              LDR      r6,[r4,#8]            ;194
00001a  2501              MOVS     r5,#1                 ;194
00001c  032d              LSLS     r5,r5,#12             ;194
00001e  e006              B        |L38.46|
                  |L38.32|
000020  68a6              LDR      r6,[r4,#8]            ;203
000022  2501              MOVS     r5,#1                 ;203
000024  036d              LSLS     r5,r5,#13             ;203
000026  e002              B        |L38.46|
                  |L38.40|
;;;210    	{
;;;211    		//enable SPI1 clock
;;;212    		CLK->APBCLK_BITS.SPI2_EN        =1;
000028  68a6              LDR      r6,[r4,#8]
00002a  2501              MOVS     r5,#1
00002c  03ad              LSLS     r5,r5,#14
                  |L38.46|
00002e  432e              ORRS     r6,r6,r5
000030  60a6              STR      r6,[r4,#8]
;;;213    		
;;;214    		//SPI1 reset
;;;215    		GCR->IPRST_CTL2_BITS.SPI2_RST	=1;
000032  68cc              LDR      r4,[r1,#0xc]
000034  432c              ORRS     r4,r4,r5
000036  60cc              STR      r4,[r1,#0xc]
;;;216    		GCR->IPRST_CTL2_BITS.SPI2_RST	=0;		
000038  68cc              LDR      r4,[r1,#0xc]
00003a  43ac              BICS     r4,r4,r5
00003c  60cc              STR      r4,[r1,#0xc]
;;;217    	}
;;;218    	else	
;;;219    		return 0;
;;;220    			
;;;221    	/* Check busy*/
;;;222    	i32TimeOut = 0x10000;
00003e  2101              MOVS     r1,#1
000040  0409              LSLS     r1,r1,#16
;;;223    	while(SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY == 1)
000042  4f1d              LDR      r7,|L38.184|
000044  0085              LSLS     r5,r0,#2
000046  597c              LDR      r4,[r7,r5]
;;;224    	{
;;;225    		if(i32TimeOut-- <= 0)
;;;226    			return E_DRVSPI_ERR_BUSY;
000048  e005              B        |L38.86|
                  |L38.74|
00004a  460e              MOV      r6,r1                 ;225
00004c  1e49              SUBS     r1,r1,#1              ;225
00004e  2e00              CMP      r6,#0                 ;225
000050  dc01              BGT      |L38.86|
                  |L38.82|
000052  2000              MOVS     r0,#0
;;;227    	}
;;;228    	
;;;229    	g_sSpiHandler[eSpiPort].bBusy = TRUE;
;;;230    	g_sSpiHandler[eSpiPort].pfncallback = NULL;
;;;231    	g_sSpiHandler[eSpiPort].u32userData = 0;
;;;232    	g_sSpiHandler[eSpiPort].pfn3WireStartCallBack = NULL;
;;;233        g_sSpiHandler[eSpiPort].u32ThreeWireStartUserData = 0;
;;;234    		
;;;235    	/* "i32BitLength = 0" means 32 bits */
;;;236    	if(i32BitLength == 32)
;;;237    		i32BitLength = 0;
;;;238    		
;;;239    	SPI_PORT[eSpiPort]->CTL_BITS.TX_BIT_LEN = i32BitLength;
;;;240    	
;;;241    	SPI_PORT[eSpiPort]->CTL_BITS.SLAVE = eMode;
;;;242    
;;;243    	/* Default to automatic slave select and it is low active */
;;;244    	SPI_PORT[eSpiPort]->SSR_BITS.AUTOSS = 1;
;;;245    	
;;;246    	/* Transition types */	
;;;247    	SPI_PORT[eSpiPort]->CTL = (SPI_PORT[eSpiPort]->CTL &~0x806) | eType;
;;;248    	
;;;249        return E_SUCCESS;
;;;250    }
000054  bdf0              POP      {r4-r7,pc}
                  |L38.86|
000056  6826              LDR      r6,[r4,#0]            ;223
000058  07f6              LSLS     r6,r6,#31             ;223
00005a  d1f6              BNE      |L38.74|
00005c  2114              MOVS     r1,#0x14              ;229
00005e  4348              MULS     r0,r1,r0              ;229
000060  4915              LDR      r1,|L38.184|
000062  2601              MOVS     r6,#1                 ;229
000064  393c              SUBS     r1,r1,#0x3c           ;229
000066  540e              STRB     r6,[r1,r0]            ;229
000068  2600              MOVS     r6,#0                 ;230
00006a  1840              ADDS     r0,r0,r1              ;230
00006c  6046              STR      r6,[r0,#4]            ;231
00006e  6086              STR      r6,[r0,#8]            ;232
000070  60c6              STR      r6,[r0,#0xc]          ;233
000072  6106              STR      r6,[r0,#0x10]         ;236
000074  2b20              CMP      r3,#0x20              ;236
000076  d100              BNE      |L38.122|
000078  2300              MOVS     r3,#0                 ;237
                  |L38.122|
00007a  6820              LDR      r0,[r4,#0]            ;239
00007c  21f8              MOVS     r1,#0xf8              ;239
00007e  4388              BICS     r0,r0,r1              ;239
000080  06d9              LSLS     r1,r3,#27             ;239
000082  0e09              LSRS     r1,r1,#24             ;239
000084  4308              ORRS     r0,r0,r1              ;239
000086  6020              STR      r0,[r4,#0]            ;239
000088  5978              LDR      r0,[r7,r5]            ;241
00008a  6801              LDR      r1,[r0,#0]            ;241
00008c  2301              MOVS     r3,#1                 ;241
00008e  049b              LSLS     r3,r3,#18             ;241
000090  4399              BICS     r1,r1,r3              ;241
000092  4663              MOV      r3,r12                ;241
000094  07db              LSLS     r3,r3,#31             ;241
000096  0b5b              LSRS     r3,r3,#13             ;241
000098  4319              ORRS     r1,r1,r3              ;241
00009a  6001              STR      r1,[r0,#0]            ;241
00009c  5978              LDR      r0,[r7,r5]            ;244
00009e  68c1              LDR      r1,[r0,#0xc]          ;244
0000a0  2308              MOVS     r3,#8                 ;244
0000a2  4319              ORRS     r1,r1,r3              ;244
0000a4  60c1              STR      r1,[r0,#0xc]          ;244
0000a6  5978              LDR      r0,[r7,r5]            ;247
0000a8  6801              LDR      r1,[r0,#0]            ;247
0000aa  4b04              LDR      r3,|L38.188|
0000ac  4019              ANDS     r1,r1,r3              ;247
0000ae  4311              ORRS     r1,r1,r2              ;247
0000b0  6001              STR      r1,[r0,#0]            ;247
0000b2  e7ce              B        |L38.82|
;;;251    
                          ENDP

                  |L38.180|
                          DCD      0x50000200
                  |L38.184|
                          DCD      ||.bss||+0x3c
                  |L38.188|
                          DCD      0xfffff7f9

                          AREA ||i.DrvSPI_Set2BitTransferMode||, CODE, READONLY, ALIGN=2

                  DrvSPI_Set2BitTransferMode PROC
;;;305      */
;;;306    void DrvSPI_Set2BitTransferMode(E_DRVSPI_PORT eSpiPort, uint8_t bEnable)
000000  4b06              LDR      r3,|L39.28|
;;;307    {
;;;308    	if(bEnable)
;;;309    		SPI_PORT[eSpiPort]->CTL_BITS.TWOB = 1;
000002  2201              MOVS     r2,#1
000004  0080              LSLS     r0,r0,#2
000006  0592              LSLS     r2,r2,#22
000008  5818              LDR      r0,[r3,r0]
00000a  2900              CMP      r1,#0                 ;308
;;;310    	else
;;;311    		SPI_PORT[eSpiPort]->CTL_BITS.TWOB = 0;
00000c  6801              LDR      r1,[r0,#0]
00000e  d001              BEQ      |L39.20|
000010  4311              ORRS     r1,r1,r2              ;309
000012  e000              B        |L39.22|
                  |L39.20|
000014  4391              BICS     r1,r1,r2
                  |L39.22|
000016  6001              STR      r1,[r0,#0]            ;309
;;;312    }
000018  4770              BX       lr
;;;313    
                          ENDP

00001a  0000              DCW      0x0000
                  |L39.28|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetBitLength||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetBitLength PROC
;;;330      */
;;;331    int32_t DrvSPI_SetBitLength(E_DRVSPI_PORT eSpiPort, int32_t i32BitLength)
000000  2920              CMP      r1,#0x20
;;;332    {
;;;333    	assert_param(SPI_CHECK_BIT_LENGTH);
;;;334       
;;;335        if(i32BitLength == 32)
000002  d100              BNE      |L40.6|
;;;336            i32BitLength = 0;
000004  2100              MOVS     r1,#0
                  |L40.6|
;;;337    
;;;338    	SPI_PORT[eSpiPort]->CTL_BITS.TX_BIT_LEN = i32BitLength;
000006  0082              LSLS     r2,r0,#2
000008  4805              LDR      r0,|L40.32|
00000a  5880              LDR      r0,[r0,r2]
00000c  6802              LDR      r2,[r0,#0]
00000e  23f8              MOVS     r3,#0xf8
000010  06c9              LSLS     r1,r1,#27
000012  439a              BICS     r2,r2,r3
000014  0e09              LSRS     r1,r1,#24
000016  430a              ORRS     r2,r2,r1
000018  6002              STR      r2,[r0,#0]
;;;339    	
;;;340        return E_SUCCESS;
00001a  2000              MOVS     r0,#0
;;;341    }
00001c  4770              BX       lr
;;;342    
                          ENDP

00001e  0000              DCW      0x0000
                  |L40.32|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetByteReorder||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetByteReorder PROC
;;;357      
;;;358    int32_t DrvSPI_SetByteReorder(E_DRVSPI_PORT eSpiPort, E_DRVSPI_BYTE_REORDER eOption)
000000  0082              LSLS     r2,r0,#2
;;;359    {
;;;360    	/* The Byte Suspend function is only available in 32-bit transaction. */
;;;361        if( (eOption==eDRVSPI_BYTE_REORDER_SUSPEND)||(eOption==eDRVSPI_BYTE_SUSPEND) )
;;;362        {	
;;;363        	assert_param(SPI_CHECK_BYTE_REORDER_MIX(eSpiPort));
;;;364        }
;;;365        /* The Byte Reorder function is supported only in 16-, 24- and 32-bit transaction mode. */
;;;366        else if( eOption==eDRVSPI_BYTE_REORDER )    	
;;;367        {
;;;368        	assert_param(SPI_CHECK_BYTE_REORDER(eSpiPort));
;;;369        }
;;;370    
;;;371    	SPI_PORT[eSpiPort]->CTL_BITS.REORDER = eOption;
000002  4806              LDR      r0,|L41.28|
000004  5880              LDR      r0,[r0,r2]
000006  6802              LDR      r2,[r0,#0]
000008  2301              MOVS     r3,#1
00000a  04db              LSLS     r3,r3,#19
00000c  07c9              LSLS     r1,r1,#31
00000e  439a              BICS     r2,r2,r3
000010  0b09              LSRS     r1,r1,#12
000012  430a              ORRS     r2,r2,r1
000014  6002              STR      r2,[r0,#0]
;;;372    	
;;;373    	return E_SUCCESS;
000016  2000              MOVS     r0,#0
;;;374    }
000018  4770              BX       lr
;;;375    
                          ENDP

00001a  0000              DCW      0x0000
                  |L41.28|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetClockFreq||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetClockFreq PROC
;;;506      */
;;;507    uint32_t DrvSPI_SetClockFreq(E_DRVSPI_PORT eSpiPort, uint32_t u32Clock1, uint32_t u32Clock2)
000000  b5f7              PUSH     {r0-r2,r4-r7,lr}
;;;508    {
000002  b082              SUB      sp,sp,#8
000004  4604              MOV      r4,r0
;;;509        uint32_t u32Div;
;;;510        uint32_t u32Pclk, u32CalculatedSpeed=0;
000006  2600              MOVS     r6,#0
;;;511        
;;;512        u32Pclk = DrvSYS_GetHCLKFreq();
000008  f7fffffe          BL       DrvSYS_GetHCLKFreq
;;;513        
;;;514    	if(u32Clock2!=0)
00000c  9000              STR      r0,[sp,#0]
00000e  9804              LDR      r0,[sp,#0x10]
;;;515    	{
;;;516    		u32Div = (((u32Pclk / u32Clock2) + 1) >> 1) - 1;
;;;517    		if(u32Div > 0xFF)
;;;518    		    u32Div = 0xFF;
;;;519    		
;;;520    		u32CalculatedSpeed = u32Pclk / (2*(u32Div+1));
;;;521    		if(u32CalculatedSpeed > u32Clock2)
;;;522    			u32Div ++;
;;;523    			
;;;524    		
;;;525    		SPI_PORT[eSpiPort]->CLKDIV_BITS.DIVIDER2 = u32Div;
000010  4f29              LDR      r7,|L42.184|
000012  00a5              LSLS     r5,r4,#2
000014  2800              CMP      r0,#0                 ;514
000016  d028              BEQ      |L42.106|
000018  4601              MOV      r1,r0                 ;516
00001a  9800              LDR      r0,[sp,#0]            ;516
00001c  f7fffffe          BL       __aeabi_uidivmod
000020  1c40              ADDS     r0,r0,#1              ;516
000022  0844              LSRS     r4,r0,#1              ;516
000024  1e64              SUBS     r4,r4,#1              ;516
000026  2cff              CMP      r4,#0xff              ;517
000028  d900              BLS      |L42.44|
00002a  24ff              MOVS     r4,#0xff              ;518
                  |L42.44|
00002c  0061              LSLS     r1,r4,#1              ;520
00002e  1c89              ADDS     r1,r1,#2              ;520
000030  9800              LDR      r0,[sp,#0]            ;520
000032  f7fffffe          BL       __aeabi_uidivmod
000036  9904              LDR      r1,[sp,#0x10]         ;521
000038  4606              MOV      r6,r0                 ;520
00003a  4288              CMP      r0,r1                 ;521
00003c  d900              BLS      |L42.64|
00003e  1c64              ADDS     r4,r4,#1              ;522
                  |L42.64|
000040  5978              LDR      r0,[r7,r5]
000042  6881              LDR      r1,[r0,#8]
000044  22ff              MOVS     r2,#0xff
000046  0412              LSLS     r2,r2,#16
000048  4391              BICS     r1,r1,r2
00004a  0622              LSLS     r2,r4,#24
00004c  0a12              LSRS     r2,r2,#8
                  |L42.78|
;;;526    	}
;;;527    	else
;;;528    		SPI_PORT[eSpiPort]->CLKDIV_BITS.DIVIDER2 = 0xFF;
00004e  4311              ORRS     r1,r1,r2
000050  6081              STR      r1,[r0,#8]
;;;529    	
;;;530    	if(u32Clock1!=0)
000052  9803              LDR      r0,[sp,#0xc]
000054  2800              CMP      r0,#0
000056  d02a              BEQ      |L42.174|
;;;531    	{
;;;532    		u32Div = ((u32Pclk / u32Clock1) >> 1);
000058  4601              MOV      r1,r0
00005a  9800              LDR      r0,[sp,#0]
00005c  f7fffffe          BL       __aeabi_uidivmod
000060  0844              LSRS     r4,r0,#1
;;;533    		if(u32Div > 0x7F)
000062  2c7f              CMP      r4,#0x7f
000064  d906              BLS      |L42.116|
;;;534    		    u32Div = 0x7F;
000066  247f              MOVS     r4,#0x7f
000068  e006              B        |L42.120|
                  |L42.106|
00006a  5978              LDR      r0,[r7,r5]            ;528
00006c  6881              LDR      r1,[r0,#8]            ;528
00006e  22ff              MOVS     r2,#0xff              ;528
000070  0412              LSLS     r2,r2,#16             ;528
000072  e7ec              B        |L42.78|
                  |L42.116|
;;;535    		
;;;536    		if(u32Div == 0)
000074  2c00              CMP      r4,#0
000076  d018              BEQ      |L42.170|
                  |L42.120|
;;;537    			u32CalculatedSpeed = u32Pclk;
;;;538    		else
;;;539    			u32CalculatedSpeed = u32Pclk / (u32Div << 1);
000078  0061              LSLS     r1,r4,#1
00007a  9800              LDR      r0,[sp,#0]
00007c  f7fffffe          BL       __aeabi_uidivmod
000080  4606              MOV      r6,r0
                  |L42.130|
;;;540    		
;;;541    		if(u32CalculatedSpeed > u32Clock1)
000082  9803              LDR      r0,[sp,#0xc]
000084  4286              CMP      r6,r0
000086  d905              BLS      |L42.148|
;;;542    		{	
;;;543    			u32Div ++;
000088  1c64              ADDS     r4,r4,#1
;;;544    			u32CalculatedSpeed = u32Pclk / (u32Div << 1);
00008a  0061              LSLS     r1,r4,#1
00008c  9800              LDR      r0,[sp,#0]
00008e  f7fffffe          BL       __aeabi_uidivmod
000092  4606              MOV      r6,r0
                  |L42.148|
;;;545    		}
;;;546    		
;;;547    		SPI_PORT[eSpiPort]->CLKDIV_BITS.DIVIDER1 = u32Div;
000094  5978              LDR      r0,[r7,r5]
000096  6881              LDR      r1,[r0,#8]
000098  0662              LSLS     r2,r4,#25
00009a  09c9              LSRS     r1,r1,#7
00009c  01c9              LSLS     r1,r1,#7
00009e  0e52              LSRS     r2,r2,#25
                  |L42.160|
;;;548    	}
;;;549    	else
;;;550    		SPI_PORT[eSpiPort]->CLKDIV_BITS.DIVIDER1 = 0x7F;
0000a0  4311              ORRS     r1,r1,r2
0000a2  6081              STR      r1,[r0,#8]
;;;551    	
;;;552    	return u32CalculatedSpeed;
0000a4  4630              MOV      r0,r6
;;;553    }
0000a6  b005              ADD      sp,sp,#0x14
0000a8  bdf0              POP      {r4-r7,pc}
                  |L42.170|
0000aa  9e00              LDR      r6,[sp,#0]            ;537
0000ac  e7e9              B        |L42.130|
                  |L42.174|
0000ae  5978              LDR      r0,[r7,r5]            ;550
0000b0  6881              LDR      r1,[r0,#8]            ;550
0000b2  227f              MOVS     r2,#0x7f              ;550
0000b4  e7f4              B        |L42.160|
;;;554    
                          ENDP

0000b6  0000              DCW      0x0000
                  |L42.184|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetDualIOMode||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetDualIOMode PROC
;;;1257     */
;;;1258   void DrvSPI_SetDualIOMode(E_DRVSPI_PORT eSpiPort, uint8_t bEnable, uint8_t u8Dir)
000000  b570              PUSH     {r4-r6,lr}
;;;1259   {
;;;1260   	SPI_PORT[eSpiPort]->CTL_BITS.DUAL_IO_EN = bEnable;
000002  4d0a              LDR      r5,|L43.44|
000004  0080              LSLS     r0,r0,#2
000006  582b              LDR      r3,[r5,r0]
000008  681c              LDR      r4,[r3,#0]
00000a  2601              MOVS     r6,#1
00000c  0776              LSLS     r6,r6,#29
00000e  07c9              LSLS     r1,r1,#31
000010  43b4              BICS     r4,r4,r6
000012  0889              LSRS     r1,r1,#2
000014  430c              ORRS     r4,r4,r1
000016  601c              STR      r4,[r3,#0]
;;;1261   	SPI_PORT[eSpiPort]->CTL_BITS.DUAL_IO_DIR = u8Dir;
000018  5828              LDR      r0,[r5,r0]
00001a  6801              LDR      r1,[r0,#0]
00001c  1073              ASRS     r3,r6,#1
00001e  07d2              LSLS     r2,r2,#31
000020  4399              BICS     r1,r1,r3
000022  08d2              LSRS     r2,r2,#3
000024  4311              ORRS     r1,r1,r2
000026  6001              STR      r1,[r0,#0]
;;;1262   }
000028  bd70              POP      {r4-r6,pc}
;;;1263   
                          ENDP

00002a  0000              DCW      0x0000
                  |L43.44|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetEndian||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetEndian PROC
;;;319      */
;;;320    void DrvSPI_SetEndian(E_DRVSPI_PORT eSpiPort, E_DRVSPI_ENDIAN eEndian)
000000  0082              LSLS     r2,r0,#2
;;;321    {	
;;;322    	SPI_PORT[eSpiPort]->CTL_BITS.LSB = eEndian;
000002  4805              LDR      r0,|L44.24|
000004  5880              LDR      r0,[r0,r2]
000006  6802              LDR      r2,[r0,#0]
000008  2301              MOVS     r3,#1
00000a  029b              LSLS     r3,r3,#10
00000c  07c9              LSLS     r1,r1,#31
00000e  439a              BICS     r2,r2,r3
000010  0d49              LSRS     r1,r1,#21
000012  430a              ORRS     r2,r2,r1
000014  6002              STR      r2,[r0,#0]
;;;323    }
000016  4770              BX       lr
;;;324    
                          ENDP

                  |L44.24|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetFIFOMode||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetFIFOMode PROC
;;;866      */
;;;867    int32_t DrvSPI_SetFIFOMode(E_DRVSPI_PORT eSpiPort, uint8_t bEnable, int32_t i32Interval)
000000  b570              PUSH     {r4-r6,lr}
;;;868    {    
;;;869        SPI_PORT[eSpiPort]->CTL_BITS.SP_CYCLE = i32Interval;
000002  4d0b              LDR      r5,|L45.48|
000004  0080              LSLS     r0,r0,#2
000006  582b              LDR      r3,[r5,r0]
000008  681c              LDR      r4,[r3,#0]
00000a  260f              MOVS     r6,#0xf
00000c  0336              LSLS     r6,r6,#12
00000e  0712              LSLS     r2,r2,#28
000010  43b4              BICS     r4,r4,r6
000012  0c12              LSRS     r2,r2,#16
000014  4314              ORRS     r4,r4,r2
000016  601c              STR      r4,[r3,#0]
;;;870        SPI_PORT[eSpiPort]->CTL_BITS.FIFOM = bEnable;
000018  5828              LDR      r0,[r5,r0]
00001a  6802              LDR      r2,[r0,#0]
00001c  2301              MOVS     r3,#1
00001e  055b              LSLS     r3,r3,#21
000020  07c9              LSLS     r1,r1,#31
000022  439a              BICS     r2,r2,r3
000024  0a89              LSRS     r1,r1,#10
000026  430a              ORRS     r2,r2,r1
000028  6002              STR      r2,[r0,#0]
;;;871       
;;;872        return E_SUCCESS;
00002a  2000              MOVS     r0,#0
;;;873    }
00002c  bd70              POP      {r4-r6,pc}
;;;874    
                          ENDP

00002e  0000              DCW      0x0000
                  |L45.48|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetGo||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetGo PROC
;;;731      */
;;;732    void DrvSPI_SetGo(E_DRVSPI_PORT eSpiPort)
000000  0081              LSLS     r1,r0,#2
;;;733    {
;;;734    	SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY = 1;
000002  4803              LDR      r0,|L46.16|
000004  5840              LDR      r0,[r0,r1]
000006  6801              LDR      r1,[r0,#0]
000008  2201              MOVS     r2,#1
00000a  4311              ORRS     r1,r1,r2
00000c  6001              STR      r1,[r0,#0]
;;;735    }
00000e  4770              BX       lr
;;;736    
                          ENDP

                  |L46.16|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetPDMA||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetPDMA PROC
;;;753      */
;;;754    void DrvSPI_SetPDMA(E_DRVSPI_PORT eSpiPort, E_DRVSPI_DMA_MODE eDmaMode, uint8_t bEnable)
000000  4b08              LDR      r3,|L47.36|
;;;755    {
;;;756    	if(eDmaMode==eDRVSPI_TX_DMA)
;;;757    		SPI_PORT[eSpiPort]->PDMA_BITS.TX_DMA_EN = bEnable;
000002  07d2              LSLS     r2,r2,#31
000004  0080              LSLS     r0,r0,#2
000006  0fd2              LSRS     r2,r2,#31
000008  5818              LDR      r0,[r3,r0]
00000a  2900              CMP      r1,#0                 ;756
;;;758    	else
;;;759    		SPI_PORT[eSpiPort]->PDMA_BITS.RX_DMA_EN = bEnable;
00000c  6b81              LDR      r1,[r0,#0x38]
00000e  d005              BEQ      |L47.28|
000010  2302              MOVS     r3,#2
000012  4399              BICS     r1,r1,r3
000014  0052              LSLS     r2,r2,#1
                  |L47.22|
000016  4311              ORRS     r1,r1,r2              ;757
000018  6381              STR      r1,[r0,#0x38]         ;757
;;;760    }
00001a  4770              BX       lr
                  |L47.28|
00001c  0849              LSRS     r1,r1,#1              ;757
00001e  0049              LSLS     r1,r1,#1              ;757
000020  e7f9              B        |L47.22|
;;;761    
                          ENDP

000022  0000              DCW      0x0000
                  |L47.36|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetSS||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetSS PROC
;;;466      */
;;;467    void DrvSPI_SetSS(E_DRVSPI_PORT eSpiPort, E_DRVSPI_SLAVE_SEL eSlaveSel)
000000  0082              LSLS     r2,r0,#2
;;;468    {
;;;469        SPI_PORT[eSpiPort]->SSR_BITS.SSR = eSlaveSel;
000002  4805              LDR      r0,|L48.24|
000004  5880              LDR      r0,[r0,r2]
000006  68c2              LDR      r2,[r0,#0xc]
000008  0789              LSLS     r1,r1,#30
00000a  0892              LSRS     r2,r2,#2
00000c  0092              LSLS     r2,r2,#2
00000e  0f89              LSRS     r1,r1,#30
000010  430a              ORRS     r2,r2,r1
000012  60c2              STR      r2,[r0,#0xc]
;;;470    }
000014  4770              BX       lr
;;;471    
                          ENDP

000016  0000              DCW      0x0000
                  |L48.24|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetSlaveSelectActiveLevel||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetSlaveSelectActiveLevel PROC
;;;416      */
;;;417    void DrvSPI_SetSlaveSelectActiveLevel(E_DRVSPI_PORT eSpiPort, E_DRVSPI_SS_ACT_TYPE eSSActType)
000000  0082              LSLS     r2,r0,#2
;;;418    {
;;;419        SPI_PORT[eSpiPort]->SSR_BITS.SS_LVL = eSSActType;
000002  4805              LDR      r0,|L49.24|
000004  5880              LDR      r0,[r0,r2]
000006  68c2              LDR      r2,[r0,#0xc]
000008  2304              MOVS     r3,#4
00000a  07c9              LSLS     r1,r1,#31
00000c  439a              BICS     r2,r2,r3
00000e  0f49              LSRS     r1,r1,#29
000010  430a              ORRS     r2,r2,r1
000012  60c2              STR      r2,[r0,#0xc]
;;;420    }
000014  4770              BX       lr
;;;421    
                          ENDP

000016  0000              DCW      0x0000
                  |L49.24|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetSuspendCycle||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetSuspendCycle PROC
;;;382      */
;;;383    int32_t DrvSPI_SetSuspendCycle(E_DRVSPI_PORT eSpiPort, int32_t i32Interval)
000000  0082              LSLS     r2,r0,#2
;;;384    {
;;;385        if(SPI_PORT[eSpiPort]->CTL_BITS.FIFOM == 1) 
000002  480c              LDR      r0,|L50.52|
000004  5880              LDR      r0,[r0,r2]
000006  6802              LDR      r2,[r0,#0]
;;;386        	SPI_PORT[eSpiPort]->CTL_BITS.SP_CYCLE = i32Interval;
000008  0309              LSLS     r1,r1,#12
00000a  0293              LSLS     r3,r2,#10             ;385
00000c  220f              MOVS     r2,#0xf
00000e  0312              LSLS     r2,r2,#12
000010  2b00              CMP      r3,#0                 ;385
000012  da05              BGE      |L50.32|
000014  6803              LDR      r3,[r0,#0]
000016  b289              UXTH     r1,r1
000018  4393              BICS     r3,r3,r2
00001a  430b              ORRS     r3,r3,r1
00001c  6003              STR      r3,[r0,#0]
00001e  e007              B        |L50.48|
                  |L50.32|
;;;387        else /* Byte suspend function, it could be 2~17. */
;;;388        {    
;;;389        	assert_param(SPI_CHECK_BYTE_SUS);
;;;390    		SPI_PORT[eSpiPort]->CTL_BITS.SP_CYCLE = i32Interval-2;
000020  2307              MOVS     r3,#7
000022  035b              LSLS     r3,r3,#13
000024  18c9              ADDS     r1,r1,r3
000026  6803              LDR      r3,[r0,#0]
000028  b289              UXTH     r1,r1
00002a  4393              BICS     r3,r3,r2
00002c  4319              ORRS     r1,r1,r3
00002e  6001              STR      r1,[r0,#0]
                  |L50.48|
;;;391    	}
;;;392    
;;;393    	return E_SUCCESS;
000030  2000              MOVS     r0,#0
;;;394    }
000032  4770              BX       lr
;;;395    
                          ENDP

                  |L50.52|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetTriggerMode||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetTriggerMode PROC
;;;401      */
;;;402    void DrvSPI_SetTriggerMode(E_DRVSPI_PORT eSpiPort, E_DRVSPI_SSLTRIG eSSTriggerMode)
000000  0082              LSLS     r2,r0,#2
;;;403    {
;;;404        SPI_PORT[eSpiPort]->SSR_BITS.SS_LTRIG = eSSTriggerMode;
000002  4805              LDR      r0,|L51.24|
000004  5880              LDR      r0,[r0,r2]
000006  68c2              LDR      r2,[r0,#0xc]
000008  2310              MOVS     r3,#0x10
00000a  07c9              LSLS     r1,r1,#31
00000c  439a              BICS     r2,r2,r3
00000e  0ec9              LSRS     r1,r1,#27
000010  430a              ORRS     r2,r2,r1
000012  60c2              STR      r2,[r0,#0xc]
;;;405    }
000014  4770              BX       lr
;;;406    
                          ENDP

000016  0000              DCW      0x0000
                  |L51.24|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetTxRegister||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetTxRegister PROC
;;;714      */
;;;715    uint32_t DrvSPI_SetTxRegister(E_DRVSPI_PORT eSpiPort, uint32_t *pu32Buf, uint32_t u32DataCount)
000000  4603              MOV      r3,r0
;;;716    {
000002  b530              PUSH     {r4,r5,lr}
000004  4610              MOV      r0,r2
;;;717    	assert_param(SPI_CHECK_SET_DATAREG_NUM);
;;;718    	
;;;719    	SPI_PORT[eSpiPort]->TX0 = pu32Buf[0];
000006  4a05              LDR      r2,|L52.28|
000008  009b              LSLS     r3,r3,#2
00000a  58d5              LDR      r5,[r2,r3]
00000c  680c              LDR      r4,[r1,#0]
00000e  622c              STR      r4,[r5,#0x20]
;;;720    	
;;;721    	if(u32DataCount == 2)
000010  2802              CMP      r0,#2
000012  d102              BNE      |L52.26|
;;;722    		SPI_PORT[eSpiPort]->TX1 = pu32Buf[1];
000014  58d2              LDR      r2,[r2,r3]
000016  6849              LDR      r1,[r1,#4]
000018  6251              STR      r1,[r2,#0x24]
                  |L52.26|
;;;723    		
;;;724        return u32DataCount;
;;;725    }
00001a  bd30              POP      {r4,r5,pc}
;;;726    
                          ENDP

                  |L52.28|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SetVariableClockFunction||, CODE, READONLY, ALIGN=2

                  DrvSPI_SetVariableClockFunction PROC
;;;593      */
;;;594    void DrvSPI_SetVariableClockFunction(E_DRVSPI_PORT eSpiPort, uint8_t bEnable, uint32_t u32Pattern)
000000  b570              PUSH     {r4-r6,lr}
;;;595    {
;;;596    	SPI_PORT[eSpiPort]->CTL_BITS.VARCLK_EN = bEnable;
000002  4d07              LDR      r5,|L53.32|
000004  0083              LSLS     r3,r0,#2
000006  58e8              LDR      r0,[r5,r3]
000008  6804              LDR      r4,[r0,#0]
00000a  2601              MOVS     r6,#1
00000c  05f6              LSLS     r6,r6,#23
00000e  07c9              LSLS     r1,r1,#31
000010  43b4              BICS     r4,r4,r6
000012  0a09              LSRS     r1,r1,#8
000014  430c              ORRS     r4,r4,r1
000016  6004              STR      r4,[r0,#0]
;;;597    	SPI_PORT[eSpiPort]->VARCLK = u32Pattern;	
000018  58e8              LDR      r0,[r5,r3]
00001a  6342              STR      r2,[r0,#0x34]
;;;598    }
00001c  bd70              POP      {r4-r6,pc}
;;;599    
                          ENDP

00001e  0000              DCW      0x0000
                  |L53.32|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SingleRead||, CODE, READONLY, ALIGN=2

                  DrvSPI_SingleRead PROC
;;;661      */
;;;662    uint8_t DrvSPI_SingleRead(E_DRVSPI_PORT eSpiPort, uint32_t *pu32Data)
000000  b510              PUSH     {r4,lr}
;;;663    {
;;;664    	if(SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY==1)
000002  4b08              LDR      r3,|L54.36|
000004  0082              LSLS     r2,r0,#2
000006  5898              LDR      r0,[r3,r2]
000008  6804              LDR      r4,[r0,#0]
00000a  07e4              LSLS     r4,r4,#31
00000c  d001              BEQ      |L54.18|
;;;665    		return FALSE;
00000e  2000              MOVS     r0,#0
;;;666    
;;;667    	*pu32Data = SPI_PORT[eSpiPort]->RX0;
;;;668    	SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY = 1;
;;;669    	return TRUE;
;;;670    }
000010  bd10              POP      {r4,pc}
                  |L54.18|
000012  6900              LDR      r0,[r0,#0x10]         ;667
000014  6008              STR      r0,[r1,#0]            ;668
000016  5898              LDR      r0,[r3,r2]            ;668
000018  6801              LDR      r1,[r0,#0]            ;668
00001a  2201              MOVS     r2,#1                 ;668
00001c  4311              ORRS     r1,r1,r2              ;668
00001e  6001              STR      r1,[r0,#0]            ;668
000020  4610              MOV      r0,r2                 ;669
000022  bd10              POP      {r4,pc}
;;;671    
                          ENDP

                  |L54.36|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_SingleWrite||, CODE, READONLY, ALIGN=2

                  DrvSPI_SingleWrite PROC
;;;678      */
;;;679    uint8_t DrvSPI_SingleWrite(E_DRVSPI_PORT eSpiPort, uint32_t *pu32Data)
000000  b510              PUSH     {r4,lr}
;;;680    {
;;;681    	if(SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY==1)
000002  4b08              LDR      r3,|L55.36|
000004  0082              LSLS     r2,r0,#2
000006  5898              LDR      r0,[r3,r2]
000008  6804              LDR      r4,[r0,#0]
00000a  07e4              LSLS     r4,r4,#31
00000c  d001              BEQ      |L55.18|
;;;682    		return FALSE;
00000e  2000              MOVS     r0,#0
;;;683    
;;;684    	SPI_PORT[eSpiPort]->TX0 = *pu32Data;
;;;685    	SPI_PORT[eSpiPort]->CTL_BITS.GO_BUSY = 1;
;;;686    	return TRUE;
;;;687    }
000010  bd10              POP      {r4,pc}
                  |L55.18|
000012  6809              LDR      r1,[r1,#0]            ;684
000014  6201              STR      r1,[r0,#0x20]         ;684
000016  5898              LDR      r0,[r3,r2]            ;685
000018  6801              LDR      r1,[r0,#0]            ;685
00001a  2201              MOVS     r2,#1                 ;685
00001c  4311              ORRS     r1,r1,r2              ;685
00001e  6001              STR      r1,[r0,#0]            ;685
000020  4610              MOV      r0,r2                 ;686
000022  bd10              POP      {r4,pc}
;;;688    
                          ENDP

                  |L55.36|
                          DCD      ||.bss||+0x3c

                          AREA ||i.DrvSPI_WakeupConfigure||, CODE, READONLY, ALIGN=2

                  DrvSPI_WakeupConfigure PROC
;;;853      */
;;;854    void DrvSPI_WakeupConfigure(E_DRVSPI_PORT eSpiPort, uint8_t bEnable)
000000  0082              LSLS     r2,r0,#2
;;;855    {
;;;856    	SPI_PORT[eSpiPort]->CTL_BITS.WKEUP_EN = bEnable;
000002  4804              LDR      r0,|L56.20|
000004  5880              LDR      r0,[r0,r2]
000006  6802              LDR      r2,[r0,#0]
000008  0052              LSLS     r2,r2,#1
00000a  0852              LSRS     r2,r2,#1
00000c  07c9              LSLS     r1,r1,#31
00000e  430a              ORRS     r2,r2,r1
000010  6002              STR      r2,[r0,#0]
;;;857    }
000012  4770              BX       lr
;;;858    
                          ENDP

                  |L56.20|
                          DCD      ||.bss||+0x3c

                          AREA ||i.NVIC_DisableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_DisableIRQ PROC
;;;809     */
;;;810    static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;811    {
;;;812      NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L57.16|
00000a  6008              STR      r0,[r1,#0]
;;;813    }
00000c  4770              BX       lr
;;;814    
                          ENDP

00000e  0000              DCW      0x0000
                  |L57.16|
                          DCD      0xe000e180

                          AREA ||i.SPI0_IRQHandler||, CODE, READONLY, ALIGN=2

                  SPI0_IRQHandler PROC
;;;36       */
;;;37     void SPI0_IRQHandler(void)
000000  b570              PUSH     {r4-r6,lr}
;;;38     {
;;;39     	if( SPI0->STATUS_BITS.INTSTS == 1 ) /* One transaction done interrupt */
000002  4c0d              LDR      r4,|L58.56|
000004  6860              LDR      r0,[r4,#4]
;;;40         {
;;;41     		// write '1' to clear SPI0 interrupt flag
;;;42     		SPI0->STATUS_BITS.INTSTS = 1;
;;;43     		
;;;44     		if(g_sSpiHandler[0].pfncallback != NULL)
000006  4d0d              LDR      r5,|L58.60|
000008  0600              LSLS     r0,r0,#24             ;39
00000a  d508              BPL      |L58.30|
00000c  6860              LDR      r0,[r4,#4]            ;42
00000e  2180              MOVS     r1,#0x80              ;42
000010  4308              ORRS     r0,r0,r1              ;42
000012  6060              STR      r0,[r4,#4]            ;42
000014  6869              LDR      r1,[r5,#4]  ; g_sSpiHandler
000016  2900              CMP      r1,#0
000018  d001              BEQ      |L58.30|
;;;45     			g_sSpiHandler[0].pfncallback(g_sSpiHandler[0].u32userData);	
00001a  68a8              LDR      r0,[r5,#8]  ; g_sSpiHandler
00001c  4788              BLX      r1
                  |L58.30|
;;;46     	}
;;;47     	
;;;48     	if( SPI0->STATUS_BITS.SLV_START_INTSTS == 1 ) /* 3-wire SPI start interrupt */
00001e  6860              LDR      r0,[r4,#4]
000020  0640              LSLS     r0,r0,#25
000022  d508              BPL      |L58.54|
;;;49         {
;;;50             SPI0->STATUS_BITS.SLV_START_INTSTS = 1;   /* write '1' to clear SPI0 3-wire start interrupt flag */
000024  6860              LDR      r0,[r4,#4]
000026  2140              MOVS     r1,#0x40
000028  4308              ORRS     r0,r0,r1
00002a  6060              STR      r0,[r4,#4]
;;;51         
;;;52             if(g_sSpiHandler[0].pfn3WireStartCallBack != NULL)
00002c  68e9              LDR      r1,[r5,#0xc]  ; g_sSpiHandler
00002e  2900              CMP      r1,#0
000030  d001              BEQ      |L58.54|
;;;53             {
;;;54                 g_sSpiHandler[0].pfn3WireStartCallBack(g_sSpiHandler[0].u32ThreeWireStartUserData);
000032  6928              LDR      r0,[r5,#0x10]  ; g_sSpiHandler
000034  4788              BLX      r1
                  |L58.54|
;;;55             }
;;;56         }	
;;;57     }
000036  bd70              POP      {r4-r6,pc}
;;;58     
                          ENDP

                  |L58.56|
                          DCD      0x40030000
                  |L58.60|
                          DCD      ||.bss||

                          AREA ||i.SPI1_IRQHandler||, CODE, READONLY, ALIGN=2

                  SPI1_IRQHandler PROC
;;;63       */
;;;64     void SPI1_IRQHandler(void)
000000  b570              PUSH     {r4-r6,lr}
;;;65     {
;;;66     	if( SPI1->STATUS_BITS.INTSTS == 1 ) /* One transaction done interrupt */
000002  4c0d              LDR      r4,|L59.56|
000004  6860              LDR      r0,[r4,#4]
;;;67         {
;;;68     		// write '1' to clear SPI1 interrupt flag
;;;69     		SPI1->STATUS_BITS.INTSTS = 1;
;;;70     		
;;;71     		if(g_sSpiHandler[1].pfncallback != NULL)
000006  4d0d              LDR      r5,|L59.60|
000008  0600              LSLS     r0,r0,#24             ;66
00000a  d508              BPL      |L59.30|
00000c  6860              LDR      r0,[r4,#4]            ;69
00000e  2180              MOVS     r1,#0x80              ;69
000010  4308              ORRS     r0,r0,r1              ;69
000012  6060              STR      r0,[r4,#4]            ;69
000014  69a9              LDR      r1,[r5,#0x18]  ; g_sSpiHandler
000016  2900              CMP      r1,#0
000018  d001              BEQ      |L59.30|
;;;72     			g_sSpiHandler[1].pfncallback(g_sSpiHandler[1].u32userData);	
00001a  69e8              LDR      r0,[r5,#0x1c]  ; g_sSpiHandler
00001c  4788              BLX      r1
                  |L59.30|
;;;73     	}
;;;74     	
;;;75     	if( SPI1->STATUS_BITS.SLV_START_INTSTS == 1 ) /* 3-wire SPI start interrupt */
00001e  6860              LDR      r0,[r4,#4]
000020  0640              LSLS     r0,r0,#25
000022  d508              BPL      |L59.54|
;;;76         {
;;;77             SPI1->STATUS_BITS.SLV_START_INTSTS = 1;   /* write '1' to clear SPI0 3-wire start interrupt flag */
000024  6860              LDR      r0,[r4,#4]
000026  2140              MOVS     r1,#0x40
000028  4308              ORRS     r0,r0,r1
00002a  6060              STR      r0,[r4,#4]
;;;78         
;;;79             if(g_sSpiHandler[1].pfn3WireStartCallBack != NULL)
00002c  6a29              LDR      r1,[r5,#0x20]  ; g_sSpiHandler
00002e  2900              CMP      r1,#0
000030  d001              BEQ      |L59.54|
;;;80             {
;;;81                 g_sSpiHandler[1].pfn3WireStartCallBack(g_sSpiHandler[1].u32ThreeWireStartUserData);
000032  6a68              LDR      r0,[r5,#0x24]  ; g_sSpiHandler
000034  4788              BLX      r1
                  |L59.54|
;;;82             }
;;;83         }	
;;;84     }
000036  bd70              POP      {r4-r6,pc}
;;;85     
                          ENDP

                  |L59.56|
                          DCD      0x40130000
                  |L59.60|
                          DCD      ||.bss||

                          AREA ||i.SPI2_IRQHandler||, CODE, READONLY, ALIGN=2

                  SPI2_IRQHandler PROC
;;;90       */
;;;91     void SPI2_IRQHandler(void)
000000  b570              PUSH     {r4-r6,lr}
;;;92     {
;;;93     	if( SPI2->STATUS_BITS.INTSTS == 1 ) /* One transaction done interrupt */
000002  4c0d              LDR      r4,|L60.56|
000004  6860              LDR      r0,[r4,#4]
;;;94         {    	
;;;95     		// write '1' to clear SPI2 interrupt flag
;;;96     		SPI2->STATUS_BITS.INTSTS = 1;
;;;97     		
;;;98     		if(g_sSpiHandler[2].pfncallback != NULL)
000006  4d0d              LDR      r5,|L60.60|
000008  0600              LSLS     r0,r0,#24             ;93
00000a  d508              BPL      |L60.30|
00000c  6860              LDR      r0,[r4,#4]            ;96
00000e  2180              MOVS     r1,#0x80              ;96
000010  4308              ORRS     r0,r0,r1              ;96
000012  6060              STR      r0,[r4,#4]            ;96
000014  6ae9              LDR      r1,[r5,#0x2c]  ; g_sSpiHandler
000016  2900              CMP      r1,#0
000018  d001              BEQ      |L60.30|
;;;99     			g_sSpiHandler[2].pfncallback(g_sSpiHandler[2].u32userData);
00001a  6b28              LDR      r0,[r5,#0x30]  ; g_sSpiHandler
00001c  4788              BLX      r1
                  |L60.30|
;;;100    	}
;;;101    	
;;;102    	if( SPI2->STATUS_BITS.SLV_START_INTSTS == 1 ) /* 3-wire SPI start interrupt */
00001e  6860              LDR      r0,[r4,#4]
000020  0640              LSLS     r0,r0,#25
000022  d508              BPL      |L60.54|
;;;103        {
;;;104            SPI2->STATUS_BITS.SLV_START_INTSTS = 1;   /* write '1' to clear SPI0 3-wire start interrupt flag */
000024  6860              LDR      r0,[r4,#4]
000026  2140              MOVS     r1,#0x40
000028  4308              ORRS     r0,r0,r1
00002a  6060              STR      r0,[r4,#4]
;;;105        
;;;106            if(g_sSpiHandler[2].pfn3WireStartCallBack != NULL)
00002c  6b69              LDR      r1,[r5,#0x34]  ; g_sSpiHandler
00002e  2900              CMP      r1,#0
000030  d001              BEQ      |L60.54|
;;;107            {
;;;108                g_sSpiHandler[2].pfn3WireStartCallBack(g_sSpiHandler[2].u32ThreeWireStartUserData);
000032  6ba8              LDR      r0,[r5,#0x38]  ; g_sSpiHandler
000034  4788              BLX      r1
                  |L60.54|
;;;109            }
;;;110        }
;;;111    }
000036  bd70              POP      {r4-r6,pc}
;;;112    
                          ENDP

                  |L60.56|
                          DCD      0x400d0000
                  |L60.60|
                          DCD      ||.bss||

                          AREA ||.bss||, DATA, NOINIT, ALIGN=2

                  g_sSpiHandler
                          %        60
                  SPI_PORT
                          %        12
