; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\drvtk.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\drvtk.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\drvtk.crf ..\bsp\Driver\DrvTK.c]
                          THUMB

                          AREA ||i.DrvTK_CheckBusyComplete||, CODE, READONLY, ALIGN=2

                  DrvTK_CheckBusyComplete PROC
;;;322      */
;;;323    int32_t DrvTK_CheckBusyComplete(uint8_t *pu8Busy, uint8_t *pu8Complete)
000000  4a07              LDR      r2,|L1.32|
;;;324    {
;;;325    	assert_param(!(pu8Busy == NULL && pu8Complete == NULL));
;;;326    
;;;327    	if(pu8Busy != NULL)	
000002  2800              CMP      r0,#0
000004  d003              BEQ      |L1.14|
;;;328    		*pu8Busy = (uint8_t)(TK->STAT & 1);
000006  68d3              LDR      r3,[r2,#0xc]
000008  07db              LSLS     r3,r3,#31
00000a  0fdb              LSRS     r3,r3,#31
00000c  7003              STRB     r3,[r0,#0]
                  |L1.14|
;;;329    	if(pu8Complete != NULL)	
00000e  2900              CMP      r1,#0
000010  d003              BEQ      |L1.26|
;;;330    		*pu8Complete = (uint8_t)(TK->STAT & 0x2) >> 1;
000012  68d0              LDR      r0,[r2,#0xc]
000014  0780              LSLS     r0,r0,#30
000016  0fc0              LSRS     r0,r0,#31
000018  7008              STRB     r0,[r1,#0]
                  |L1.26|
;;;331    
;;;332    	return(0);
00001a  2000              MOVS     r0,#0
;;;333    
;;;334    }
00001c  4770              BX       lr
;;;335    
                          ENDP

00001e  0000              DCW      0x0000
                  |L1.32|
                          DCD      0x400c0000

                          AREA ||i.DrvTK_Close||, CODE, READONLY, ALIGN=2

                  DrvTK_Close PROC
;;;51       */
;;;52     int32_t DrvTK_Close(void)
000000  490c              LDR      r1,|L2.52|
;;;53     {
;;;54     	if(tk_opened == 1) {
000002  7808              LDRB     r0,[r1,#0]  ; tk_opened
000004  2801              CMP      r0,#1
000006  d001              BEQ      |L2.12|
;;;55     		TK->CTL1 &= ~0xFF00;		
;;;56     		TK->CTL1_BITS.EN = 0;	
;;;57     		tk_opened = 0;
;;;58     		CLK->APBCLK_BITS.TK_EN = 0;
;;;59     
;;;60     	} else
;;;61     		return(E_DRVTK_ALREADY);
000008  480b              LDR      r0,|L2.56|
;;;62     	//TK_DisableInterrupt();  //XXX: disable?
;;;63     	tk_opened = 0;
;;;64     
;;;65     	return(0);
;;;66     }
00000a  4770              BX       lr
                  |L2.12|
00000c  480b              LDR      r0,|L2.60|
00000e  6802              LDR      r2,[r0,#0]            ;55
000010  23ff              MOVS     r3,#0xff              ;55
000012  021b              LSLS     r3,r3,#8              ;55
000014  439a              BICS     r2,r2,r3              ;55
000016  6002              STR      r2,[r0,#0]            ;55
000018  6802              LDR      r2,[r0,#0]            ;56
00001a  0052              LSLS     r2,r2,#1              ;56
00001c  0852              LSRS     r2,r2,#1              ;56
00001e  6002              STR      r2,[r0,#0]            ;56
000020  2000              MOVS     r0,#0                 ;57
000022  7008              STRB     r0,[r1,#0]            ;57
000024  4806              LDR      r0,|L2.64|
000026  6881              LDR      r1,[r0,#8]            ;58
000028  03c2              LSLS     r2,r0,#15             ;58
00002a  4391              BICS     r1,r1,r2              ;58
00002c  6081              STR      r1,[r0,#8]            ;58
00002e  2000              MOVS     r0,#0                 ;65
000030  4770              BX       lr
;;;67     
                          ENDP

000032  0000              DCW      0x0000
                  |L2.52|
                          DCD      ||.data||
                  |L2.56|
                          DCD      0xffffa481
                  |L2.60|
                          DCD      0x400c0000
                  |L2.64|
                          DCD      0x50000200

                          AREA ||i.DrvTK_ConfigChannel||, CODE, READONLY, ALIGN=2

                  DrvTK_ConfigChannel PROC
;;;96       */
;;;97     int32_t DrvTK_ConfigChannel(uint8_t ch, S_TK_CH_CFG *cfg)
000000  b5f8              PUSH     {r3-r7,lr}
;;;98     {
;;;99     	uint32_t i;
;;;100    	
;;;101    	assert_param(cfg != NULL);
;;;102    	assert_param(ch < TK_MAX_CH);
;;;103    	assert_param(tk_opened == 1);
;;;104    		
;;;105    	if(TK->STAT_BITS.BUSY == 1)
000002  4d11              LDR      r5,|L3.72|
000004  68ea              LDR      r2,[r5,#0xc]
000006  07d2              LSLS     r2,r2,#31
000008  d001              BEQ      |L3.14|
;;;106    		return(E_DRVTK_BUSY);
00000a  4810              LDR      r0,|L3.76|
;;;107    
;;;108    	ch = ch & 0x7;
;;;109    	
;;;110    	i = *(unsigned int volatile *)(TK_BASE + 0x4 + 4 * (ch >> 2));
;;;111    	i &= ~(0xff << (8 *(ch & 0x3)));
;;;112    	i |= ((cfg->eLevel << 4) | (cfg->u8Div)) << (8 *(ch & 0x3));
;;;113    	*(unsigned int volatile *)(TK_BASE + 0x4 + 4 * (ch >> 2)) = i;
;;;114    	
;;;115    	*(unsigned int volatile *)(TK_BASE + 0x24 + 4 * ch) = (cfg->high_th << 16) | (cfg->low_th);
;;;116    	
;;;117    	return(0);
;;;118    }
00000c  bdf8              POP      {r3-r7,pc}
                  |L3.14|
00000e  0744              LSLS     r4,r0,#29             ;108
000010  0f64              LSRS     r4,r4,#29             ;108
000012  08a0              LSRS     r0,r4,#2              ;110
000014  0080              LSLS     r0,r0,#2              ;110
000016  1943              ADDS     r3,r0,r5              ;110
000018  685a              LDR      r2,[r3,#4]            ;110
00001a  07a0              LSLS     r0,r4,#30             ;111
00001c  0ec0              LSRS     r0,r0,#27             ;111
00001e  26ff              MOVS     r6,#0xff              ;111
000020  4086              LSLS     r6,r6,r0              ;111
000022  43b2              BICS     r2,r2,r6              ;111
000024  780e              LDRB     r6,[r1,#0]            ;112
000026  784f              LDRB     r7,[r1,#1]            ;112
000028  0136              LSLS     r6,r6,#4              ;112
00002a  433e              ORRS     r6,r6,r7              ;112
00002c  4086              LSLS     r6,r6,r0              ;112
00002e  4316              ORRS     r6,r6,r2              ;112
000030  605e              STR      r6,[r3,#4]            ;113
000032  1c88              ADDS     r0,r1,#2              ;115
000034  f7fffffe          BL       __aeabi_uread4
000038  2110              MOVS     r1,#0x10              ;115
00003a  41c8              RORS     r0,r0,r1              ;115
00003c  00a1              LSLS     r1,r4,#2              ;115
00003e  1949              ADDS     r1,r1,r5              ;115
000040  6248              STR      r0,[r1,#0x24]         ;115
000042  2000              MOVS     r0,#0                 ;117
000044  bdf8              POP      {r3-r7,pc}
;;;119    
                          ENDP

000046  0000              DCW      0x0000
                  |L3.72|
                          DCD      0x400c0000
                  |L3.76|
                          DCD      0xffffa484

                          AREA ||i.DrvTK_DisableInterrupt||, CODE, READONLY, ALIGN=2

                  DrvTK_DisableInterrupt PROC
;;;220      */
;;;221    int32_t DrvTK_DisableInterrupt(uint32_t mask)
000000  4909              LDR      r1,|L4.40|
;;;222    {
;;;223      	
;;;224    	assert_param(mask & 0x7 != 0);
;;;225    
;;;226    	if(TK->STAT_BITS.BUSY == 1)
000002  68ca              LDR      r2,[r1,#0xc]
000004  07d2              LSLS     r2,r2,#31
000006  d001              BEQ      |L4.12|
;;;227    		return(E_DRVTK_BUSY);
000008  4808              LDR      r0,|L4.44|
;;;228    
;;;229    	TK->INTEN &= ~(mask & 7);
;;;230    
;;;231    	if(TK->INTEN == 0) {
;;;232    
;;;233    		NVIC_DisableIRQ(TK_IRQn);
;;;234    	} 
;;;235    
;;;236    	return(0);
;;;237    }
00000a  4770              BX       lr
                  |L4.12|
00000c  6a0a              LDR      r2,[r1,#0x20]         ;229
00000e  0740              LSLS     r0,r0,#29             ;229
000010  0f40              LSRS     r0,r0,#29             ;229
000012  4382              BICS     r2,r2,r0              ;229
000014  620a              STR      r2,[r1,#0x20]         ;229
000016  6a08              LDR      r0,[r1,#0x20]         ;231
000018  2800              CMP      r0,#0                 ;231
00001a  d103              BNE      |L4.36|
00001c  2001              MOVS     r0,#1                 ;231
00001e  4904              LDR      r1,|L4.48|
000020  0600              LSLS     r0,r0,#24             ;231
000022  6008              STR      r0,[r1,#0]            ;231
                  |L4.36|
000024  2000              MOVS     r0,#0                 ;236
000026  4770              BX       lr
;;;238    
                          ENDP

                  |L4.40|
                          DCD      0x400c0000
                  |L4.44|
                          DCD      0xffffa484
                  |L4.48|
                          DCD      0xe000e180

                          AREA ||i.DrvTK_EnableInterrupt||, CODE, READONLY, ALIGN=2

                  DrvTK_EnableInterrupt PROC
;;;197      */
;;;198    int32_t DrvTK_EnableInterrupt(uint32_t mask)
000000  4908              LDR      r1,|L5.36|
;;;199    {
;;;200    	assert_param(mask & 0x7 != 0);
;;;201    
;;;202    	if(TK->STAT_BITS.BUSY == 1)
000002  68ca              LDR      r2,[r1,#0xc]
000004  07d2              LSLS     r2,r2,#31
000006  d001              BEQ      |L5.12|
;;;203    		return(E_DRVTK_BUSY);
000008  4807              LDR      r0,|L5.40|
;;;204    		
;;;205    	// Clear pending interrupt status.
;;;206    	TK->STAT = TK->STAT;
;;;207    	TK->INTEN = mask & 7;
;;;208    
;;;209    	NVIC_EnableIRQ(TK_IRQn);
;;;210    	
;;;211    	return(0);
;;;212    }
00000a  4770              BX       lr
                  |L5.12|
00000c  68ca              LDR      r2,[r1,#0xc]          ;206
00000e  60ca              STR      r2,[r1,#0xc]          ;206
000010  0740              LSLS     r0,r0,#29             ;207
000012  0f40              LSRS     r0,r0,#29             ;207
000014  6208              STR      r0,[r1,#0x20]         ;207
000016  2001              MOVS     r0,#1                 ;207
000018  4904              LDR      r1,|L5.44|
00001a  0600              LSLS     r0,r0,#24             ;207
00001c  6008              STR      r0,[r1,#0]            ;207
00001e  2000              MOVS     r0,#0                 ;211
000020  4770              BX       lr
;;;213    
                          ENDP

000022  0000              DCW      0x0000
                  |L5.36|
                          DCD      0x400c0000
                  |L5.40|
                          DCD      0xffffa484
                  |L5.44|
                          DCD      0xe000e100

                          AREA ||i.DrvTK_GetVersion||, CODE, READONLY, ALIGN=1

                  DrvTK_GetVersion PROC
;;;340      */
;;;341    uint32_t DrvTK_GetVersion (void)
000000  2001              MOVS     r0,#1
;;;342    {
;;;343    	return DRVTK_VERSION_NUM;
000002  0400              LSLS     r0,r0,#16
;;;344    }
000004  4770              BX       lr
;;;345    
                          ENDP


                          AREA ||i.DrvTK_Open||, CODE, READONLY, ALIGN=2

                  DrvTK_Open PROC
;;;26       */
;;;27     int32_t DrvTK_Open(S_TK_COMM_CFG *cfg)
000000  b570              PUSH     {r4-r6,lr}
;;;28     {		
;;;29      	assert_param(cfg != NULL);
;;;30     
;;;31     	if(tk_opened == 0) {
000002  4e14              LDR      r6,|L7.84|
000004  4605              MOV      r5,r0                 ;28
000006  7830              LDRB     r0,[r6,#0]  ; tk_opened
000008  2800              CMP      r0,#0
00000a  d001              BEQ      |L7.16|
;;;32     		CLK->APBCLK_BITS.TK_EN = 1;
;;;33     		TK->CTL1_BITS.EN = 1;
;;;34     		TK->CTL1_BITS.SEN_SEL = cfg->eWidth;
;;;35     		DrvTK_SetExtCap(cfg->u8Cap);
;;;36     		TK->CTL1_BITS.START_BY_TMR = cfg->tmr_trigger;
;;;37     		tk_opened = 1;
;;;38     	} else
;;;39     		return(E_DRVTK_ALREADY);
00000c  4812              LDR      r0,|L7.88|
;;;40     
;;;41     	return(0);
;;;42     }
00000e  bd70              POP      {r4-r6,pc}
                  |L7.16|
000010  4812              LDR      r0,|L7.92|
000012  6881              LDR      r1,[r0,#8]            ;32
000014  03c2              LSLS     r2,r0,#15             ;32
000016  4311              ORRS     r1,r1,r2              ;32
000018  6081              STR      r1,[r0,#8]            ;32
00001a  4c11              LDR      r4,|L7.96|
00001c  6820              LDR      r0,[r4,#0]            ;33
00001e  01d1              LSLS     r1,r2,#7              ;33
000020  4308              ORRS     r0,r0,r1              ;33
000022  6020              STR      r0,[r4,#0]            ;33
000024  6820              LDR      r0,[r4,#0]            ;34
000026  02e1              LSLS     r1,r4,#11             ;34
000028  4388              BICS     r0,r0,r1              ;34
00002a  7829              LDRB     r1,[r5,#0]            ;34
00002c  0789              LSLS     r1,r1,#30             ;34
00002e  0849              LSRS     r1,r1,#1              ;34
000030  4308              ORRS     r0,r0,r1              ;34
000032  6020              STR      r0,[r4,#0]            ;34
000034  78a8              LDRB     r0,[r5,#2]            ;35
000036  f7fffffe          BL       DrvTK_SetExtCap
00003a  6820              LDR      r0,[r4,#0]            ;36
00003c  2101              MOVS     r1,#1                 ;36
00003e  0449              LSLS     r1,r1,#17             ;36
000040  4388              BICS     r0,r0,r1              ;36
000042  7869              LDRB     r1,[r5,#1]            ;36
000044  07c9              LSLS     r1,r1,#31             ;36
000046  0b89              LSRS     r1,r1,#14             ;36
000048  4308              ORRS     r0,r0,r1              ;36
00004a  6020              STR      r0,[r4,#0]            ;36
00004c  2001              MOVS     r0,#1                 ;37
00004e  7030              STRB     r0,[r6,#0]            ;37
000050  2000              MOVS     r0,#0                 ;41
000052  bd70              POP      {r4-r6,pc}
;;;43     
                          ENDP

                  |L7.84|
                          DCD      ||.data||
                  |L7.88|
                          DCD      0xffffa481
                  |L7.92|
                          DCD      0x50000200
                  |L7.96|
                          DCD      0x400c0000

                          AREA ||i.DrvTK_ReadData||, CODE, READONLY, ALIGN=2

                  DrvTK_ReadData PROC
;;;266      */
;;;267    int32_t DrvTK_ReadData(uint8_t ch, uint16_t *pu16Data)
000000  4a09              LDR      r2,|L8.40|
;;;268    {	
;;;269    	assert_param(pu16Data != NULL);
;;;270    	assert_param(ch < TK_CH_NUM);
;;;271    
;;;272    	if(TK->STAT_BITS.BUSY == 1)
000002  68d2              LDR      r2,[r2,#0xc]
000004  07d2              LSLS     r2,r2,#31
000006  d001              BEQ      |L8.12|
;;;273    		return(E_DRVTK_BUSY);
000008  4808              LDR      r0,|L8.44|
;;;274    
;;;275    		
;;;276    	if(ch & 1) {
;;;277    		*pu16Data = (uint16_t)(*(unsigned int volatile *)(TK_BASE + 0x10 + 4 * ((ch & 0x7) >> 1))  >> 16);
;;;278    	} else {
;;;279    		*pu16Data = (uint16_t)(*(unsigned int volatile *)(TK_BASE + 0x10 + 4 * ((ch & 0x7) >> 1)) & 0xffff);
;;;280    	}
;;;281    	
;;;282    	return(0);
;;;283    
;;;284    }
00000a  4770              BX       lr
                  |L8.12|
00000c  07c2              LSLS     r2,r0,#31             ;276
00000e  0740              LSLS     r0,r0,#29             ;277
000010  0f80              LSRS     r0,r0,#30             ;277
000012  4b05              LDR      r3,|L8.40|
000014  0080              LSLS     r0,r0,#2              ;277
000016  18c0              ADDS     r0,r0,r3              ;277
000018  6900              LDR      r0,[r0,#0x10]         ;279
00001a  2a00              CMP      r2,#0                 ;276
00001c  d000              BEQ      |L8.32|
00001e  0c00              LSRS     r0,r0,#16             ;277
                  |L8.32|
000020  8008              STRH     r0,[r1,#0]            ;279
000022  2000              MOVS     r0,#0                 ;282
000024  4770              BX       lr
;;;285    
                          ENDP

000026  0000              DCW      0x0000
                  |L8.40|
                          DCD      0x400c0000
                  |L8.44|
                          DCD      0xffffa484

                          AREA ||i.DrvTK_ReadStatus||, CODE, READONLY, ALIGN=2

                  DrvTK_ReadStatus PROC
;;;296      */
;;;297    int32_t DrvTK_ReadStatus(uint8_t *pu8Level, uint8_t *pu8State, uint8_t *pu8Th)
000000  b510              PUSH     {r4,lr}
;;;298    {
;;;299    	assert_param(!(pu8Level == NULL && pu8State == NULL && pu8Th == NULL));
;;;300    
;;;301    	if(pu8Level != NULL)	
;;;302    		*pu8Level = (uint8_t)((TK->STAT & 0xFF) >> 4);
000002  4b09              LDR      r3,|L9.40|
000004  2800              CMP      r0,#0                 ;301
000006  d003              BEQ      |L9.16|
000008  68dc              LDR      r4,[r3,#0xc]
00000a  0624              LSLS     r4,r4,#24
00000c  0f24              LSRS     r4,r4,#28
00000e  7004              STRB     r4,[r0,#0]
                  |L9.16|
;;;303    	if(pu8State != NULL)	
000010  2900              CMP      r1,#0
000012  d002              BEQ      |L9.26|
;;;304    		*pu8State = (uint8_t)((TK->STAT & 0xFF00) >> 8);
000014  68d8              LDR      r0,[r3,#0xc]
000016  0a00              LSRS     r0,r0,#8
000018  7008              STRB     r0,[r1,#0]
                  |L9.26|
;;;305    	if(pu8Th != NULL)	
00001a  2a00              CMP      r2,#0
00001c  d002              BEQ      |L9.36|
;;;306    		*pu8Th = (uint8_t)((TK->STAT & 0xFF0000) >> 16);
00001e  68d8              LDR      r0,[r3,#0xc]
000020  0c00              LSRS     r0,r0,#16
000022  7010              STRB     r0,[r2,#0]
                  |L9.36|
;;;307    	
;;;308    	return(0);
000024  2000              MOVS     r0,#0
;;;309    
;;;310    }
000026  bd10              POP      {r4,pc}
;;;311    
                          ENDP

                  |L9.40|
                          DCD      0x400c0000

                          AREA ||i.DrvTK_RegisterCallback||, CODE, READONLY, ALIGN=2

                  DrvTK_RegisterCallback PROC
;;;248      */
;;;249    int32_t DrvTK_RegisterCallback(PFN_TK_CALLBACK pfnFp, uint32_t u32Param)
000000  4a05              LDR      r2,|L10.24|
;;;250    {
;;;251    	if(TK->STAT_BITS.BUSY == 1)
000002  68d2              LDR      r2,[r2,#0xc]
000004  07d2              LSLS     r2,r2,#31
000006  d001              BEQ      |L10.12|
;;;252    		return(E_DRVTK_BUSY);
000008  4804              LDR      r0,|L10.28|
;;;253    		
;;;254        callback = pfnFp;
;;;255    	data = u32Param;
;;;256        return(0);
;;;257    }
00000a  4770              BX       lr
                  |L10.12|
00000c  4a04              LDR      r2,|L10.32|
00000e  6091              STR      r1,[r2,#8]            ;256  ; data
000010  6050              STR      r0,[r2,#4]            ;256  ; callback
000012  2000              MOVS     r0,#0                 ;256
000014  4770              BX       lr
;;;258    
                          ENDP

000016  0000              DCW      0x0000
                  |L10.24|
                          DCD      0x400c0000
                  |L10.28|
                          DCD      0xffffa484
                  |L10.32|
                          DCD      ||.data||

                          AREA ||i.DrvTK_Reset||, CODE, READONLY, ALIGN=2

                  DrvTK_Reset PROC
;;;73       */
;;;74     void DrvTK_Reset(void)
000000  2205              MOVS     r2,#5
;;;75     {
;;;76     	uint16_t volatile i;
;;;77     
;;;78     	GCR->IPRST_CTL2_BITS.TK_RST = 1;
000002  0712              LSLS     r2,r2,#28
000004  68d0              LDR      r0,[r2,#0xc]
000006  2301              MOVS     r3,#1
000008  061b              LSLS     r3,r3,#24
00000a  4318              ORRS     r0,r0,r3
00000c  60d0              STR      r0,[r2,#0xc]
;;;79     	for(i = 0; i < 0x1000; i++);
00000e  2000              MOVS     r0,#0
000010  1319              ASRS     r1,r3,#12
                  |L11.18|
000012  1c40              ADDS     r0,r0,#1
000014  b280              UXTH     r0,r0
000016  4288              CMP      r0,r1
000018  d3fb              BCC      |L11.18|
;;;80     	GCR->IPRST_CTL2_BITS.TK_RST = 0;
00001a  68d0              LDR      r0,[r2,#0xc]
00001c  4398              BICS     r0,r0,r3
00001e  60d0              STR      r0,[r2,#0xc]
;;;81     
;;;82     	callback = NULL;
000020  4802              LDR      r0,|L11.44|
000022  2100              MOVS     r1,#0
;;;83     	data = 0;	
000024  6041              STR      r1,[r0,#4]  ; callback
000026  6081              STR      r1,[r0,#8]  ; data
;;;84     
;;;85     	return;
;;;86     }
000028  4770              BX       lr
;;;87     
                          ENDP

00002a  0000              DCW      0x0000
                  |L11.44|
                          DCD      ||.data||

                          AREA ||i.DrvTK_SetExtCap||, CODE, READONLY, ALIGN=2

                  DrvTK_SetExtCap PROC
;;;155      */
;;;156    int32_t DrvTK_SetExtCap(uint8_t u8Cap)
000000  4907              LDR      r1,|L12.32|
;;;157    {
;;;158    	if(TK->STAT_BITS.BUSY == 1)
000002  68ca              LDR      r2,[r1,#0xc]
000004  07d2              LSLS     r2,r2,#31
000006  d001              BEQ      |L12.12|
;;;159    		return(E_DRVTK_BUSY);
000008  4806              LDR      r0,|L12.36|
;;;160    	
;;;161    	TK->CTL1_BITS.EXT_CAP_EN = u8Cap;
;;;162    
;;;163    	
;;;164    	return(0);
;;;165    
;;;166    
;;;167    }
00000a  4770              BX       lr
                  |L12.12|
00000c  680a              LDR      r2,[r1,#0]            ;161
00000e  2301              MOVS     r3,#1                 ;161
000010  061b              LSLS     r3,r3,#24             ;161
000012  07c0              LSLS     r0,r0,#31             ;161
000014  439a              BICS     r2,r2,r3              ;161
000016  09c0              LSRS     r0,r0,#7              ;161
000018  4302              ORRS     r2,r2,r0              ;161
00001a  600a              STR      r2,[r1,#0]            ;161
00001c  2000              MOVS     r0,#0                 ;164
00001e  4770              BX       lr
;;;168    
                          ENDP

                  |L12.32|
                          DCD      0x400c0000
                  |L12.36|
                          DCD      0xffffa484

                          AREA ||i.DrvTK_SetTmrTrigger||, CODE, READONLY, ALIGN=2

                  DrvTK_SetTmrTrigger PROC
;;;175      */
;;;176    int32_t DrvTK_SetTmrTrigger(uint8_t enable)
000000  4907              LDR      r1,|L13.32|
;;;177    {
;;;178    	assert_param(tk_opened == 1);
;;;179    
;;;180    	if(TK->STAT_BITS.BUSY == 1)
000002  68ca              LDR      r2,[r1,#0xc]
000004  07d2              LSLS     r2,r2,#31
000006  d001              BEQ      |L13.12|
;;;181    		return(E_DRVTK_BUSY);
000008  4806              LDR      r0,|L13.36|
;;;182    
;;;183    
;;;184    	TK->CTL1_BITS.START_BY_TMR = enable;
;;;185    
;;;186    	
;;;187    	return(0);
;;;188    }
00000a  4770              BX       lr
                  |L13.12|
00000c  680a              LDR      r2,[r1,#0]            ;184
00000e  2301              MOVS     r3,#1                 ;184
000010  045b              LSLS     r3,r3,#17             ;184
000012  07c0              LSLS     r0,r0,#31             ;184
000014  439a              BICS     r2,r2,r3              ;184
000016  0b80              LSRS     r0,r0,#14             ;184
000018  4302              ORRS     r2,r2,r0              ;184
00001a  600a              STR      r2,[r1,#0]            ;184
00001c  2000              MOVS     r0,#0                 ;187
00001e  4770              BX       lr
;;;189    
                          ENDP

                  |L13.32|
                          DCD      0x400c0000
                  |L13.36|
                          DCD      0xffffa484

                          AREA ||i.DrvTK_Start||, CODE, READONLY, ALIGN=2

                  DrvTK_Start PROC
;;;127      */
;;;128    int32_t DrvTK_Start(uint16_t mask)
000000  b510              PUSH     {r4,lr}
;;;129    {
;;;130    //	uint16_t i = (mask & 0xff) | (mask >> 8);	
;;;131    
;;;132        assert_param(mask != 0);
;;;133    	assert_param(((mask & 0xff) & (mask >> 8)) == 0);	// check mutual exclusive
;;;134    	assert_param(tk_opened == 1);
;;;135    	
;;;136    	if(TK->STAT_BITS.BUSY == 1)
000002  490f              LDR      r1,|L14.64|
000004  68ca              LDR      r2,[r1,#0xc]
000006  07d2              LSLS     r2,r2,#31
000008  d001              BEQ      |L14.14|
;;;137    		return(E_DRVTK_BUSY);
00000a  480e              LDR      r0,|L14.68|
;;;138    
;;;139    	TK->CTL1 = (TK->CTL1 & ~0xff00) | ((mask & 0xff00) | ((mask & 0xFF) << 8)); // en
;;;140    	TK->CTL1 = (TK->CTL1 & ~0xff) | (((mask & 0xff00) >> 8) & ~(mask & 0xff)); // sel, 0~7 has higher priority
;;;141    	
;;;142    	TK->CTL1_BITS.START_BY_SW = 1;
;;;143    		
;;;144    	return(0);
;;;145    }
00000c  bd10              POP      {r4,pc}
                  |L14.14|
00000e  0a02              LSRS     r2,r0,#8              ;139
000010  0212              LSLS     r2,r2,#8              ;139
000012  0603              LSLS     r3,r0,#24             ;139
000014  0c1b              LSRS     r3,r3,#16             ;139
000016  431a              ORRS     r2,r2,r3              ;139
000018  680b              LDR      r3,[r1,#0]            ;139
00001a  24ff              MOVS     r4,#0xff              ;139
00001c  0224              LSLS     r4,r4,#8              ;139
00001e  43a3              BICS     r3,r3,r4              ;139
000020  431a              ORRS     r2,r2,r3              ;139
000022  600a              STR      r2,[r1,#0]            ;139
000024  680a              LDR      r2,[r1,#0]            ;140
000026  0a13              LSRS     r3,r2,#8              ;140
000028  021b              LSLS     r3,r3,#8              ;140
00002a  0a02              LSRS     r2,r0,#8              ;140
00002c  4382              BICS     r2,r2,r0              ;140
00002e  4313              ORRS     r3,r3,r2              ;140
000030  600b              STR      r3,[r1,#0]            ;140
000032  6808              LDR      r0,[r1,#0]            ;142
000034  2201              MOVS     r2,#1                 ;142
000036  0412              LSLS     r2,r2,#16             ;142
000038  4310              ORRS     r0,r0,r2              ;142
00003a  6008              STR      r0,[r1,#0]            ;142
00003c  2000              MOVS     r0,#0                 ;144
00003e  bd10              POP      {r4,pc}
;;;146    
                          ENDP

                  |L14.64|
                          DCD      0x400c0000
                  |L14.68|
                          DCD      0xffffa484

                          AREA ||i.TK_IRQHandler||, CODE, READONLY, ALIGN=2

                  TK_IRQHandler PROC
;;;345    
;;;346    void TK_IRQHandler(void)
000000  b510              PUSH     {r4,lr}
;;;347    {		
;;;348    
;;;349    	if(callback != NULL)
000002  4806              LDR      r0,|L15.28|
000004  6841              LDR      r1,[r0,#4]  ; callback
000006  2900              CMP      r1,#0
000008  d001              BEQ      |L15.14|
;;;350    		callback(data);
00000a  6880              LDR      r0,[r0,#8]  ; data
00000c  4788              BLX      r1
                  |L15.14|
;;;351    
;;;352    	// Clear interrupt status.
;;;353    	TK->STAT = TK->STAT & 0xFFFF02;
00000e  4904              LDR      r1,|L15.32|
000010  68c8              LDR      r0,[r1,#0xc]
000012  4a04              LDR      r2,|L15.36|
000014  4010              ANDS     r0,r0,r2
000016  60c8              STR      r0,[r1,#0xc]
;;;354    
;;;355    	return;
;;;356    }
000018  bd10              POP      {r4,pc}
;;;357    
                          ENDP

00001a  0000              DCW      0x0000
                  |L15.28|
                          DCD      ||.data||
                  |L15.32|
                          DCD      0x400c0000
                  |L15.36|
                          DCD      0x00ffff02

                          AREA ||.data||, DATA, ALIGN=2

                  tk_opened
000000  00000000          DCB      0x00,0x00,0x00,0x00
                  callback
                          DCD      0x00000000
                  data
                          DCD      0x00000000
