; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_adc.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_adc.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_adc.crf ..\bsp\Driver\nano1xx_adc.c]
                          THUMB

                          AREA ||i.ADC_ConfigCal||, CODE, READONLY, ALIGN=2

                  ADC_ConfigCal PROC
;;;293      */
;;;294    void ADC_ConfigCal(uint8_t u8Enable, uint32_t u32Mode)
000000  b510              PUSH     {r4,lr}
;;;295    {
;;;296    
;;;297    	uint32_t reg;
;;;298    
;;;299    	assert_param((u32Mode == ADC_CALCTL_CALSEL) || (u32Mode == ADC_CALCTL_LOAD));
;;;300    
;;;301    	reg = ADC->CALCTL & ~(ADC_CALCTL_CALEN | ADC_CALCTL_CALSEL);
000002  4b05              LDR      r3,|L1.24|
000004  6a9a              LDR      r2,[r3,#0x28]
000006  2409              MOVS     r4,#9
000008  43a2              BICS     r2,r2,r4
;;;302    	ADC->CALCTL = reg | u32Mode | (u8Enable == 0 ? 0 : 1);
00000a  430a              ORRS     r2,r2,r1
00000c  2800              CMP      r0,#0
00000e  d000              BEQ      |L1.18|
000010  2001              MOVS     r0,#1
                  |L1.18|
000012  4302              ORRS     r2,r2,r0
000014  629a              STR      r2,[r3,#0x28]
;;;303    
;;;304    }
000016  bd10              POP      {r4,pc}
;;;305    
                          ENDP

                  |L1.24|
                          DCD      0x400e0040

                          AREA ||i.ADC_DeInit||, CODE, READONLY, ALIGN=2

                  ADC_DeInit PROC
;;;56       */
;;;57     void ADC_DeInit(void)
000000  b510              PUSH     {r4,lr}
;;;58     {
;;;59             ADC->CHER = 0;
000002  4907              LDR      r1,|L2.32|
000004  2000              MOVS     r0,#0
000006  60c8              STR      r0,[r1,#0xc]
;;;60             ADC->CR = 0;
000008  6088              STR      r0,[r1,#8]
;;;61             ADC->CMPR0 = 0;
00000a  6108              STR      r0,[r1,#0x10]
;;;62             ADC->CMPR1 = 0;
00000c  6148              STR      r0,[r1,#0x14]
;;;63             CLK->APBCLK &= ~CLK_APBCLK_ADC_EN;         /* ADC engine clock disable */
00000e  4805              LDR      r0,|L2.36|
000010  6881              LDR      r1,[r0,#8]
000012  04c2              LSLS     r2,r0,#19
000014  4391              BICS     r1,r1,r2
000016  6081              STR      r1,[r0,#8]
;;;64     
;;;65             NVIC_DisableIRQ(ADC_IRQn);
000018  201d              MOVS     r0,#0x1d
00001a  f7fffffe          BL       NVIC_DisableIRQ
;;;66     }
00001e  bd10              POP      {r4,pc}
;;;67     
                          ENDP

                  |L2.32|
                          DCD      0x400e0040
                  |L2.36|
                          DCD      0x50000200

                          AREA ||i.ADC_DisableComp0Int||, CODE, READONLY, ALIGN=2

                  ADC_DisableComp0Int PROC
;;;116      */
;;;117    void ADC_DisableComp0Int(void)
000000  b510              PUSH     {r4,lr}
;;;118    {
;;;119            ADC->CMPR0 &= ~ADC_CMPR_CMPIE;
000002  4807              LDR      r0,|L3.32|
000004  6901              LDR      r1,[r0,#0x10]
000006  2202              MOVS     r2,#2
000008  4391              BICS     r1,r1,r2
00000a  6101              STR      r1,[r0,#0x10]
;;;120    
;;;121            if(!(ADC->CR & ADC_CR_ADIE))
00000c  6881              LDR      r1,[r0,#8]
00000e  0789              LSLS     r1,r1,#30
000010  d405              BMI      |L3.30|
;;;122                if(!(ADC->CMPR1 & ADC_CMPR_CMPIE))
000012  6940              LDR      r0,[r0,#0x14]
000014  0780              LSLS     r0,r0,#30
000016  d402              BMI      |L3.30|
;;;123    		NVIC_DisableIRQ(ADC_IRQn);
000018  201d              MOVS     r0,#0x1d
00001a  f7fffffe          BL       NVIC_DisableIRQ
                  |L3.30|
;;;124    }
00001e  bd10              POP      {r4,pc}
;;;125    
                          ENDP

                  |L3.32|
                          DCD      0x400e0040

                          AREA ||i.ADC_DisableComp1Int||, CODE, READONLY, ALIGN=2

                  ADC_DisableComp1Int PROC
;;;144      */
;;;145    void ADC_DisableComp1Int(void)
000000  b510              PUSH     {r4,lr}
;;;146    {
;;;147            ADC->CMPR1 &= ~ADC_CMPR_CMPIE;
000002  4807              LDR      r0,|L4.32|
000004  6941              LDR      r1,[r0,#0x14]
000006  2202              MOVS     r2,#2
000008  4391              BICS     r1,r1,r2
00000a  6141              STR      r1,[r0,#0x14]
;;;148    
;;;149            if(!(ADC->CR & ADC_CR_ADIE))
00000c  6881              LDR      r1,[r0,#8]
00000e  0789              LSLS     r1,r1,#30
000010  d405              BMI      |L4.30|
;;;150                if(!(ADC->CMPR0 & ADC_CMPR_CMPIE))
000012  6900              LDR      r0,[r0,#0x10]
000014  0780              LSLS     r0,r0,#30
000016  d402              BMI      |L4.30|
;;;151    		NVIC_DisableIRQ(ADC_IRQn);
000018  201d              MOVS     r0,#0x1d
00001a  f7fffffe          BL       NVIC_DisableIRQ
                  |L4.30|
;;;152    
;;;153    }
00001e  bd10              POP      {r4,pc}
;;;154    
                          ENDP

                  |L4.32|
                          DCD      0x400e0040

                          AREA ||i.ADC_DisableInt||, CODE, READONLY, ALIGN=2

                  ADC_DisableInt PROC
;;;88       */
;;;89     void ADC_DisableInt(void)
000000  b510              PUSH     {r4,lr}
;;;90     {
;;;91             ADC->CR &= ~ADC_CR_ADIE;
000002  4807              LDR      r0,|L5.32|
000004  6881              LDR      r1,[r0,#8]
000006  2202              MOVS     r2,#2
000008  4391              BICS     r1,r1,r2
00000a  6081              STR      r1,[r0,#8]
;;;92             if(!(ADC->CMPR0 & ADC_CMPR_CMPIE))
00000c  6901              LDR      r1,[r0,#0x10]
00000e  0789              LSLS     r1,r1,#30
000010  d405              BMI      |L5.30|
;;;93                 if(!(ADC->CMPR1 & ADC_CMPR_CMPIE))
000012  6940              LDR      r0,[r0,#0x14]
000014  0780              LSLS     r0,r0,#30
000016  d402              BMI      |L5.30|
;;;94     		NVIC_DisableIRQ(ADC_IRQn);
000018  201d              MOVS     r0,#0x1d
00001a  f7fffffe          BL       NVIC_DisableIRQ
                  |L5.30|
;;;95     }
00001e  bd10              POP      {r4,pc}
;;;96     
                          ENDP

                  |L5.32|
                          DCD      0x400e0040

                          AREA ||i.ADC_EnableComp0||, CODE, READONLY, ALIGN=2

                  ADC_EnableComp0 PROC
;;;223      */
;;;224    void ADC_EnableComp0(uint8_t u8ch,
000000  021b              LSLS     r3,r3,#8
;;;225                                 uint32_t u32Condition,
;;;226                                 uint16_t u16Data,
;;;227                                 uint8_t u8Count)
;;;228    {
;;;229            assert_param(u8ch < ADC_CH_NUM);
;;;230            assert_param(u16Data <= ADC_RESULT_RSLT_MASK);
;;;231            assert_param(u8Count <= (ADC_CMPR_CMPMATCNT_MASK + 1));
;;;232    	assert_param((u32Condition == ADC_CMPR_CMPCOND_GE) || (u32Condition == ADC_CMPR_CMPCOND_LT));
;;;233    
;;;234            ADC->CMPR0 = (u16Data << 16) | ((u8Count - 1) << 8) | (u8ch << 3) | u32Condition | ADC_CMPR_CMPEN;
000002  3bff              SUBS     r3,r3,#0xff
000004  0412              LSLS     r2,r2,#16
000006  3b01              SUBS     r3,#1
000008  431a              ORRS     r2,r2,r3
00000a  00c0              LSLS     r0,r0,#3
00000c  4302              ORRS     r2,r2,r0
00000e  430a              ORRS     r2,r2,r1
000010  2001              MOVS     r0,#1
000012  4302              ORRS     r2,r2,r0
000014  4801              LDR      r0,|L6.28|
000016  6102              STR      r2,[r0,#0x10]
;;;235    
;;;236    }
000018  4770              BX       lr
;;;237    
                          ENDP

00001a  0000              DCW      0x0000
                  |L6.28|
                          DCD      0x400e0040

                          AREA ||i.ADC_EnableComp0Int||, CODE, READONLY, ALIGN=2

                  ADC_EnableComp0Int PROC
;;;102      */
;;;103    void ADC_EnableComp0Int(void)
000000  4804              LDR      r0,|L7.20|
;;;104    {
;;;105    
;;;106            ADC->SR = ADC_SR_CMPF0;        /* clear the ADC comparator 1 interrupt flag for safe */
000002  2102              MOVS     r1,#2
000004  6181              STR      r1,[r0,#0x18]
;;;107            ADC->CMPR0 |= ADC_CMPR_CMPIE;
000006  6902              LDR      r2,[r0,#0x10]
000008  430a              ORRS     r2,r2,r1
00000a  6102              STR      r2,[r0,#0x10]
00000c  4902              LDR      r1,|L7.24|
00000e  05c0              LSLS     r0,r0,#23
000010  6008              STR      r0,[r1,#0]
;;;108            NVIC_EnableIRQ(ADC_IRQn);
;;;109    }
000012  4770              BX       lr
;;;110    
                          ENDP

                  |L7.20|
                          DCD      0x400e0040
                  |L7.24|
                          DCD      0xe000e100

                          AREA ||i.ADC_EnableComp1||, CODE, READONLY, ALIGN=2

                  ADC_EnableComp1 PROC
;;;246      */
;;;247    void ADC_EnableComp1(uint8_t u8ch,
000000  021b              LSLS     r3,r3,#8
;;;248                                 uint32_t u32Condition,
;;;249                                 uint16_t u16Data,
;;;250                                 uint8_t u8Count)
;;;251    {
;;;252            assert_param(u8ch < ADC_CH_NUM);
;;;253            assert_param(u16Data <= ADC_RESULT_RSLT_MASK);
;;;254            assert_param(u8Count <= (ADC_CMPR_CMPMATCNT_MASK + 1));
;;;255    	assert_param((u32Condition == ADC_CMPR_CMPCOND_GE) || (u32Condition == ADC_CMPR_CMPCOND_LT));
;;;256    
;;;257            ADC->CMPR1 = (u16Data << 16) | ((u8Count - 1) << 8) | (u8ch << 3) | u32Condition | ADC_CMPR_CMPEN;
000002  3bff              SUBS     r3,r3,#0xff
000004  0412              LSLS     r2,r2,#16
000006  3b01              SUBS     r3,#1
000008  431a              ORRS     r2,r2,r3
00000a  00c0              LSLS     r0,r0,#3
00000c  4302              ORRS     r2,r2,r0
00000e  430a              ORRS     r2,r2,r1
000010  2001              MOVS     r0,#1
000012  4302              ORRS     r2,r2,r0
000014  4801              LDR      r0,|L8.28|
000016  6142              STR      r2,[r0,#0x14]
;;;258    
;;;259    }
000018  4770              BX       lr
;;;260    
                          ENDP

00001a  0000              DCW      0x0000
                  |L8.28|
                          DCD      0x400e0040

                          AREA ||i.ADC_EnableComp1Int||, CODE, READONLY, ALIGN=2

                  ADC_EnableComp1Int PROC
;;;130      */
;;;131    void ADC_EnableComp1Int(void)
000000  4805              LDR      r0,|L9.24|
;;;132    {
;;;133    
;;;134            ADC->SR = ADC_SR_CMPF1;        /* clear the ADC comparator 1 interrupt flag for safe */
000002  2104              MOVS     r1,#4
000004  6181              STR      r1,[r0,#0x18]
;;;135            ADC->CMPR1 |= ADC_CMPR_CMPIE;
000006  6941              LDR      r1,[r0,#0x14]
000008  2202              MOVS     r2,#2
00000a  4311              ORRS     r1,r1,r2
00000c  6141              STR      r1,[r0,#0x14]
00000e  4903              LDR      r1,|L9.28|
000010  05c0              LSLS     r0,r0,#23
000012  6008              STR      r0,[r1,#0]
;;;136            NVIC_EnableIRQ(ADC_IRQn);
;;;137    }
000014  4770              BX       lr
;;;138    
                          ENDP

000016  0000              DCW      0x0000
                  |L9.24|
                          DCD      0x400e0040
                  |L9.28|
                          DCD      0xe000e100

                          AREA ||i.ADC_EnableExtTrigger||, CODE, READONLY, ALIGN=2

                  ADC_EnableExtTrigger PROC
;;;160      */
;;;161    void ADC_EnableExtTrigger(uint32_t u32Condition)
000000  4a04              LDR      r2,|L10.20|
;;;162    {
;;;163    	uint32_t reg;
;;;164    
;;;165    	assert_param((u32Condition == ADC_CR_TRGCOND_L_LEV) ||
;;;166    		(u32Condition == ADC_CR_TRGCOND_H_LEV) ||
;;;167    		(u32Condition == ADC_CR_TRGCOND_F_EDGE) ||
;;;168    		(u32Condition == ADC_CR_TRGCOND_R_EDGE));
;;;169    
;;;170    	reg = ADC->CR & ~(ADC_CR_TRGCOND_MASK);
000002  6891              LDR      r1,[r2,#8]
000004  23c0              MOVS     r3,#0xc0
000006  4399              BICS     r1,r1,r3
;;;171    	ADC->CR = reg | u32Condition | ADC_CR_TRGEN;
000008  4301              ORRS     r1,r1,r0
00000a  1590              ASRS     r0,r2,#22
00000c  4301              ORRS     r1,r1,r0
00000e  6091              STR      r1,[r2,#8]
;;;172    
;;;173    }
000010  4770              BX       lr
;;;174    
                          ENDP

000012  0000              DCW      0x0000
                  |L10.20|
                          DCD      0x400e0040

                          AREA ||i.ADC_EnableInt||, CODE, READONLY, ALIGN=2

                  ADC_EnableInt PROC
;;;75       */
;;;76     void ADC_EnableInt(void)
000000  4805              LDR      r0,|L11.24|
;;;77     {
;;;78     
;;;79             ADC->SR = ADC_SR_ADF;  // clear interrupt flag
000002  2101              MOVS     r1,#1
000004  6181              STR      r1,[r0,#0x18]
;;;80             ADC->CR |= ADC_CR_ADIE;
000006  6881              LDR      r1,[r0,#8]
000008  2202              MOVS     r2,#2
00000a  4311              ORRS     r1,r1,r2
00000c  6081              STR      r1,[r0,#8]
00000e  4903              LDR      r1,|L11.28|
000010  05c0              LSLS     r0,r0,#23
000012  6008              STR      r0,[r1,#0]
;;;81             NVIC_EnableIRQ(ADC_IRQn);
;;;82     }
000014  4770              BX       lr
;;;83     
                          ENDP

000016  0000              DCW      0x0000
                  |L11.24|
                          DCD      0x400e0040
                  |L11.28|
                          DCD      0xe000e100

                          AREA ||i.ADC_EnableTimerTrigger||, CODE, READONLY, ALIGN=2

                  ADC_EnableTimerTrigger PROC
;;;268      */
;;;269    void ADC_EnableTimerTrigger(S_ADC_TIMER_TRIGGER_CFG *cfg)
000000  4b06              LDR      r3,|L12.28|
;;;270    {
;;;271    	uint32_t reg;
;;;272    
;;;273            assert_param(cfg != NULL);
;;;274            assert_param(cfg->u8Cnt != 0);
;;;275            assert_param((cfg->u32Src == ADC_CR_TMSEL_TMR0_CH0) ||
;;;276    		(cfg->u32Src == ADC_CR_TMSEL_TMR0_CH1) ||
;;;277    		(cfg->u32Src == ADC_CR_TMSEL_TMR1_CH0) ||
;;;278    		(cfg->u32Src == ADC_CR_TMSEL_TMR1_CH1));
;;;279    
;;;280    	reg = ADC->CR & ~(ADC_CR_TMSEL_MASK | ADC_CR_TMPDMACNT_MASK | ADC_CR_ADEN);
000002  6899              LDR      r1,[r3,#8]
000004  4a06              LDR      r2,|L12.32|
000006  4011              ANDS     r1,r1,r2
;;;281    	ADC->CR = reg | (cfg->u32Src) | (cfg->u8Cnt) | ADC_CR_TMTRGMOD;
000008  6802              LDR      r2,[r0,#0]
00000a  7900              LDRB     r0,[r0,#4]
00000c  4302              ORRS     r2,r2,r0
00000e  2001              MOVS     r0,#1
000010  03c0              LSLS     r0,r0,#15
000012  4301              ORRS     r1,r1,r0
000014  430a              ORRS     r2,r2,r1
000016  609a              STR      r2,[r3,#8]
;;;282    
;;;283    }
000018  4770              BX       lr
;;;284    
                          ENDP

00001a  0000              DCW      0x0000
                  |L12.28|
                          DCD      0x400e0040
                  |L12.32|
                          DCD      0x00ffcffe

                          AREA ||i.ADC_GetConversionData||, CODE, READONLY, ALIGN=2

                  ADC_GetConversionData PROC
;;;182      */
;;;183    int32_t ADC_GetConversionData(uint8_t u8Ch)
000000  4903              LDR      r1,|L13.16|
;;;184    {
;;;185            return(*(__IO uint32_t *)(ADC_BASE + (u8Ch * 4)) & ADC_RESULT_RSLT_MASK);
000002  0080              LSLS     r0,r0,#2
000004  1840              ADDS     r0,r0,r1
000006  6800              LDR      r0,[r0,#0]
000008  0500              LSLS     r0,r0,#20
00000a  0d00              LSRS     r0,r0,#20
;;;186    }
00000c  4770              BX       lr
;;;187    
                          ENDP

00000e  0000              DCW      0x0000
                  |L13.16|
                          DCD      0x400e0000

                          AREA ||i.ADC_Init||, CODE, READONLY, ALIGN=2

                  ADC_Init PROC
;;;33       */
;;;34     void ADC_Init(uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32Mask, uint32_t u32Ref)
000000  b570              PUSH     {r4-r6,lr}
;;;35     {
;;;36             assert_param(u32Mask < (1 << ADC_CH_NUM));
;;;37             assert_param((u32InputMode == ADC_CR_DIFF) || (u32InputMode == ADC_CR_SINGLE_END));
;;;38     	assert_param((u32OpMode == ADC_CR_ADMD_SINGEL) ||
;;;39                          (u32OpMode == ADC_CR_ADMD_S_CYCLE) ||
;;;40                          (u32OpMode == ADC_CR_ADMD_CONTINUOUS));
;;;41             assert_param((u32Ref == ADC_CR_REFSEL_AVDD) ||
;;;42     		(u32Ref == ADC_CR_REFSEL_INT_REF) ||
;;;43     		(u32Ref == ADC_CR_REFSEL_VREF));
;;;44     
;;;45             /* ADC engine clock enable */
;;;46             CLK->APBCLK |= CLK_APBCLK_ADC_EN;
000002  4c07              LDR      r4,|L14.32|
000004  68a5              LDR      r5,[r4,#8]
000006  04e6              LSLS     r6,r4,#19
000008  4335              ORRS     r5,r5,r6
00000a  60a5              STR      r5,[r4,#8]
;;;47     	ADC->CR = u32InputMode | u32OpMode | u32Ref | ADC_CR_RESSEL_12BIT;
00000c  4308              ORRS     r0,r0,r1
00000e  2103              MOVS     r1,#3
000010  4318              ORRS     r0,r0,r3
000012  0489              LSLS     r1,r1,#18
000014  4308              ORRS     r0,r0,r1
000016  4903              LDR      r1,|L14.36|
000018  6088              STR      r0,[r1,#8]
;;;48             ADC->CHER = u32Mask;
00001a  60ca              STR      r2,[r1,#0xc]
;;;49     
;;;50     }
00001c  bd70              POP      {r4-r6,pc}
;;;51     
                          ENDP

00001e  0000              DCW      0x0000
                  |L14.32|
                          DCD      0x50000200
                  |L14.36|
                          DCD      0x400e0040

                          AREA ||i.ADC_IsDataOverrun||, CODE, READONLY, ALIGN=2

                  ADC_IsDataOverrun PROC
;;;208      */
;;;209    uint32_t ADC_IsDataOverrun(uint8_t u8Ch)
000000  4903              LDR      r1,|L15.16|
;;;210    {
;;;211            assert_param(u8Ch < ADC_CH_NUM);
;;;212    
;;;213            return((*(__IO uint32_t *)(ADC_BASE + (u8Ch * 4)) & ADC_RESULT_OVERRUN) ? 1 : 0);
000002  0080              LSLS     r0,r0,#2
000004  1840              ADDS     r0,r0,r1
000006  6800              LDR      r0,[r0,#0]
000008  0380              LSLS     r0,r0,#14
00000a  0fc0              LSRS     r0,r0,#31
;;;214    }
00000c  4770              BX       lr
;;;215    
                          ENDP

00000e  0000              DCW      0x0000
                  |L15.16|
                          DCD      0x400e0000

                          AREA ||i.ADC_IsDataValid||, CODE, READONLY, ALIGN=2

                  ADC_IsDataValid PROC
;;;194      */
;;;195    uint32_t ADC_IsDataValid(uint8_t u8Ch)
000000  4903              LDR      r1,|L16.16|
;;;196    {
;;;197            assert_param(u8Ch < ADC_CH_NUM);
;;;198    
;;;199            return((*(__IO uint32_t *)(ADC_BASE + (u8Ch * 4)) & ADC_RESULT_VALID) ? 1 : 0);
000002  0080              LSLS     r0,r0,#2
000004  1840              ADDS     r0,r0,r1
000006  6800              LDR      r0,[r0,#0]
000008  03c0              LSLS     r0,r0,#15
00000a  0fc0              LSRS     r0,r0,#31
;;;200    }
00000c  4770              BX       lr
;;;201    
                          ENDP

00000e  0000              DCW      0x0000
                  |L16.16|
                          DCD      0x400e0000

                          AREA ||i.ADC_SetPDMode||, CODE, READONLY, ALIGN=2

                  ADC_SetPDMode PROC
;;;315      */
;;;316    void ADC_SetPDMode(uint32_t u32PdMode, uint32_t u32CalEn)
000000  b510              PUSH     {r4,lr}
;;;317    {
;;;318    	uint32_t reg;
;;;319    
;;;320    	assert_param((u32PdMode == ADC_PWRCTL_PWDMOD_PD) || (u32PdMode == ADC_PWRCTL_PWDMOD_STBY));
;;;321    	assert_param((u32CalEn == ADC_PWRCTL_PWDCALEN) || (u32CalEn == ADC_PWRCTL_PWDCALDIS));
;;;322    
;;;323    	reg = ADC->PWRCTL & ~(ADC_PWRCTL_PWDCALEN | ADC_PWRCTL_PWDMOD_STBY);
000002  4b04              LDR      r3,|L17.20|
000004  6a5a              LDR      r2,[r3,#0x24]
000006  240a              MOVS     r4,#0xa
000008  43a2              BICS     r2,r2,r4
;;;324    	ADC->PWRCTL = reg | u32PdMode | u32CalEn;
00000a  4302              ORRS     r2,r2,r0
00000c  430a              ORRS     r2,r2,r1
00000e  625a              STR      r2,[r3,#0x24]
;;;325    
;;;326    }
000010  bd10              POP      {r4,pc}
;;;327    
                          ENDP

000012  0000              DCW      0x0000
                  |L17.20|
                          DCD      0x400e0040

                          AREA ||i.ADC_SetResolution||, CODE, READONLY, ALIGN=2

                  ADC_SetResolution PROC
;;;332      */
;;;333    void ADC_SetResolution(uint32_t u32Res)
000000  4a03              LDR      r2,|L18.16|
;;;334    {
;;;335            assert_param((u32Res == ADC_CR_RESSEL_6BIT) ||
;;;336                         (u32Res == ADC_CR_RESSEL_8BIT) ||
;;;337                         (u32Res == ADC_CR_RESSEL_10BIT) ||
;;;338                         (u32Res == ADC_CR_RESSEL_12BIT));
;;;339            ADC->CR = (ADC->CR & ~ADC_CR_RESSEL_MASK) | u32Res;
000002  6891              LDR      r1,[r2,#8]
000004  2303              MOVS     r3,#3
000006  049b              LSLS     r3,r3,#18
000008  4399              BICS     r1,r1,r3
00000a  4301              ORRS     r1,r1,r0
00000c  6091              STR      r1,[r2,#8]
;;;340    
;;;341    }
00000e  4770              BX       lr
;;;342    
                          ENDP

                  |L18.16|
                          DCD      0x400e0040

                          AREA ||i.ADC_SetSampleTime||, CODE, READONLY, ALIGN=2

                  ADC_SetSampleTime PROC
;;;349      */
;;;350    void ADC_SetSampleTime(uint8_t u8Ch, uint32_t u32Time)
000000  b510              PUSH     {r4,lr}
;;;351    {
;;;352            uint32_t reg;
;;;353    
;;;354            assert_param(u8Ch < ADC_CH_NUM);
;;;355            assert_param(u32Time < ADC_SMPLCNT_Mask);
;;;356    
;;;357            if(u8Ch< 8) {
;;;358                    reg = ADC->SMPLCNT0 & ~(0xF << (4 *u8Ch));
000002  240f              MOVS     r4,#0xf
000004  4b0d              LDR      r3,|L19.60|
000006  0082              LSLS     r2,r0,#2
000008  2808              CMP      r0,#8                 ;357
00000a  d206              BCS      |L19.26|
00000c  6b18              LDR      r0,[r3,#0x30]
00000e  4094              LSLS     r4,r4,r2
000010  43a0              BICS     r0,r0,r4
;;;359                    ADC->SMPLCNT0 = reg | (u32Time << (4 * u8Ch));
000012  4091              LSLS     r1,r1,r2
000014  4301              ORRS     r1,r1,r0
000016  6319              STR      r1,[r3,#0x30]
;;;360            } else if(u8Ch < 12) {
;;;361                    reg = ADC->SMPLCNT1 & ~(0xF << (4 * (u8Ch - 8)));
;;;362                    ADC->SMPLCNT1 = reg | (u32Time << (4 * (u8Ch - 8)));
;;;363            } else {  // internal channel
;;;364                    reg = ADC->SMPLCNT1 & ~(0xF << (4 * (13 - 8)));
;;;365                    ADC->SMPLCNT1 = reg | (u32Time << (4 * (13 - 8)));
;;;366            }
;;;367    
;;;368    }
000018  bd10              POP      {r4,pc}
                  |L19.26|
00001a  280c              CMP      r0,#0xc               ;360
00001c  d205              BCS      |L19.42|
00001e  3a20              SUBS     r2,r2,#0x20           ;361
000020  6b58              LDR      r0,[r3,#0x34]         ;361
000022  4094              LSLS     r4,r4,r2              ;361
000024  43a0              BICS     r0,r0,r4              ;361
000026  4091              LSLS     r1,r1,r2              ;362
000028  e004              B        |L19.52|
                  |L19.42|
00002a  6b58              LDR      r0,[r3,#0x34]         ;364
00002c  220f              MOVS     r2,#0xf               ;364
00002e  0512              LSLS     r2,r2,#20             ;364
000030  4390              BICS     r0,r0,r2              ;364
000032  0509              LSLS     r1,r1,#20             ;365
                  |L19.52|
000034  4301              ORRS     r1,r1,r0              ;365
000036  6359              STR      r1,[r3,#0x34]         ;365
000038  bd10              POP      {r4,pc}
;;;369    
                          ENDP

00003a  0000              DCW      0x0000
                  |L19.60|
                          DCD      0x400e0040

                          AREA ||i.NVIC_DisableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_DisableIRQ PROC
;;;511     */
;;;512    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;513    {
;;;514      NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L20.16|
00000a  6008              STR      r0,[r1,#0]
;;;515    }
00000c  4770              BX       lr
;;;516    
                          ENDP

00000e  0000              DCW      0x0000
                  |L20.16|
                          DCD      0xe000e180

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_adc.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_adc_c_ADC_Init____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___13_nano1xx_adc_c_ADC_Init____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_adc_c_ADC_Init____REVSH|
#line 130
|__asm___13_nano1xx_adc_c_ADC_Init____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
