; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_dac.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_dac.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_dac.crf ..\bsp\Driver\nano1xx_dac.c]
                          THUMB

                          AREA ||i.DAC_DisableInterrupt||, CODE, READONLY, ALIGN=2

                  DAC_DisableInterrupt PROC
;;;126      */
;;;127    void DAC_DisableInterrupt(uint8_t u8Ch)
000000  2202              MOVS     r2,#2
;;;128    {
;;;129            assert_param(u8Ch < DAC_CH_NUM);
;;;130    
;;;131            if(u8Ch == 0) {
;;;132                    DAC->CTL0 &= ~DAC_CTL_IE;
000002  490a              LDR      r1,|L1.44|
000004  2800              CMP      r0,#0                 ;131
000006  d00d              BEQ      |L1.36|
;;;133            } else {
;;;134                    DAC->CTL1 &= ~DAC_CTL_IE;
000008  6908              LDR      r0,[r1,#0x10]
00000a  4390              BICS     r0,r0,r2
00000c  6108              STR      r0,[r1,#0x10]
                  |L1.14|
;;;135            }
;;;136            if(!(DAC->CTL0 & DAC_CTL_IE))
00000e  6808              LDR      r0,[r1,#0]
000010  0780              LSLS     r0,r0,#30
000012  d406              BMI      |L1.34|
;;;137              if(!(DAC->CTL1 & DAC_CTL_IE))
000014  6908              LDR      r0,[r1,#0x10]
000016  0780              LSLS     r0,r0,#30
000018  d403              BMI      |L1.34|
00001a  2001              MOVS     r0,#1
00001c  4904              LDR      r1,|L1.48|
00001e  0780              LSLS     r0,r0,#30
000020  6008              STR      r0,[r1,#0]
                  |L1.34|
;;;138                    NVIC_DisableIRQ(DAC_IRQn);
;;;139    }
000022  4770              BX       lr
                  |L1.36|
000024  6808              LDR      r0,[r1,#0]            ;132
000026  4390              BICS     r0,r0,r2              ;132
000028  6008              STR      r0,[r1,#0]            ;132
00002a  e7f0              B        |L1.14|
;;;140    
                          ENDP

                  |L1.44|
                          DCD      0x400a0000
                  |L1.48|
                          DCD      0xe000e180

                          AREA ||i.DAC_EnableInterrupt||, CODE, READONLY, ALIGN=2

                  DAC_EnableInterrupt PROC
;;;104      */
;;;105    void DAC_EnableInterrupt(uint8_t u8Ch)
000000  4909              LDR      r1,|L2.40|
;;;106    {
;;;107    
;;;108            assert_param(u8Ch < DAC_CH_NUM);
;;;109    
;;;110    
;;;111            if(u8Ch == 0) {
;;;112                    DAC_CLEAR_CH0_INTERRUPT;
;;;113                    DAC->CTL0 |= DAC_CTL_IE;
000002  2302              MOVS     r3,#2
000004  2201              MOVS     r2,#1                 ;112
000006  2800              CMP      r0,#0                 ;111
000008  d008              BEQ      |L2.28|
;;;114            } else {
;;;115                    DAC_CLEAR_CH1_INTERRUPT;
00000a  618a              STR      r2,[r1,#0x18]
;;;116                    DAC->CTL1 |= DAC_CTL_IE;
00000c  6908              LDR      r0,[r1,#0x10]
00000e  4318              ORRS     r0,r0,r3
000010  6108              STR      r0,[r1,#0x10]
                  |L2.18|
000012  2001              MOVS     r0,#1
000014  4905              LDR      r1,|L2.44|
000016  0780              LSLS     r0,r0,#30
000018  6008              STR      r0,[r1,#0]
;;;117            }
;;;118    
;;;119            NVIC_EnableIRQ(DAC_IRQn);
;;;120    }
00001a  4770              BX       lr
                  |L2.28|
00001c  608a              STR      r2,[r1,#8]            ;112
00001e  6808              LDR      r0,[r1,#0]            ;113
000020  4318              ORRS     r0,r0,r3              ;113
000022  6008              STR      r0,[r1,#0]            ;113
000024  e7f5              B        |L2.18|
;;;121    
                          ENDP

000026  0000              DCW      0x0000
                  |L2.40|
                          DCD      0x400a0000
                  |L2.44|
                          DCD      0xe000e100

                          AREA ||i.DAC_GetState||, CODE, READONLY, ALIGN=2

                  DAC_GetState PROC
;;;150      */
;;;151    E_DAC_STATE DAC_GetState(uint8_t u8Ch)
000000  4907              LDR      r1,|L3.32|
;;;152    {
;;;153            uint32_t i;
;;;154    
;;;155            assert_param(u8Ch < DAC_CH_NUM);
;;;156    
;;;157            if(u8Ch == 0)
000002  2800              CMP      r0,#0
000004  d004              BEQ      |L3.16|
;;;158                    i = DAC->STS0;
;;;159            else
;;;160                    i = DAC->STS1;
000006  6988              LDR      r0,[r1,#0x18]
                  |L3.8|
;;;161    
;;;162            if(!(i & 0x2))
000008  0781              LSLS     r1,r0,#30
00000a  d403              BMI      |L3.20|
;;;163                    return(DAC_INIT);
00000c  2002              MOVS     r0,#2
;;;164            else if(i & 0x4)
;;;165                    return(DAC_BUSY);
;;;166            else
;;;167                    return(DAC_IDLE);
;;;168    
;;;169    
;;;170    }
00000e  4770              BX       lr
                  |L3.16|
000010  6888              LDR      r0,[r1,#8]            ;158
000012  e7f9              B        |L3.8|
                  |L3.20|
000014  0740              LSLS     r0,r0,#29             ;164
000016  d501              BPL      |L3.28|
000018  2001              MOVS     r0,#1                 ;165
00001a  4770              BX       lr
                  |L3.28|
00001c  2000              MOVS     r0,#0                 ;167
00001e  4770              BX       lr
;;;171    
                          ENDP

                  |L3.32|
                          DCD      0x400a0000

                          AREA ||i.DAC_SetDelayTime||, CODE, READONLY, ALIGN=2

                  DAC_SetDelayTime PROC
;;;54       */
;;;55     void DAC_SetDelayTime(uint8_t u8Ch, uint16_t u16PUPDelay, uint8_t u8ConvDelay)
000000  b510              PUSH     {r4,lr}
;;;56     {
;;;57     
;;;58             assert_param(u8Ch <DAC_CH_NUM);
;;;59             assert_param(u8ConvDelay != 0);
;;;60             assert_param(u16PUPDelay != 0);
;;;61             assert_param(u16PUPDelay < (1 << 15));
;;;62     
;;;63             DAC->COMCTL = (DAC->COMCTL & ~DAC_COMCTL_WAITDACCONV_MASK) | u8ConvDelay;
000002  4b0a              LDR      r3,|L4.44|
000004  6a1c              LDR      r4,[r3,#0x20]
000006  0a24              LSRS     r4,r4,#8
000008  0224              LSLS     r4,r4,#8
00000a  4314              ORRS     r4,r4,r2
00000c  621c              STR      r4,[r3,#0x20]
;;;64     
;;;65             if(u8Ch == 0) {
;;;66                     DAC->CTL0 = (DAC->CTL0 & ~DAC_CTL_PWONSTBCNT_MASK) | (u16PUPDelay << 8);
00000e  4a08              LDR      r2,|L4.48|
000010  0209              LSLS     r1,r1,#8
000012  2800              CMP      r0,#0                 ;65
000014  d004              BEQ      |L4.32|
;;;67             } else {
;;;68                     DAC->CTL1 = (DAC->CTL1 & ~DAC_CTL_PWONSTBCNT_MASK) | (u16PUPDelay << 8);
000016  6918              LDR      r0,[r3,#0x10]
000018  4010              ANDS     r0,r0,r2
00001a  4308              ORRS     r0,r0,r1
00001c  6118              STR      r0,[r3,#0x10]
;;;69             }
;;;70     
;;;71     }
00001e  bd10              POP      {r4,pc}
                  |L4.32|
000020  6818              LDR      r0,[r3,#0]            ;66
000022  4010              ANDS     r0,r0,r2              ;66
000024  4308              ORRS     r0,r0,r1              ;66
000026  6018              STR      r0,[r3,#0]            ;66
000028  bd10              POP      {r4,pc}
;;;72     
                          ENDP

00002a  0000              DCW      0x0000
                  |L4.44|
                          DCD      0x400a0000
                  |L4.48|
                          DCD      0xffc000ff

                          AREA ||i.DAC_SetLoadSel||, CODE, READONLY, ALIGN=2

                  DAC_SetLoadSel PROC
;;;79       */
;;;80     void DAC_SetLoadSel(uint8_t u8Ch, uint32_t u32LoadSel)
000000  4a06              LDR      r2,|L5.28|
;;;81     {
;;;82     
;;;83             assert_param(u8Ch < DAC_CH_NUM);
;;;84     	assert_param((u32LoadSel == DAC_CTL_LSEL_DATA_WRITE) ||
;;;85     		     (u32LoadSel == DAC_CTL_LSEL_PDMA) ||
;;;86     		     (u32LoadSel == DAC_CTL_LSEL_TIMER0_CH0) ||
;;;87     		     (u32LoadSel == DAC_CTL_LSEL_TIMER0_CH1) ||
;;;88     		     (u32LoadSel == DAC_CTL_LSEL_TIMER1_CH0) ||
;;;89     		     (u32LoadSel == DAC_CTL_LSEL_TIMER1_CH1));
;;;90     
;;;91             if(u8Ch == 0) {
;;;92                     DAC->CTL0 = (DAC->CTL0 & ~DAC_CTL_LSEL_MASK) | u32LoadSel;
000002  23f0              MOVS     r3,#0xf0
000004  2800              CMP      r0,#0                 ;91
000006  d004              BEQ      |L5.18|
;;;93             } else {
;;;94                     DAC->CTL1 = (DAC->CTL1 & ~DAC_CTL_LSEL_MASK) | u32LoadSel;
000008  6910              LDR      r0,[r2,#0x10]
00000a  4398              BICS     r0,r0,r3
00000c  4308              ORRS     r0,r0,r1
00000e  6110              STR      r0,[r2,#0x10]
;;;95             }
;;;96     
;;;97     }
000010  4770              BX       lr
                  |L5.18|
000012  6810              LDR      r0,[r2,#0]            ;92
000014  4398              BICS     r0,r0,r3              ;92
000016  4308              ORRS     r0,r0,r1              ;92
000018  6010              STR      r0,[r2,#0]            ;92
00001a  4770              BX       lr
;;;98     
                          ENDP

                  |L5.28|
                          DCD      0x400a0000

                          AREA ||i.DAC_WriteData||, CODE, READONLY, ALIGN=2

                  DAC_WriteData PROC
;;;30       */
;;;31     void DAC_WriteData(uint8_t u8Ch, uint16_t u16Data)
000000  4a03              LDR      r2,|L6.16|
;;;32     {
;;;33     
;;;34             assert_param(u8Ch < DAC_CH_NUM);
;;;35             assert_param(u16Data <= 0xFFF);
;;;36     
;;;37     
;;;38             if(u8Ch == 0) {
000002  2800              CMP      r0,#0
000004  d001              BEQ      |L6.10|
;;;39                     DAC->DATA0 = u16Data;
;;;40             } else {
;;;41                     DAC->DATA1 = u16Data;
000006  6151              STR      r1,[r2,#0x14]
;;;42             }
;;;43     }
000008  4770              BX       lr
                  |L6.10|
00000a  6051              STR      r1,[r2,#4]            ;39
00000c  4770              BX       lr
;;;44     
                          ENDP

00000e  0000              DCW      0x0000
                  |L6.16|
                          DCD      0x400a0000

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_dac.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_dac_c_d5bf63c4____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___13_nano1xx_dac_c_d5bf63c4____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_dac_c_d5bf63c4____REVSH|
#line 130
|__asm___13_nano1xx_dac_c_d5bf63c4____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
