; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_pwm.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_pwm.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_pwm.crf ..\bsp\Driver\nano1xx_pwm.c]
                          THUMB

                          AREA ||i.NVIC_EnableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_EnableIRQ PROC
;;;499     */
;;;500    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;501    {
;;;502      NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L1.16|
00000a  6008              STR      r0,[r1,#0]
;;;503    }
00000c  4770              BX       lr
;;;504    
                          ENDP

00000e  0000              DCW      0x0000
                  |L1.16|
                          DCD      0xe000e100

                          AREA ||i.PWM_CaptureDisable||, CODE, READONLY, ALIGN=2

                  PWM_CaptureDisable PROC
;;;385      */
;;;386    void PWM_CaptureDisable(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;387    {
;;;388            PWM_TypeDef *base = (u8Ch< 4) ? PWM0 : PWM1;
000002  d201              BCS      |L2.8|
000004  4907              LDR      r1,|L2.36|
000006  e000              B        |L2.10|
                  |L2.8|
000008  4907              LDR      r1,|L2.40|
                  |L2.10|
;;;389    	assert_param(u8Ch < PWM_CH_NUM);
;;;390    
;;;391    
;;;392    	base->CTL &= ~(0x9 << ((u8Ch & 0x3) * 8));
00000a  688a              LDR      r2,[r1,#8]
00000c  0780              LSLS     r0,r0,#30
00000e  0ec0              LSRS     r0,r0,#27
000010  2309              MOVS     r3,#9
000012  4083              LSLS     r3,r3,r0
000014  439a              BICS     r2,r2,r3
000016  608a              STR      r2,[r1,#8]
;;;393    	base->CAPCTL &= ~(2 << ((u8Ch & 0x3) * 8));
000018  6d4a              LDR      r2,[r1,#0x54]
00001a  2302              MOVS     r3,#2
00001c  4083              LSLS     r3,r3,r0
00001e  439a              BICS     r2,r2,r3
000020  654a              STR      r2,[r1,#0x54]
;;;394    
;;;395    
;;;396    }
000022  4770              BX       lr
;;;397    
                          ENDP

                  |L2.36|
                          DCD      0x40040000
                  |L2.40|
                          DCD      0x40140000

                          AREA ||i.PWM_CaptureEnable||, CODE, READONLY, ALIGN=2

                  PWM_CaptureEnable PROC
;;;354      */
;;;355    void PWM_CaptureEnable(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;356    {
;;;357            PWM_TypeDef *base = (u8Ch< 4) ? PWM0 : PWM1;
000002  d201              BCS      |L3.8|
000004  4907              LDR      r1,|L3.36|
000006  e000              B        |L3.10|
                  |L3.8|
000008  4907              LDR      r1,|L3.40|
                  |L3.10|
;;;358    	assert_param(u8Ch < PWM_CH_NUM);
;;;359    
;;;360    
;;;361    	base->CTL |= (0x9 << ((u8Ch & 0x3) * 8));
00000a  688a              LDR      r2,[r1,#8]
00000c  0780              LSLS     r0,r0,#30
00000e  0ec0              LSRS     r0,r0,#27
000010  2309              MOVS     r3,#9
000012  4083              LSLS     r3,r3,r0
000014  431a              ORRS     r2,r2,r3
000016  608a              STR      r2,[r1,#8]
;;;362    	base->CAPCTL |= (2 << ((u8Ch & 0x3) * 8));
000018  6d4a              LDR      r2,[r1,#0x54]
00001a  2302              MOVS     r3,#2
00001c  4083              LSLS     r3,r3,r0
00001e  431a              ORRS     r2,r2,r3
000020  654a              STR      r2,[r1,#0x54]
;;;363    
;;;364    
;;;365    }
000022  4770              BX       lr
;;;366    
                          ENDP

                  |L3.36|
                          DCD      0x40040000
                  |L3.40|
                          DCD      0x40140000

                          AREA ||i.PWM_ClearCaptureInt||, CODE, READONLY, ALIGN=2

                  PWM_ClearCaptureInt PROC
;;;162      */
;;;163    void PWM_ClearCaptureInt(uint8_t u8Ch)
000000  2107              MOVS     r1,#7
;;;164    {
;;;165    
;;;166    	assert_param(u8Ch < PWM_CH_NUM);
;;;167    	if(u8Ch < 4)
000002  2804              CMP      r0,#4
000004  d203              BCS      |L4.14|
;;;168    		PWM0->CAPINTSTS = 0x7 << (u8Ch * 8);
000006  00c0              LSLS     r0,r0,#3
000008  4081              LSLS     r1,r1,r0
00000a  4804              LDR      r0,|L4.28|
00000c  e003              B        |L4.22|
                  |L4.14|
;;;169    	else
;;;170    		PWM1->CAPINTSTS = 0x7 << ((u8Ch & 0x3) * 8);
00000e  0780              LSLS     r0,r0,#30
000010  0ec0              LSRS     r0,r0,#27
000012  4081              LSLS     r1,r1,r0
000014  4802              LDR      r0,|L4.32|
                  |L4.22|
000016  61c1              STR      r1,[r0,#0x1c]         ;168
;;;171    }
000018  4770              BX       lr
;;;172    
                          ENDP

00001a  0000              DCW      0x0000
                  |L4.28|
                          DCD      0x40040040
                  |L4.32|
                          DCD      0x40140040

                          AREA ||i.PWM_ClearInt||, CODE, READONLY, ALIGN=2

                  PWM_ClearInt PROC
;;;147      */
;;;148    void PWM_ClearInt(uint8_t u8Ch)
000000  2101              MOVS     r1,#1
;;;149    {
;;;150    
;;;151    	assert_param(u8Ch < PWM_CH_NUM);
;;;152    	if(u8Ch < 4)
000002  2804              CMP      r0,#4
000004  d202              BCS      |L5.12|
;;;153    		PWM0->INTSTS = 1 << u8Ch;
000006  4081              LSLS     r1,r1,r0
000008  4803              LDR      r0,|L5.24|
00000a  e003              B        |L5.20|
                  |L5.12|
;;;154    	else
;;;155    		PWM1->INTSTS = 1 << (u8Ch & 0x3);
00000c  0780              LSLS     r0,r0,#30
00000e  0f80              LSRS     r0,r0,#30
000010  4081              LSLS     r1,r1,r0
000012  4802              LDR      r0,|L5.28|
                  |L5.20|
000014  6101              STR      r1,[r0,#0x10]         ;153
;;;156    }
000016  4770              BX       lr
;;;157    
                          ENDP

                  |L5.24|
                          DCD      0x40040000
                  |L5.28|
                          DCD      0x40140000

                          AREA ||i.PWM_ConfigCaptureIntput||, CODE, READONLY, ALIGN=2

                  PWM_ConfigCaptureIntput PROC
;;;451      */
;;;452    void PWM_ConfigCaptureIntput(uint8_t u8Ch, uint32_t u32Enable)
000000  2804              CMP      r0,#4
;;;453    {
;;;454    
;;;455            PWM_TypeDef *base = (u8Ch < 4) ? PWM0 : PWM1;
000002  d201              BCS      |L6.8|
000004  4a07              LDR      r2,|L6.36|
000006  e000              B        |L6.10|
                  |L6.8|
000008  4a07              LDR      r2,|L6.40|
                  |L6.10|
;;;456            uint8_t ch = u8Ch & 0x3;
00000a  0780              LSLS     r0,r0,#30
;;;457    
;;;458    	assert_param(u8Ch < PWM_CH_NUM);
;;;459    	if(u32Enable)
;;;460    		base->CAPCTL |= 0x4 << (8 * ch);
00000c  0ec3              LSRS     r3,r0,#27
00000e  2004              MOVS     r0,#4
000010  4098              LSLS     r0,r0,r3
000012  2900              CMP      r1,#0                 ;459
;;;461    	else
;;;462    		base->CAPCTL &= ~(0x4 << (8 * ch));
000014  6d51              LDR      r1,[r2,#0x54]
000016  d001              BEQ      |L6.28|
000018  4301              ORRS     r1,r1,r0              ;460
00001a  e000              B        |L6.30|
                  |L6.28|
00001c  4381              BICS     r1,r1,r0
                  |L6.30|
00001e  6551              STR      r1,[r2,#0x54]         ;460
;;;463    }
000020  4770              BX       lr
;;;464    
                          ENDP

000022  0000              DCW      0x0000
                  |L6.36|
                          DCD      0x40040000
                  |L6.40|
                          DCD      0x40140000

                          AREA ||i.PWM_ConfigCascade||, CODE, READONLY, ALIGN=2

                  PWM_ConfigCascade PROC
;;;472      */
;;;473    void PWM_ConfigCascade(uint8_t u8Ch, uint32_t u32Enable)
000000  2804              CMP      r0,#4
;;;474    {
;;;475            PWM_TypeDef *base = (u8Ch < 4) ? PWM0 : PWM1;
000002  d201              BCS      |L7.8|
000004  4a07              LDR      r2,|L7.36|
000006  e000              B        |L7.10|
                  |L7.8|
000008  4a07              LDR      r2,|L7.40|
                  |L7.10|
;;;476            uint8_t ch = u8Ch & 0x3;
00000a  0780              LSLS     r0,r0,#30
;;;477    
;;;478    	assert_param(u8Ch < PWM_CH_NUM);
;;;479    	assert_param((u8Ch & 1) == 0);
;;;480    
;;;481    	if(u32Enable)
;;;482    		base->CAPCTL |= (0x2000 << (8 * ch));
00000c  0ec3              LSRS     r3,r0,#27
00000e  2001              MOVS     r0,#1
000010  0340              LSLS     r0,r0,#13
000012  4098              LSLS     r0,r0,r3
000014  2900              CMP      r1,#0                 ;481
;;;483    	else
;;;484    		base->CAPCTL &= ~(0x2000 << (8 * ch));
000016  6d51              LDR      r1,[r2,#0x54]
000018  d001              BEQ      |L7.30|
00001a  4301              ORRS     r1,r1,r0              ;482
00001c  e000              B        |L7.32|
                  |L7.30|
00001e  4381              BICS     r1,r1,r0
                  |L7.32|
000020  6551              STR      r1,[r2,#0x54]         ;482
;;;485    }
000022  4770              BX       lr
;;;486    
                          ENDP

                  |L7.36|
                          DCD      0x40040000
                  |L7.40|
                          DCD      0x40140000

                          AREA ||i.PWM_ConfigOutput||, CODE, READONLY, ALIGN=2

                  PWM_ConfigOutput PROC
;;;433      */
;;;434    void PWM_ConfigOutput(uint8_t u8Ch, uint32_t u32Enable)
000000  2804              CMP      r0,#4
;;;435    {
;;;436            PWM_TypeDef *base = (u8Ch < 4) ? PWM0 : PWM1;
000002  d201              BCS      |L8.8|
000004  4a07              LDR      r2,|L8.36|
000006  e000              B        |L8.10|
                  |L8.8|
000008  4a07              LDR      r2,|L8.40|
                  |L8.10|
;;;437            uint8_t ch = u8Ch & 0x3;
00000a  0780              LSLS     r0,r0,#30
;;;438    
;;;439    	assert_param(u8Ch < PWM_CH_NUM);
;;;440    	if(u32Enable)
;;;441    		base->OE |= (1 << ch);
00000c  2301              MOVS     r3,#1
00000e  0f80              LSRS     r0,r0,#30             ;437
000010  4083              LSLS     r3,r3,r0
;;;442    	else
;;;443    		base->OE &= ~(1 << ch);
000012  6950              LDR      r0,[r2,#0x14]
000014  2900              CMP      r1,#0                 ;440
000016  d001              BEQ      |L8.28|
000018  4318              ORRS     r0,r0,r3              ;441
00001a  e000              B        |L8.30|
                  |L8.28|
00001c  4398              BICS     r0,r0,r3
                  |L8.30|
00001e  6150              STR      r0,[r2,#0x14]         ;441
;;;444    }
000020  4770              BX       lr
;;;445    
                          ENDP

000022  0000              DCW      0x0000
                  |L8.36|
                          DCD      0x40040000
                  |L8.40|
                          DCD      0x40140000

                          AREA ||i.PWM_DeInit||, CODE, READONLY, ALIGN=2

                  PWM_DeInit PROC
;;;257      */
;;;258    void PWM_DeInit(uint8_t u8Ch)
000000  b570              PUSH     {r4-r6,lr}
;;;259    {
;;;260            PWM_TypeDef *base;
;;;261    	uint8_t ch;
;;;262    	assert_param(u8Ch < PWM_CH_NUM);
;;;263    
;;;264    
;;;265            ch = u8Ch & 0x3;
000002  0782              LSLS     r2,r0,#30
000004  0f92              LSRS     r2,r2,#30
;;;266            base = (u8Ch < 4) ? PWM0 : PWM1;
000006  2804              CMP      r0,#4
000008  d201              BCS      |L9.14|
00000a  4920              LDR      r1,|L9.140|
00000c  e000              B        |L9.16|
                  |L9.14|
00000e  4920              LDR      r1,|L9.144|
                  |L9.16|
;;;267    
;;;268    	base->CTL &= ~(1 << (ch * 8));
000010  688c              LDR      r4,[r1,#8]
000012  2501              MOVS     r5,#1
000014  00d3              LSLS     r3,r2,#3
000016  462e              MOV      r6,r5
000018  409e              LSLS     r6,r6,r3
00001a  43b4              BICS     r4,r4,r6
00001c  608c              STR      r4,[r1,#8]
;;;269            base->OE &= ~(1 << ch);
00001e  694e              LDR      r6,[r1,#0x14]
000020  462c              MOV      r4,r5
000022  4094              LSLS     r4,r4,r2
000024  43a6              BICS     r6,r6,r4
000026  614e              STR      r6,[r1,#0x14]
;;;270            base->CAPCTL &= ~(0x6 << (8 * ch));
000028  6d4a              LDR      r2,[r1,#0x54]
00002a  2606              MOVS     r6,#6
00002c  409e              LSLS     r6,r6,r3
00002e  43b2              BICS     r2,r2,r6
000030  654a              STR      r2,[r1,#0x54]
;;;271            base->CAPINTSTS = 0x7 << (ch * 8);
000032  2207              MOVS     r2,#7
000034  409a              LSLS     r2,r2,r3
000036  65ca              STR      r2,[r1,#0x5c]
;;;272            base->INTSTS = 1 << ch;
000038  610c              STR      r4,[r1,#0x10]
;;;273    
;;;274            if((base->INTEN & 0xF == 0) && (base->CAPINTEN & 0x03030303) == 0)
00003a  68c9              LDR      r1,[r1,#0xc]
;;;275    		NVIC_DisableIRQ(u8Ch < 0x04 ? PWM0_IRQn : PWM1_IRQn);
;;;276    
;;;277    	pwm_en &= ~(1 << u8Ch);
00003c  4a15              LDR      r2,|L9.148|
00003e  4085              LSLS     r5,r5,r0
000040  7811              LDRB     r1,[r2,#0]  ; pwm_en
000042  43a9              BICS     r1,r1,r5
000044  7011              STRB     r1,[r2,#0]
;;;278    	if(u8Ch < 2 && ((pwm_en & 0x3) == 0))
;;;279    		CLK->APBCLK &= ~CLK_APBCLK_PWM0_CH01_EN;
000046  4a14              LDR      r2,|L9.152|
000048  2802              CMP      r0,#2                 ;278
00004a  d204              BCS      |L9.86|
00004c  078b              LSLS     r3,r1,#30             ;278
00004e  d104              BNE      |L9.90|
000050  6890              LDR      r0,[r2,#8]
000052  02d1              LSLS     r1,r2,#11
000054  e012              B        |L9.124|
                  |L9.86|
;;;280    	else if(u8Ch < 4 && ((pwm_en & 0xC) == 0))
000056  2804              CMP      r0,#4
000058  d202              BCS      |L9.96|
                  |L9.90|
00005a  070b              LSLS     r3,r1,#28
00005c  0f9b              LSRS     r3,r3,#30
00005e  d00a              BEQ      |L9.118|
                  |L9.96|
;;;281    		CLK->APBCLK &= ~CLK_APBCLK_PWM0_CH23_EN;
;;;282    	else if(u8Ch < 6 && ((pwm_en & 0x30) == 0))
000060  2806              CMP      r0,#6
000062  d202              BCS      |L9.106|
000064  0688              LSLS     r0,r1,#26
000066  0f80              LSRS     r0,r0,#30
000068  d00b              BEQ      |L9.130|
                  |L9.106|
;;;283    		CLK->APBCLK &= ~CLK_APBCLK_PWM1_CH01_EN;
;;;284    	else if(((pwm_en & 0xC0) == 0))
00006a  0988              LSRS     r0,r1,#6
00006c  d108              BNE      |L9.128|
;;;285    		CLK->APBCLK &= ~CLK_APBCLK_PWM1_CH23_EN;
00006e  6890              LDR      r0,[r2,#8]
000070  2101              MOVS     r1,#1
000072  05c9              LSLS     r1,r1,#23
000074  e002              B        |L9.124|
                  |L9.118|
000076  6890              LDR      r0,[r2,#8]            ;281
000078  2101              MOVS     r1,#1                 ;281
00007a  0549              LSLS     r1,r1,#21             ;281
                  |L9.124|
00007c  4388              BICS     r0,r0,r1              ;279
00007e  6090              STR      r0,[r2,#8]            ;279
                  |L9.128|
;;;286    
;;;287    }
000080  bd70              POP      {r4-r6,pc}
                  |L9.130|
000082  6890              LDR      r0,[r2,#8]            ;283
000084  2101              MOVS     r1,#1                 ;283
000086  0589              LSLS     r1,r1,#22             ;283
000088  e7f8              B        |L9.124|
;;;288    
                          ENDP

00008a  0000              DCW      0x0000
                  |L9.140|
                          DCD      0x40040000
                  |L9.144|
                          DCD      0x40140000
                  |L9.148|
                          DCD      ||.data||
                  |L9.152|
                          DCD      0x50000200

                          AREA ||i.PWM_Disable||, CODE, READONLY, ALIGN=2

                  PWM_Disable PROC
;;;371      */
;;;372    void PWM_Disable(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;373    {
;;;374            PWM_TypeDef *base = (u8Ch< 4) ? PWM0 : PWM1;
000002  d201              BCS      |L10.8|
000004  4905              LDR      r1,|L10.28|
000006  e000              B        |L10.10|
                  |L10.8|
000008  4905              LDR      r1,|L10.32|
                  |L10.10|
;;;375    	assert_param(u8Ch < PWM_CH_NUM);
;;;376    
;;;377            base->CTL &= ~(1 << ((u8Ch & 0x3) * 8));
00000a  688a              LDR      r2,[r1,#8]
00000c  0780              LSLS     r0,r0,#30
00000e  0ec3              LSRS     r3,r0,#27
000010  2001              MOVS     r0,#1
000012  4098              LSLS     r0,r0,r3
000014  4382              BICS     r2,r2,r0
000016  608a              STR      r2,[r1,#8]
;;;378    
;;;379    }
000018  4770              BX       lr
;;;380    
                          ENDP

00001a  0000              DCW      0x0000
                  |L10.28|
                          DCD      0x40040000
                  |L10.32|
                          DCD      0x40140000

                          AREA ||i.PWM_DisableCaptureInt||, CODE, READONLY, ALIGN=2

                  PWM_DisableCaptureInt PROC
;;;125      */
;;;126    void PWM_DisableCaptureInt(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;127    {
;;;128            PWM_TypeDef *base;
;;;129            uint8_t ch;
;;;130    
;;;131    	assert_param(u8Ch < PWM_CH_NUM);
;;;132    
;;;133            base = (u8Ch < 4) ? PWM0 : PWM1;
000002  d201              BCS      |L11.8|
000004  4907              LDR      r1,|L11.36|
000006  e000              B        |L11.10|
                  |L11.8|
000008  4907              LDR      r1,|L11.40|
                  |L11.10|
;;;134            ch = u8Ch & 0x3;
00000a  0780              LSLS     r0,r0,#30
;;;135    
;;;136            base->CAPINTEN &= ~(0x3 << (ch * 8));
00000c  6d8a              LDR      r2,[r1,#0x58]
00000e  0ec0              LSRS     r0,r0,#27
000010  2303              MOVS     r3,#3
000012  4083              LSLS     r3,r3,r0
000014  439a              BICS     r2,r2,r3
000016  658a              STR      r2,[r1,#0x58]
;;;137            base->CAPINTSTS = 0x7 << (ch * 8);
000018  2207              MOVS     r2,#7
00001a  4082              LSLS     r2,r2,r0
00001c  65ca              STR      r2,[r1,#0x5c]
;;;138    
;;;139            if((base->INTEN & 0xF == 0) && (base->CAPINTEN & 0x03030303) == 0)
00001e  68c8              LDR      r0,[r1,#0xc]
;;;140    		NVIC_DisableIRQ(u8Ch < 0x04 ? PWM0_IRQn : PWM1_IRQn);
;;;141    }
000020  4770              BX       lr
;;;142    
                          ENDP

000022  0000              DCW      0x0000
                  |L11.36|
                          DCD      0x40040000
                  |L11.40|
                          DCD      0x40140000

                          AREA ||i.PWM_DisableDeadZone||, CODE, READONLY, ALIGN=2

                  PWM_DisableDeadZone PROC
;;;320      */
;;;321    void PWM_DisableDeadZone(uint8_t u8Ch)
000000  4908              LDR      r1,|L12.36|
;;;322    {
;;;323    	assert_param(u8Ch < PWM_CH_NUM);
;;;324    
;;;325    	if(u8Ch < 2) {
;;;326    		PWM0->CTL &= ~PWM_CTL_DZEN01;
000002  2310              MOVS     r3,#0x10
000004  2802              CMP      r0,#2                 ;325
000006  d305              BCC      |L12.20|
;;;327    	} else if(u8Ch < 4) {
;;;328    		PWM0->CTL &= ~PWM_CTL_DZEN23;
000008  2220              MOVS     r2,#0x20
00000a  2804              CMP      r0,#4                 ;327
00000c  d306              BCC      |L12.28|
;;;329    	} else if(u8Ch < 6) {
;;;330    		PWM1->CTL &= ~PWM_CTL_DZEN01;
00000e  4906              LDR      r1,|L12.40|
000010  2806              CMP      r0,#6                 ;329
000012  d203              BCS      |L12.28|
                  |L12.20|
000014  6888              LDR      r0,[r1,#8]
000016  4398              BICS     r0,r0,r3
                  |L12.24|
000018  6088              STR      r0,[r1,#8]            ;326
;;;331    	} else {
;;;332    		PWM1->CTL &= ~PWM_CTL_DZEN23;
;;;333            }
;;;334    }
00001a  4770              BX       lr
                  |L12.28|
00001c  6888              LDR      r0,[r1,#8]            ;332
00001e  4390              BICS     r0,r0,r2              ;332
000020  e7fa              B        |L12.24|
;;;335    
                          ENDP

000022  0000              DCW      0x0000
                  |L12.36|
                          DCD      0x40040000
                  |L12.40|
                          DCD      0x40140000

                          AREA ||i.PWM_DisableInt||, CODE, READONLY, ALIGN=2

                  PWM_DisableInt PROC
;;;73       */
;;;74     void PWM_DisableInt(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;75     {
;;;76             PWM_TypeDef *base;
;;;77             uint8_t ch;
;;;78     
;;;79     	assert_param(u8Ch < PWM_CH_NUM);
;;;80     
;;;81             base = (u8Ch < 4) ? PWM0 : PWM1;
000002  d201              BCS      |L13.8|
000004  4906              LDR      r1,|L13.32|
000006  e000              B        |L13.10|
                  |L13.8|
000008  4906              LDR      r1,|L13.36|
                  |L13.10|
;;;82             ch = u8Ch & 0x3;
00000a  0782              LSLS     r2,r0,#30
;;;83     
;;;84     
;;;85             base->INTEN &= ~(1 << ch);
00000c  68cb              LDR      r3,[r1,#0xc]
00000e  0f92              LSRS     r2,r2,#30             ;82
000010  2001              MOVS     r0,#1
000012  4090              LSLS     r0,r0,r2
000014  4383              BICS     r3,r3,r0
000016  60cb              STR      r3,[r1,#0xc]
;;;86             base->INTSTS = 1 << ch;
000018  6108              STR      r0,[r1,#0x10]
;;;87     
;;;88             if((base->INTEN & 0xF == 0) && (base->CAPINTEN & 0x03030303) == 0)
00001a  68c8              LDR      r0,[r1,#0xc]
;;;89     		NVIC_DisableIRQ(u8Ch < 0x04 ? PWM0_IRQn : PWM1_IRQn);
;;;90     
;;;91     
;;;92     }
00001c  4770              BX       lr
;;;93     
                          ENDP

00001e  0000              DCW      0x0000
                  |L13.32|
                          DCD      0x40040000
                  |L13.36|
                          DCD      0x40140000

                          AREA ||i.PWM_DisablePdma||, CODE, READONLY, ALIGN=2

                  PWM_DisablePdma PROC
;;;518      */
;;;519    void PWM_DisablePdma(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;520    {
;;;521            PWM_TypeDef *base = (u8Ch < 4) ? PWM0 : PWM1;
000002  d201              BCS      |L14.8|
000004  4905              LDR      r1,|L14.28|
000006  e000              B        |L14.10|
                  |L14.8|
000008  4905              LDR      r1,|L14.32|
                  |L14.10|
;;;522            uint8_t ch = u8Ch & 0x3;
00000a  0780              LSLS     r0,r0,#30
;;;523    
;;;524    	assert_param(u8Ch < PWM_CH_NUM);
;;;525    	assert_param((u8Ch & 1) == 0);
;;;526    
;;;527            base->CAPCTL &= ~(PWM_CAPCTL_CH0PDMAEN << (ch * 8));
00000c  6d4a              LDR      r2,[r1,#0x54]
00000e  0ec3              LSRS     r3,r0,#27
000010  2008              MOVS     r0,#8
000012  4098              LSLS     r0,r0,r3
000014  4382              BICS     r2,r2,r0
000016  654a              STR      r2,[r1,#0x54]
;;;528    
;;;529    }
000018  4770              BX       lr
;;;530    
                          ENDP

00001a  0000              DCW      0x0000
                  |L14.28|
                          DCD      0x40040000
                  |L14.32|
                          DCD      0x40140000

                          AREA ||i.PWM_Enable||, CODE, READONLY, ALIGN=2

                  PWM_Enable PROC
;;;340      */
;;;341    void PWM_Enable(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;342    {
;;;343            PWM_TypeDef *base = (u8Ch< 4) ? PWM0 : PWM1;
000002  d201              BCS      |L15.8|
000004  4905              LDR      r1,|L15.28|
000006  e000              B        |L15.10|
                  |L15.8|
000008  4905              LDR      r1,|L15.32|
                  |L15.10|
;;;344    	assert_param(u8Ch < PWM_CH_NUM);
;;;345    
;;;346            base->CTL |= (1 << ((u8Ch & 0x3) * 8));
00000a  688a              LDR      r2,[r1,#8]
00000c  0780              LSLS     r0,r0,#30
00000e  0ec3              LSRS     r3,r0,#27
000010  2001              MOVS     r0,#1
000012  4098              LSLS     r0,r0,r3
000014  4302              ORRS     r2,r2,r0
000016  608a              STR      r2,[r1,#8]
;;;347    
;;;348    }
000018  4770              BX       lr
;;;349    
                          ENDP

00001a  0000              DCW      0x0000
                  |L15.28|
                          DCD      0x40040000
                  |L15.32|
                          DCD      0x40140000

                          AREA ||i.PWM_EnableCaptureInt||, CODE, READONLY, ALIGN=2

                  PWM_EnableCaptureInt PROC
;;;98       */
;;;99     void PWM_EnableCaptureInt(uint8_t u8Ch, uint8_t u8Int)
000000  b570              PUSH     {r4-r6,lr}
;;;100    {
;;;101            PWM_TypeDef *base;
;;;102            uint8_t ch;
;;;103    
;;;104    	assert_param(u8Ch < PWM_CH_NUM);
;;;105    
;;;106            base = (u8Ch < 4) ? PWM0 : PWM1;
000002  2804              CMP      r0,#4
000004  d201              BCS      |L16.10|
000006  4a0c              LDR      r2,|L16.56|
000008  e000              B        |L16.12|
                  |L16.10|
00000a  4a0c              LDR      r2,|L16.60|
                  |L16.12|
;;;107            ch = u8Ch & 0x3;
00000c  0783              LSLS     r3,r0,#30
;;;108    
;;;109    
;;;110            base->CAPINTSTS = 0x7 << (ch * 8);
00000e  0edb              LSRS     r3,r3,#27
000010  2407              MOVS     r4,#7
000012  409c              LSLS     r4,r4,r3
000014  65d4              STR      r4,[r2,#0x5c]
;;;111            base->CAPINTEN &= ~(0x3 << (ch * 8));
000016  6d94              LDR      r4,[r2,#0x58]
000018  2503              MOVS     r5,#3
00001a  409d              LSLS     r5,r5,r3
00001c  43ac              BICS     r4,r4,r5
00001e  6594              STR      r4,[r2,#0x58]
;;;112            base->CAPINTEN |= ((u8Int) << (ch * 8));
000020  6d94              LDR      r4,[r2,#0x58]
000022  4099              LSLS     r1,r1,r3
000024  430c              ORRS     r4,r4,r1
000026  6594              STR      r4,[r2,#0x58]
;;;113    
;;;114    
;;;115            if (u8Ch < 0x04)
000028  2804              CMP      r0,#4
00002a  d201              BCS      |L16.48|
;;;116                    NVIC_EnableIRQ(PWM0_IRQn);
00002c  2006              MOVS     r0,#6
00002e  e000              B        |L16.50|
                  |L16.48|
;;;117            else
;;;118                    NVIC_EnableIRQ(PWM1_IRQn);
000030  2007              MOVS     r0,#7
                  |L16.50|
000032  f7fffffe          BL       NVIC_EnableIRQ
;;;119    }
000036  bd70              POP      {r4-r6,pc}
;;;120    
                          ENDP

                  |L16.56|
                          DCD      0x40040000
                  |L16.60|
                          DCD      0x40140000

                          AREA ||i.PWM_EnableDeadZone||, CODE, READONLY, ALIGN=2

                  PWM_EnableDeadZone PROC
;;;294      */
;;;295    void PWM_EnableDeadZone(uint8_t u8Ch, uint8_t u8Length)
000000  b570              PUSH     {r4-r6,lr}
;;;296    {
;;;297    	assert_param(u8Ch < PWM_CH_NUM);
;;;298    
;;;299    
;;;300    	if(u8Ch < 2) {
;;;301    		PWM0->PRES = (PWM0->PRES & ~PWM_PRES_DZ01_MASK) | u8Length;
000002  25ff              MOVS     r5,#0xff
000004  042d              LSLS     r5,r5,#16
;;;302    		PWM0->CTL |= PWM_CTL_DZEN01;
000006  2410              MOVS     r4,#0x10
000008  4a13              LDR      r2,|L17.88|
00000a  2802              CMP      r0,#2                 ;300
00000c  d206              BCS      |L17.28|
00000e  6810              LDR      r0,[r2,#0]            ;301
000010  43a8              BICS     r0,r0,r5              ;301
000012  4308              ORRS     r0,r0,r1              ;301
000014  6010              STR      r0,[r2,#0]            ;301
000016  6890              LDR      r0,[r2,#8]
000018  4320              ORRS     r0,r0,r4
00001a  e009              B        |L17.48|
                  |L17.28|
;;;303    	} else if(u8Ch < 4) {
;;;304    		PWM0->PRES = (PWM0->PRES & ~PWM_PRES_DZ23_MASK) | u8Length;
;;;305    		PWM0->CTL |= PWM_CTL_DZEN23;
00001c  2620              MOVS     r6,#0x20
00001e  2804              CMP      r0,#4                 ;303
000020  d208              BCS      |L17.52|
000022  6810              LDR      r0,[r2,#0]            ;304
000024  0200              LSLS     r0,r0,#8              ;304
000026  0a00              LSRS     r0,r0,#8              ;304
000028  4308              ORRS     r0,r0,r1              ;304
00002a  6010              STR      r0,[r2,#0]            ;304
00002c  6890              LDR      r0,[r2,#8]
00002e  4330              ORRS     r0,r0,r6
                  |L17.48|
000030  6090              STR      r0,[r2,#8]            ;302
;;;306    	} else if(u8Ch < 6) {
;;;307    		PWM1->PRES = (PWM0->PRES & ~PWM_PRES_DZ01_MASK) | u8Length;
;;;308    		PWM1->CTL |= PWM_CTL_DZEN01;
;;;309    	} else {
;;;310    		PWM1->PRES = (PWM0->PRES & ~PWM_PRES_DZ23_MASK) | u8Length;
;;;311    		PWM1->CTL |= PWM_CTL_DZEN23;
;;;312            }
;;;313    
;;;314    }
000032  bd70              POP      {r4-r6,pc}
                  |L17.52|
000034  2806              CMP      r0,#6                 ;306
000036  4b09              LDR      r3,|L17.92|
000038  6810              LDR      r0,[r2,#0]            ;310
00003a  d205              BCS      |L17.72|
00003c  43a8              BICS     r0,r0,r5              ;307
00003e  4308              ORRS     r0,r0,r1              ;307
000040  6018              STR      r0,[r3,#0]            ;307
000042  6898              LDR      r0,[r3,#8]            ;308
000044  4320              ORRS     r0,r0,r4              ;308
000046  e005              B        |L17.84|
                  |L17.72|
000048  0200              LSLS     r0,r0,#8              ;310
00004a  0a00              LSRS     r0,r0,#8              ;310
00004c  4308              ORRS     r0,r0,r1              ;310
00004e  6018              STR      r0,[r3,#0]            ;310
000050  6898              LDR      r0,[r3,#8]            ;311
000052  4330              ORRS     r0,r0,r6              ;311
                  |L17.84|
000054  6098              STR      r0,[r3,#8]            ;311
000056  bd70              POP      {r4-r6,pc}
;;;315    
                          ENDP

                  |L17.88|
                          DCD      0x40040000
                  |L17.92|
                          DCD      0x40140000

                          AREA ||i.PWM_EnableInt||, CODE, READONLY, ALIGN=2

                  PWM_EnableInt PROC
;;;47       */
;;;48     void PWM_EnableInt(uint8_t u8Ch)
000000  b510              PUSH     {r4,lr}
;;;49     {
;;;50             PWM_TypeDef *base;
;;;51             uint8_t ch;
;;;52     
;;;53     	assert_param(u8Ch < PWM_CH_NUM);
;;;54     
;;;55             base = (u8Ch < 4) ? PWM0 : PWM1;
000002  2804              CMP      r0,#4
000004  d201              BCS      |L18.10|
000006  4909              LDR      r1,|L18.44|
000008  e000              B        |L18.12|
                  |L18.10|
00000a  4909              LDR      r1,|L18.48|
                  |L18.12|
;;;56             ch = u8Ch & 0x3;
00000c  0783              LSLS     r3,r0,#30
00000e  0f9b              LSRS     r3,r3,#30
;;;57     
;;;58     
;;;59             base->INTSTS = 1 << ch;
000010  2201              MOVS     r2,#1
000012  409a              LSLS     r2,r2,r3
000014  610a              STR      r2,[r1,#0x10]
;;;60             base->INTEN |= 1 << ch;
000016  68cb              LDR      r3,[r1,#0xc]
000018  4313              ORRS     r3,r3,r2
00001a  60cb              STR      r3,[r1,#0xc]
;;;61     
;;;62     
;;;63             if (u8Ch < 0x04)
00001c  2804              CMP      r0,#4
00001e  d201              BCS      |L18.36|
;;;64                     NVIC_EnableIRQ(PWM0_IRQn);
000020  2006              MOVS     r0,#6
000022  e000              B        |L18.38|
                  |L18.36|
;;;65             else
;;;66                     NVIC_EnableIRQ(PWM1_IRQn);
000024  2007              MOVS     r0,#7
                  |L18.38|
000026  f7fffffe          BL       NVIC_EnableIRQ
;;;67     }
00002a  bd10              POP      {r4,pc}
;;;68     
                          ENDP

                  |L18.44|
                          DCD      0x40040000
                  |L18.48|
                          DCD      0x40140000

                          AREA ||i.PWM_EnablePdma||, CODE, READONLY, ALIGN=2

                  PWM_EnablePdma PROC
;;;495      */
;;;496    void PWM_EnablePdma(uint8_t u8Ch, uint32_t u32Order, uint32_t u32Mode)
000000  b530              PUSH     {r4,r5,lr}
;;;497    {
;;;498            PWM_TypeDef *base = (u8Ch < 4) ? PWM0 : PWM1;
000002  2804              CMP      r0,#4
000004  d201              BCS      |L19.10|
000006  4b0b              LDR      r3,|L19.52|
000008  e000              B        |L19.12|
                  |L19.10|
00000a  4b0b              LDR      r3,|L19.56|
                  |L19.12|
;;;499            uint8_t ch = u8Ch & 0x3;
00000c  0780              LSLS     r0,r0,#30
;;;500    	uint32_t reg;
;;;501    
;;;502    	assert_param(u8Ch < PWM_CH_NUM);
;;;503    	assert_param((u8Ch & 1) == 0);
;;;504    	assert_param((u32Order & ~PWM_CAPCTL_CH0RFORDER) == 0);
;;;505    	assert_param((u32Mode & ~PWM_CAPCTL_PDMACAPMOD_MASK) == 0);
;;;506    
;;;507    	reg = base->CAPCTL;
00000e  6d5d              LDR      r5,[r3,#0x54]
;;;508    	reg = (reg & ~PWM_CAPCTL_CH0RFORDER << (ch * 8)) | (u32Order << (ch * 8));
000010  4c0a              LDR      r4,|L19.60|
000012  0ec0              LSRS     r0,r0,#27
000014  4084              LSLS     r4,r4,r0
000016  402c              ANDS     r4,r4,r5
000018  4081              LSLS     r1,r1,r0
00001a  430c              ORRS     r4,r4,r1
;;;509    	reg = (reg & ~PWM_CAPCTL_PDMACAPMOD_MASK << (ch * 8)) | (u32Mode << (ch * 8));
00001c  2130              MOVS     r1,#0x30
00001e  43c9              MVNS     r1,r1
000020  4081              LSLS     r1,r1,r0
000022  4021              ANDS     r1,r1,r4
000024  4082              LSLS     r2,r2,r0
000026  4311              ORRS     r1,r1,r2
;;;510            base->CAPCTL = reg | (PWM_CAPCTL_CH0PDMAEN << (ch * 8));
000028  2208              MOVS     r2,#8
00002a  4082              LSLS     r2,r2,r0
00002c  430a              ORRS     r2,r2,r1
00002e  655a              STR      r2,[r3,#0x54]
;;;511    
;;;512    }
000030  bd30              POP      {r4,r5,pc}
;;;513    
                          ENDP

000032  0000              DCW      0x0000
                  |L19.52|
                          DCD      0x40040000
                  |L19.56|
                          DCD      0x40140000
                  |L19.60|
                          DCD      0xffffefff

                          AREA ||i.PWM_GetCaptureIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetCaptureIntFlag PROC
;;;192      */
;;;193    uint32_t PWM_GetCaptureIntFlag(uint8_t u8Ch)
000000  4905              LDR      r1,|L20.24|
;;;194    {
;;;195    
;;;196    	assert_param(u8Ch < PWM_CH_NUM);
;;;197    	if(u8Ch < 4)
000002  2804              CMP      r0,#4
000004  d201              BCS      |L20.10|
;;;198    		return(PWM0->CAPINTSTS >> ((u8Ch * 8) & 7));
000006  69c8              LDR      r0,[r1,#0x1c]
;;;199    	else
;;;200    		return((PWM0->CAPINTSTS >> ((u8Ch & 3) * 8)) & 7);
;;;201    }
000008  4770              BX       lr
                  |L20.10|
00000a  69c9              LDR      r1,[r1,#0x1c]         ;200
00000c  0780              LSLS     r0,r0,#30             ;200
00000e  0ec0              LSRS     r0,r0,#27             ;200
000010  40c1              LSRS     r1,r1,r0              ;200
000012  0748              LSLS     r0,r1,#29             ;200
000014  0f40              LSRS     r0,r0,#29             ;200
000016  4770              BX       lr
;;;202    
                          ENDP

                  |L20.24|
                          DCD      0x40040040

                          AREA ||i.PWM_GetFallingCounter||, CODE, READONLY, ALIGN=2

                  PWM_GetFallingCounter PROC
;;;223      */
;;;224    uint32_t PWM_GetFallingCounter(uint8_t u8Ch)
000000  0781              LSLS     r1,r0,#30
;;;225    {
;;;226    	assert_param(u8Ch < PWM_CH_NUM);
;;;227            if (u8Ch < 4) {
;;;228            	return(*(uint32_t *)(&PWM0->CFL0 + 0x2 * (u8Ch & 0x3)));
000002  0ec9              LSRS     r1,r1,#27
000004  2804              CMP      r0,#4                 ;227
000006  d201              BCS      |L21.12|
000008  4802              LDR      r0,|L21.20|
00000a  e000              B        |L21.14|
                  |L21.12|
;;;229            } else {
;;;230                    return(*(uint32_t *)(&PWM1->CFL0 + 0x2 * (u8Ch & 0x3)));
00000c  4802              LDR      r0,|L21.24|
                  |L21.14|
00000e  1808              ADDS     r0,r1,r0
000010  6a40              LDR      r0,[r0,#0x24]
;;;231            }
;;;232    }
000012  4770              BX       lr
;;;233    
                          ENDP

                  |L21.20|
                          DCD      0x40040040
                  |L21.24|
                          DCD      0x40140040

                          AREA ||i.PWM_GetIntFlag||, CODE, READONLY, ALIGN=2

                  PWM_GetIntFlag PROC
;;;177      */
;;;178    uint32_t PWM_GetIntFlag(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;179    {
;;;180    
;;;181    	assert_param(u8Ch < PWM_CH_NUM);
;;;182    	if(u8Ch < 4)
000002  d202              BCS      |L22.10|
;;;183    		return((PWM0->INTSTS >> u8Ch) & 1);
000004  4905              LDR      r1,|L22.28|
000006  6909              LDR      r1,[r1,#0x10]
000008  e003              B        |L22.18|
                  |L22.10|
;;;184    	else
;;;185    		return((PWM1->INTSTS >> (u8Ch & 3)) & 1);
00000a  4905              LDR      r1,|L22.32|
00000c  6909              LDR      r1,[r1,#0x10]
00000e  0780              LSLS     r0,r0,#30
000010  0f80              LSRS     r0,r0,#30
                  |L22.18|
000012  40c1              LSRS     r1,r1,r0
000014  07c8              LSLS     r0,r1,#31
000016  0fc0              LSRS     r0,r0,#31
;;;186    }
000018  4770              BX       lr
;;;187    
                          ENDP

00001a  0000              DCW      0x0000
                  |L22.28|
                          DCD      0x40040000
                  |L22.32|
                          DCD      0x40140000

                          AREA ||i.PWM_GetRisingCounter||, CODE, READONLY, ALIGN=2

                  PWM_GetRisingCounter PROC
;;;208      */
;;;209    uint32_t PWM_GetRisingCounter(uint8_t u8Ch)
000000  2804              CMP      r0,#4
;;;210    {
;;;211    	assert_param(u8Ch < PWM_CH_NUM);
;;;212            if (u8Ch < 4) {
000002  d202              BCS      |L23.10|
;;;213            	return(*(uint32_t *)(&PWM0->CRL0 + 0x2 * u8Ch));
000004  00c0              LSLS     r0,r0,#3
000006  4904              LDR      r1,|L23.24|
000008  e002              B        |L23.16|
                  |L23.10|
;;;214            } else {
;;;215                    return(*(uint32_t *)(&PWM1->CRL0 + 0x2 * (u8Ch & 0x3)));
00000a  0780              LSLS     r0,r0,#30
00000c  4903              LDR      r1,|L23.28|
00000e  0ec0              LSRS     r0,r0,#27
                  |L23.16|
000010  1840              ADDS     r0,r0,r1
000012  6a00              LDR      r0,[r0,#0x20]
;;;216            }
;;;217    }
000014  4770              BX       lr
;;;218    
                          ENDP

000016  0000              DCW      0x0000
                  |L23.24|
                          DCD      0x40040040
                  |L23.28|
                          DCD      0x40140040

                          AREA ||i.PWM_Init||, CODE, READONLY, ALIGN=2

                  PWM_Init PROC
;;;238      */
;;;239    void PWM_Init(uint8_t u8Ch)
000000  490e              LDR      r1,|L24.60|
;;;240    {
;;;241    	assert_param(u8Ch < PWM_CH_NUM);
;;;242    	if(u8Ch < 2)
000002  2802              CMP      r0,#2
000004  d202              BCS      |L24.12|
;;;243    		CLK->APBCLK |= CLK_APBCLK_PWM0_CH01_EN;
000006  688a              LDR      r2,[r1,#8]
000008  02cb              LSLS     r3,r1,#11
00000a  e00d              B        |L24.40|
                  |L24.12|
;;;244    	else if(u8Ch < 4)
00000c  2804              CMP      r0,#4
00000e  d203              BCS      |L24.24|
;;;245    		CLK->APBCLK |= CLK_APBCLK_PWM0_CH23_EN;
000010  688a              LDR      r2,[r1,#8]
000012  2301              MOVS     r3,#1
000014  055b              LSLS     r3,r3,#21
000016  e007              B        |L24.40|
                  |L24.24|
;;;246    	else if(u8Ch < 6)
;;;247    		CLK->APBCLK |= CLK_APBCLK_PWM1_CH01_EN;
;;;248    	else
;;;249    		CLK->APBCLK |= CLK_APBCLK_PWM1_CH23_EN;
000018  688a              LDR      r2,[r1,#8]
00001a  2806              CMP      r0,#6                 ;246
00001c  d202              BCS      |L24.36|
00001e  2301              MOVS     r3,#1                 ;247
000020  059b              LSLS     r3,r3,#22             ;247
000022  e001              B        |L24.40|
                  |L24.36|
000024  2301              MOVS     r3,#1
000026  05db              LSLS     r3,r3,#23
                  |L24.40|
000028  431a              ORRS     r2,r2,r3              ;247
00002a  608a              STR      r2,[r1,#8]            ;247
;;;250    	pwm_en |= (1 << u8Ch);
00002c  2101              MOVS     r1,#1
00002e  4081              LSLS     r1,r1,r0
000030  4803              LDR      r0,|L24.64|
000032  7802              LDRB     r2,[r0,#0]  ; pwm_en
000034  4311              ORRS     r1,r1,r2
000036  7001              STRB     r1,[r0,#0]
;;;251    }
000038  4770              BX       lr
;;;252    
                          ENDP

00003a  0000              DCW      0x0000
                  |L24.60|
                          DCD      0x50000200
                  |L24.64|
                          DCD      ||.data||

                          AREA ||i.PWM_SetCaptureAttribute||, CODE, READONLY, ALIGN=2

                  PWM_SetCaptureAttribute PROC
;;;538      */
;;;539    void PWM_SetCaptureAttribute(uint8_t u8Ch, uint8_t u8Inv, uint8_t u8Cas, uint32_t u32Reload)
000000  b5f0              PUSH     {r4-r7,lr}
;;;540    {
000002  4694              MOV      r12,r2
;;;541    
;;;542            PWM_TypeDef *base = (u8Ch < 4) ? PWM0 : PWM1;
000004  2804              CMP      r0,#4
000006  d201              BCS      |L25.12|
000008  4d11              LDR      r5,|L25.80|
00000a  e000              B        |L25.14|
                  |L25.12|
00000c  4d11              LDR      r5,|L25.84|
                  |L25.14|
;;;543            uint8_t ch = u8Ch & 0x3;
00000e  0787              LSLS     r7,r0,#30
;;;544            uint32_t reg;
;;;545    
;;;546    	assert_param(u8Ch < PWM_CH_NUM);
;;;547            assert_param(!((ch % 2) && (u8Cas))) // cascade mode support channel 0 & 2 only
;;;548    	assert_param((u32Reload & PWM_CAPCTL_CAPRELOADREN) || (u32Reload & PWM_CAPCTL_CAPRELOADFEN));
;;;549    
;;;550    	reg = base->CAPCTL;
000010  6d6c              LDR      r4,[r5,#0x54]
000012  0fbf              LSRS     r7,r7,#30             ;543
;;;551    
;;;552            if(u8Inv)
000014  460a              MOV      r2,r1
000016  0786              LSLS     r6,r0,#30             ;543
;;;553                    reg |= 1 << (8 * ch);
000018  2101              MOVS     r1,#1
00001a  0ef6              LSRS     r6,r6,#27
00001c  40b1              LSLS     r1,r1,r6
00001e  2a00              CMP      r2,#0                 ;552
000020  d001              BEQ      |L25.38|
000022  430c              ORRS     r4,r4,r1
000024  e000              B        |L25.40|
                  |L25.38|
;;;554            else
;;;555                    reg &= ~(1 << (8 * ch));
000026  438c              BICS     r4,r4,r1
                  |L25.40|
;;;556    
;;;557            if(u8Cas)
;;;558                    reg |= 0x2000 << (8 * ch);
000028  2201              MOVS     r2,#1
00002a  0352              LSLS     r2,r2,#13
00002c  0780              LSLS     r0,r0,#30             ;543
00002e  0ec0              LSRS     r0,r0,#27             ;553
000030  4661              MOV      r1,r12                ;557
000032  4082              LSLS     r2,r2,r0
000034  2900              CMP      r1,#0                 ;557
000036  d001              BEQ      |L25.60|
000038  4314              ORRS     r4,r4,r2
00003a  e002              B        |L25.66|
                  |L25.60|
;;;559            else  if((ch % 2) == 0)
00003c  07f8              LSLS     r0,r7,#31
00003e  d100              BNE      |L25.66|
;;;560                    reg &= ~(0x2000 << (8 * ch));
000040  4394              BICS     r4,r4,r2
                  |L25.66|
;;;561    
;;;562            reg = (reg & ~(PWM_CAPCTL_CAPRELOAD_MASK << (8 * ch))) | (u32Reload  << (8 * ch));
000042  20c0              MOVS     r0,#0xc0
000044  40b0              LSLS     r0,r0,r6
000046  4384              BICS     r4,r4,r0
000048  40b3              LSLS     r3,r3,r6
00004a  431c              ORRS     r4,r4,r3
;;;563    	base->CAPCTL = reg;
00004c  656c              STR      r4,[r5,#0x54]
;;;564    
;;;565    }
00004e  bdf0              POP      {r4-r7,pc}
                          ENDP

                  |L25.80|
                          DCD      0x40040000
                  |L25.84|
                          DCD      0x40140000

                          AREA ||i.PWM_SetClk||, CODE, READONLY, ALIGN=2

                  PWM_SetClk PROC
;;;403      */
;;;404    void PWM_SetClk(uint8_t u8Ch, S_DRVPWM_TIME_DATA_T *cfg)
000000  b530              PUSH     {r4,r5,lr}
;;;405    {
;;;406    	PWM_TypeDef *base = (u8Ch< 4) ? PWM0 : PWM1;
000002  2804              CMP      r0,#4
000004  d201              BCS      |L26.10|
000006  4a18              LDR      r2,|L26.104|
000008  e000              B        |L26.12|
                  |L26.10|
00000a  4a18              LDR      r2,|L26.108|
                  |L26.12|
;;;407    	uint8_t ch = u8Ch & 3;
00000c  0780              LSLS     r0,r0,#30
;;;408    	uint32_t reg;
;;;409    	assert_param(u8Ch < PWM_CH_NUM);
;;;410    
;;;411    
;;;412    	reg = base->CTL & ~(0xC << (ch * 8));
00000e  6893              LDR      r3,[r2,#8]
000010  0f80              LSRS     r0,r0,#30             ;407
000012  00c4              LSLS     r4,r0,#3
000014  250c              MOVS     r5,#0xc
000016  40a5              LSLS     r5,r5,r4
000018  43ab              BICS     r3,r3,r5
;;;413    	if(cfg->u8Inv)
00001a  7a4d              LDRB     r5,[r1,#9]
00001c  2d00              CMP      r5,#0
00001e  d002              BEQ      |L26.38|
;;;414    		reg |= (0x4 << (ch * 8));
000020  2504              MOVS     r5,#4
000022  40a5              LSLS     r5,r5,r4
000024  432b              ORRS     r3,r3,r5
                  |L26.38|
;;;415    	base->CTL = reg | (cfg->u8Mode << (ch * 8));
000026  798d              LDRB     r5,[r1,#6]
000028  40a5              LSLS     r5,r5,r4
00002a  431d              ORRS     r5,r5,r3
00002c  6095              STR      r5,[r2,#8]
;;;416    
;;;417    	reg = base->PRES & ~(0xFF << ((ch >> 1) * 8));
00002e  6814              LDR      r4,[r2,#0]
000030  0843              LSRS     r3,r0,#1
000032  00db              LSLS     r3,r3,#3
000034  25ff              MOVS     r5,#0xff
000036  409d              LSLS     r5,r5,r3
000038  43ac              BICS     r4,r4,r5
;;;418    	base->PRES = reg | (cfg->u8PreScale << ((ch >> 1) * 8));
00003a  79cd              LDRB     r5,[r1,#7]
00003c  409d              LSLS     r5,r5,r3
00003e  4325              ORRS     r5,r5,r4
000040  6015              STR      r5,[r2,#0]
;;;419    
;;;420    	reg = base->CLKSEL & ~(0x7 << (ch * 4));
000042  6854              LDR      r4,[r2,#4]
000044  0083              LSLS     r3,r0,#2
000046  2507              MOVS     r5,#7
000048  409d              LSLS     r5,r5,r3
00004a  43ac              BICS     r4,r4,r5
;;;421    	base->CLKSEL = reg | (cfg->u8Div << (ch * 4));
00004c  7a0d              LDRB     r5,[r1,#8]
00004e  409d              LSLS     r5,r5,r3
000050  4325              ORRS     r5,r5,r4
000052  6055              STR      r5,[r2,#4]
;;;422    
;;;423    	*(__IO uint32_t *) (&base->DUTY0 + 0x3 * ch) = ((cfg->u16Cm << 16) | cfg->u32Cn);
000054  888b              LDRH     r3,[r1,#4]
000056  6809              LDR      r1,[r1,#0]
000058  041b              LSLS     r3,r3,#16
00005a  430b              ORRS     r3,r3,r1
00005c  210c              MOVS     r1,#0xc
00005e  4348              MULS     r0,r1,r0
000060  1880              ADDS     r0,r0,r2
000062  61c3              STR      r3,[r0,#0x1c]
;;;424    
;;;425    
;;;426    }
000064  bd30              POP      {r4,r5,pc}
;;;427    
                          ENDP

000066  0000              DCW      0x0000
                  |L26.104|
                          DCD      0x40040000
                  |L26.108|
                          DCD      0x40140000

                          AREA ||i.PWM_SetCounter||, CODE, READONLY, ALIGN=2

                  PWM_SetCounter PROC
;;;31       */
;;;32     void PWM_SetCounter(uint8_t u8Ch, uint32_t u32Cn, uint16_t u16Cm)
000000  0412              LSLS     r2,r2,#16
;;;33     {
;;;34     	assert_param(u8Ch < PWM_CH_NUM);
;;;35             if (u8Ch < 4) {
;;;36                     *(__IO uint32_t *) (&PWM0->DUTY0 + 0x3 * u8Ch) = ((u16Cm << 16) | u32Cn);
000002  430a              ORRS     r2,r2,r1
000004  210c              MOVS     r1,#0xc
000006  4603              MOV      r3,r0
000008  434b              MULS     r3,r1,r3
00000a  2804              CMP      r0,#4                 ;35
00000c  d203              BCS      |L27.22|
00000e  4804              LDR      r0,|L27.32|
000010  1818              ADDS     r0,r3,r0
000012  61c2              STR      r2,[r0,#0x1c]
;;;37             } else {
;;;38                     *(__IO uint32_t *) (&PWM1->DUTY0 + 0x3 * (u8Ch - 4)) = ((u16Cm << 16) | u32Cn);
;;;39             }
;;;40     }
000014  4770              BX       lr
                  |L27.22|
000016  4803              LDR      r0,|L27.36|
000018  1818              ADDS     r0,r3,r0              ;38
00001a  62c2              STR      r2,[r0,#0x2c]         ;38
00001c  4770              BX       lr
;;;41     
                          ENDP

00001e  0000              DCW      0x0000
                  |L27.32|
                          DCD      0x40040000
                  |L27.36|
                          DCD      0x4013ffc0

                          AREA ||.data||, DATA, ALIGN=0

                  pwm_en
000000  00                DCB      0x00

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_pwm.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_pwm_c_38fd08df____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___13_nano1xx_pwm_c_38fd08df____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_pwm_c_38fd08df____REVSH|
#line 130
|__asm___13_nano1xx_pwm_c_38fd08df____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
