; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\nano1xx_spi.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\nano1xx_spi.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\nano1xx_spi.crf ..\bsp\Driver\nano1xx_spi.c]
                          THUMB

                          AREA ||i.NVIC_DisableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_DisableIRQ PROC
;;;511     */
;;;512    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;513    {
;;;514      NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L1.16|
00000a  6008              STR      r0,[r1,#0]
;;;515    }
00000c  4770              BX       lr
;;;516    
                          ENDP

00000e  0000              DCW      0x0000
                  |L1.16|
                          DCD      0xe000e180

                          AREA ||i.NVIC_EnableIRQ||, CODE, READONLY, ALIGN=2

                  NVIC_EnableIRQ PROC
;;;499     */
;;;500    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
000000  06c1              LSLS     r1,r0,#27
;;;501    {
;;;502      NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
000002  0ec9              LSRS     r1,r1,#27
000004  2001              MOVS     r0,#1
000006  4088              LSLS     r0,r0,r1
000008  4901              LDR      r1,|L2.16|
00000a  6008              STR      r0,[r1,#0]
;;;503    }
00000c  4770              BX       lr
;;;504    
                          ENDP

00000e  0000              DCW      0x0000
                  |L2.16|
                          DCD      0xe000e100

                          AREA ||i.NVIC_SetPriority||, CODE, READONLY, ALIGN=2

                  NVIC_SetPriority PROC
;;;566     */
;;;567    __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
000000  0783              LSLS     r3,r0,#30
;;;568    {
;;;569      if(IRQn < 0) {
;;;570        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
000002  22ff              MOVS     r2,#0xff
000004  0edb              LSRS     r3,r3,#27
000006  409a              LSLS     r2,r2,r3
000008  0789              LSLS     r1,r1,#30
00000a  0e09              LSRS     r1,r1,#24
00000c  4099              LSLS     r1,r1,r3
00000e  2800              CMP      r0,#0                 ;569
000010  da0b              BGE      |L3.42|
000012  0700              LSLS     r0,r0,#28
000014  0f00              LSRS     r0,r0,#28
000016  3808              SUBS     r0,r0,#8
000018  0883              LSRS     r3,r0,#2
00001a  4808              LDR      r0,|L3.60|
00001c  009b              LSLS     r3,r3,#2
00001e  1818              ADDS     r0,r3,r0
000020  69c3              LDR      r3,[r0,#0x1c]
000022  4393              BICS     r3,r3,r2
000024  430b              ORRS     r3,r3,r1
000026  61c3              STR      r3,[r0,#0x1c]
;;;571            (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
;;;572      else {
;;;573        NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
;;;574            (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
;;;575    }
000028  4770              BX       lr
                  |L3.42|
00002a  0883              LSRS     r3,r0,#2              ;573
00002c  4804              LDR      r0,|L3.64|
00002e  009b              LSLS     r3,r3,#2              ;573
000030  1818              ADDS     r0,r3,r0              ;573
000032  6803              LDR      r3,[r0,#0]            ;573
000034  4393              BICS     r3,r3,r2              ;573
000036  430b              ORRS     r3,r3,r1              ;573
000038  6003              STR      r3,[r0,#0]            ;573
00003a  4770              BX       lr
;;;576    
                          ENDP

                  |L3.60|
                          DCD      0xe000ed00
                  |L3.64|
                          DCD      0xe000e400

                          AREA ||i.SPI_Close||, CODE, READONLY, ALIGN=2

                  SPI_Close PROC
;;;166      */  
;;;167    void SPI_Close(SPI_TypeDef *SpiPort)
000000  4908              LDR      r1,|L4.36|
;;;168    {
000002  b510              PUSH     {r4,lr}
;;;169    	if((uint32_t)SpiPort == SPI0_BASE)
000004  4288              CMP      r0,r1
000006  d101              BNE      |L4.12|
;;;170    		NVIC_DisableIRQ(SPI0_IRQn);	
000008  200e              MOVS     r0,#0xe
00000a  e003              B        |L4.20|
                  |L4.12|
;;;171    	else if((uint32_t)SpiPort == SPI1_BASE)
00000c  4906              LDR      r1,|L4.40|
00000e  4288              CMP      r0,r1
000010  d103              BNE      |L4.26|
;;;172    		NVIC_DisableIRQ(SPI1_IRQn);		
000012  200f              MOVS     r0,#0xf
                  |L4.20|
000014  f7fffffe          BL       NVIC_DisableIRQ
                  |L4.24|
;;;173    	else if((uint32_t)SpiPort == SPI2_BASE)
;;;174    		NVIC_DisableIRQ(SPI2_IRQn);			
;;;175    }
000018  bd10              POP      {r4,pc}
                  |L4.26|
00001a  4904              LDR      r1,|L4.44|
00001c  4288              CMP      r0,r1                 ;173
00001e  d1fb              BNE      |L4.24|
000020  2010              MOVS     r0,#0x10              ;174
000022  e7f7              B        |L4.20|
;;;176    
                          ENDP

                  |L4.36|
                          DCD      0x40030000
                  |L4.40|
                          DCD      0x40130000
                  |L4.44|
                          DCD      0x400d0000

                          AREA ||i.SPI_DeInit||, CODE, READONLY, ALIGN=2

                  SPI_DeInit PROC
;;;45       */
;;;46     void SPI_DeInit(SPI_TypeDef *SpiPort)
000000  4a0b              LDR      r2,|L5.48|
;;;47     {	
;;;48     	if((uint32_t)SpiPort == SPI0_BASE)
;;;49     		CLK->APBCLK &= ~CLK_APBCLK_SPI0_EN;
000002  490c              LDR      r1,|L5.52|
000004  4290              CMP      r0,r2                 ;48
000006  d102              BNE      |L5.14|
000008  6888              LDR      r0,[r1,#8]
00000a  1492              ASRS     r2,r2,#18
00000c  e005              B        |L5.26|
                  |L5.14|
;;;50     	else if((uint32_t)SpiPort == SPI1_BASE)
00000e  4a0a              LDR      r2,|L5.56|
000010  4290              CMP      r0,r2
000012  d105              BNE      |L5.32|
;;;51     		CLK->APBCLK &= ~CLK_APBCLK_SPI1_EN;
000014  6888              LDR      r0,[r1,#8]
000016  2201              MOVS     r2,#1
000018  0352              LSLS     r2,r2,#13
                  |L5.26|
00001a  4390              BICS     r0,r0,r2              ;49
00001c  6088              STR      r0,[r1,#8]            ;49
                  |L5.30|
;;;52     	else if((uint32_t)SpiPort == SPI2_BASE)
;;;53     		CLK->APBCLK &= ~CLK_APBCLK_SPI2_EN;	
;;;54     }
00001e  4770              BX       lr
                  |L5.32|
000020  4a06              LDR      r2,|L5.60|
000022  4290              CMP      r0,r2                 ;52
000024  d1fb              BNE      |L5.30|
000026  6888              LDR      r0,[r1,#8]            ;53
000028  2201              MOVS     r2,#1                 ;53
00002a  0392              LSLS     r2,r2,#14             ;53
00002c  e7f5              B        |L5.26|
;;;55     
                          ENDP

00002e  0000              DCW      0x0000
                  |L5.48|
                          DCD      0x40030000
                  |L5.52|
                          DCD      0x50000200
                  |L5.56|
                          DCD      0x40130000
                  |L5.60|
                          DCD      0x400d0000

                          AREA ||i.SPI_Disable3WireStartInt||, CODE, READONLY, ALIGN=2

                  SPI_Disable3WireStartInt PROC
;;;464      */
;;;465    void SPI_Disable3WireStartInt(SPI_TypeDef *SpiPort)
000000  b510              PUSH     {r4,lr}
;;;466    {    
;;;467        SpiPort->SSR &= ~SPI_SSR_SSTA_INTEN;
000002  68c1              LDR      r1,[r0,#0xc]
000004  2201              MOVS     r2,#1
000006  0252              LSLS     r2,r2,#9
000008  4391              BICS     r1,r1,r2
00000a  60c1              STR      r1,[r0,#0xc]
;;;468        
;;;469        if((uint32_t)SpiPort == SPI0_BASE)	
00000c  4908              LDR      r1,|L6.48|
00000e  4288              CMP      r0,r1
000010  d101              BNE      |L6.22|
;;;470    		NVIC_DisableIRQ(SPI0_IRQn);
000012  200e              MOVS     r0,#0xe
000014  e003              B        |L6.30|
                  |L6.22|
;;;471    	else if((uint32_t)SpiPort == SPI1_BASE)	
000016  4907              LDR      r1,|L6.52|
000018  4288              CMP      r0,r1
00001a  d103              BNE      |L6.36|
;;;472    		NVIC_DisableIRQ(SPI1_IRQn);
00001c  200f              MOVS     r0,#0xf
                  |L6.30|
00001e  f7fffffe          BL       NVIC_DisableIRQ
                  |L6.34|
;;;473    	else if((uint32_t)SpiPort == SPI2_BASE)		
;;;474    		NVIC_DisableIRQ(SPI2_IRQn);   
;;;475    }
000022  bd10              POP      {r4,pc}
                  |L6.36|
000024  4904              LDR      r1,|L6.56|
000026  4288              CMP      r0,r1                 ;473
000028  d1fb              BNE      |L6.34|
00002a  2010              MOVS     r0,#0x10              ;474
00002c  e7f7              B        |L6.30|
;;;476    
                          ENDP

00002e  0000              DCW      0x0000
                  |L6.48|
                          DCD      0x40030000
                  |L6.52|
                          DCD      0x40130000
                  |L6.56|
                          DCD      0x400d0000

                          AREA ||i.SPI_DisableInt||, CODE, READONLY, ALIGN=2

                  SPI_DisableInt PROC
;;;321      */
;;;322    void SPI_DisableInt(SPI_TypeDef *SpiPort)
000000  b510              PUSH     {r4,lr}
;;;323    {
;;;324    	SpiPort->CTL &= ~SPI_CTL_INTEN;
000002  6801              LDR      r1,[r0,#0]
000004  2201              MOVS     r2,#1
000006  0452              LSLS     r2,r2,#17
000008  4391              BICS     r1,r1,r2
00000a  6001              STR      r1,[r0,#0]
;;;325    
;;;326    	if((uint32_t)SpiPort == SPI0_BASE)	
00000c  4908              LDR      r1,|L7.48|
00000e  4288              CMP      r0,r1
000010  d101              BNE      |L7.22|
;;;327    		NVIC_DisableIRQ(SPI0_IRQn);
000012  200e              MOVS     r0,#0xe
000014  e003              B        |L7.30|
                  |L7.22|
;;;328    	else if((uint32_t)SpiPort == SPI1_BASE)	
000016  4907              LDR      r1,|L7.52|
000018  4288              CMP      r0,r1
00001a  d103              BNE      |L7.36|
;;;329    		NVIC_DisableIRQ(SPI1_IRQn);
00001c  200f              MOVS     r0,#0xf
                  |L7.30|
00001e  f7fffffe          BL       NVIC_DisableIRQ
                  |L7.34|
;;;330    	else if((uint32_t)SpiPort == SPI2_BASE)		
;;;331    		NVIC_DisableIRQ(SPI2_IRQn);
;;;332    }
000022  bd10              POP      {r4,pc}
                  |L7.36|
000024  4904              LDR      r1,|L7.56|
000026  4288              CMP      r0,r1                 ;330
000028  d1fb              BNE      |L7.34|
00002a  2010              MOVS     r0,#0x10              ;331
00002c  e7f7              B        |L7.30|
;;;333    
                          ENDP

00002e  0000              DCW      0x0000
                  |L7.48|
                          DCD      0x40030000
                  |L7.52|
                          DCD      0x40130000
                  |L7.56|
                          DCD      0x400d0000

                          AREA ||i.SPI_DumpRxRegister||, CODE, READONLY, ALIGN=1

                  SPI_DumpRxRegister PROC
;;;374      */
;;;375    uint32_t SPI_DumpRxRegister(SPI_TypeDef *SpiPort, uint32_t *pu32Buf, uint32_t u32DataCount)
000000  6903              LDR      r3,[r0,#0x10]
;;;376    {
;;;377    	assert_param(SPI_CHECK_SET_DATAREG_NUM);
;;;378    	
;;;379    	pu32Buf[0] = SpiPort->RX0;
;;;380    	
;;;381    	if(u32DataCount == 2)
000002  600b              STR      r3,[r1,#0]
000004  2a02              CMP      r2,#2
000006  d101              BNE      |L8.12|
;;;382    		pu32Buf[1] = SpiPort->RX1;
000008  6940              LDR      r0,[r0,#0x14]
00000a  6048              STR      r0,[r1,#4]
                  |L8.12|
;;;383    	
;;;384        return u32DataCount;
00000c  4610              MOV      r0,r2
;;;385    }
00000e  4770              BX       lr
;;;386    
                          ENDP


                          AREA ||i.SPI_Enable3WireStartInt||, CODE, READONLY, ALIGN=2

                  SPI_Enable3WireStartInt PROC
;;;438      */
;;;439    void SPI_Enable3WireStartInt(SPI_TypeDef *SpiPort)
000000  b510              PUSH     {r4,lr}
;;;440    { 
;;;441        SpiPort->SSR |= SPI_SSR_SSTA_INTEN;
000002  68c1              LDR      r1,[r0,#0xc]
000004  2201              MOVS     r2,#1
000006  0252              LSLS     r2,r2,#9
000008  4311              ORRS     r1,r1,r2
00000a  60c1              STR      r1,[r0,#0xc]
;;;442    
;;;443        if((uint32_t)SpiPort == SPI0_BASE)	
00000c  490e              LDR      r1,|L9.72|
00000e  4288              CMP      r0,r1
000010  d105              BNE      |L9.30|
;;;444    	{
;;;445    		NVIC_EnableIRQ(SPI0_IRQn);
000012  200e              MOVS     r0,#0xe
000014  f7fffffe          BL       NVIC_EnableIRQ
;;;446    		NVIC_SetPriority(SPI0_IRQn, (1<<__NVIC_PRIO_BITS) - 2);
000018  2102              MOVS     r1,#2
00001a  200e              MOVS     r0,#0xe
00001c  e007              B        |L9.46|
                  |L9.30|
;;;447    	}
;;;448    	else if((uint32_t)SpiPort == SPI1_BASE)	
00001e  490b              LDR      r1,|L9.76|
000020  4288              CMP      r0,r1
000022  d107              BNE      |L9.52|
;;;449    	{	
;;;450    		NVIC_EnableIRQ(SPI1_IRQn);
000024  200f              MOVS     r0,#0xf
000026  f7fffffe          BL       NVIC_EnableIRQ
;;;451    		NVIC_SetPriority(SPI1_IRQn, (1<<__NVIC_PRIO_BITS) - 2);
00002a  2102              MOVS     r1,#2
00002c  200f              MOVS     r0,#0xf
                  |L9.46|
00002e  f7fffffe          BL       NVIC_SetPriority
                  |L9.50|
;;;452    	}
;;;453    	else if((uint32_t)SpiPort == SPI2_BASE)
;;;454    	{	
;;;455    		NVIC_EnableIRQ(SPI2_IRQn);
;;;456    		NVIC_SetPriority(SPI2_IRQn, (1<<__NVIC_PRIO_BITS) - 2);
;;;457    	}
;;;458    }   
000032  bd10              POP      {r4,pc}
                  |L9.52|
000034  4906              LDR      r1,|L9.80|
000036  4288              CMP      r0,r1                 ;453
000038  d1fb              BNE      |L9.50|
00003a  2010              MOVS     r0,#0x10              ;455
00003c  f7fffffe          BL       NVIC_EnableIRQ
000040  2102              MOVS     r1,#2                 ;456
000042  2010              MOVS     r0,#0x10              ;456
000044  e7f3              B        |L9.46|
;;;459    
                          ENDP

000046  0000              DCW      0x0000
                  |L9.72|
                          DCD      0x40030000
                  |L9.76|
                          DCD      0x40130000
                  |L9.80|
                          DCD      0x400d0000

                          AREA ||i.SPI_EnableInt||, CODE, READONLY, ALIGN=2

                  SPI_EnableInt PROC
;;;304      */
;;;305    void SPI_EnableInt(SPI_TypeDef *SpiPort)
000000  b510              PUSH     {r4,lr}
;;;306    {	
;;;307    	SpiPort->CTL |= SPI_CTL_INTEN;
000002  6801              LDR      r1,[r0,#0]
000004  2201              MOVS     r2,#1
000006  0452              LSLS     r2,r2,#17
000008  4311              ORRS     r1,r1,r2
00000a  6001              STR      r1,[r0,#0]
;;;308    	
;;;309    	if((uint32_t)SpiPort == SPI0_BASE)	
00000c  4908              LDR      r1,|L10.48|
00000e  4288              CMP      r0,r1
000010  d101              BNE      |L10.22|
;;;310    		NVIC_EnableIRQ(SPI0_IRQn);
000012  200e              MOVS     r0,#0xe
000014  e003              B        |L10.30|
                  |L10.22|
;;;311    	else if((uint32_t)SpiPort == SPI1_BASE)	
000016  4907              LDR      r1,|L10.52|
000018  4288              CMP      r0,r1
00001a  d103              BNE      |L10.36|
;;;312    		NVIC_EnableIRQ(SPI1_IRQn);
00001c  200f              MOVS     r0,#0xf
                  |L10.30|
00001e  f7fffffe          BL       NVIC_EnableIRQ
                  |L10.34|
;;;313    	else if((uint32_t)SpiPort == SPI2_BASE)		
;;;314    		NVIC_EnableIRQ(SPI2_IRQn);
;;;315    }	
000022  bd10              POP      {r4,pc}
                  |L10.36|
000024  4904              LDR      r1,|L10.56|
000026  4288              CMP      r0,r1                 ;313
000028  d1fb              BNE      |L10.34|
00002a  2010              MOVS     r0,#0x10              ;314
00002c  e7f7              B        |L10.30|
;;;316    
                          ENDP

00002e  0000              DCW      0x0000
                  |L10.48|
                          DCD      0x40030000
                  |L10.52|
                          DCD      0x40130000
                  |L10.56|
                          DCD      0x400d0000

                          AREA ||i.SPI_FIFORead16||, CODE, READONLY, ALIGN=1

                  SPI_FIFORead16 PROC
;;;627      */
;;;628    int32_t SPI_FIFORead16(SPI_TypeDef *SpiPort, uint16_t *pu16RxBuf, uint32_t u32ReadLength)
000000  b570              PUSH     {r4-r6,lr}
;;;629    {
;;;630    	uint32_t  u32Count, u32delayno;
;;;631    		 	
;;;632    	for (u32Count=0; u32Count<u32ReadLength; u32Count++)
000002  2400              MOVS     r4,#0
;;;633        {
;;;634        	u32delayno = 0;
;;;635    	   	while (SpiPort->STATUS & SPI_STATUS_RX_EMPTY)  /* Wait Rx is not empty and Time-out manner */
;;;636            {
;;;637           	    u32delayno++;
;;;638           	    if ( u32delayno >= 0x40000000 )     	    
000004  2501              MOVS     r5,#1
000006  07ad              LSLS     r5,r5,#30
000008  e00e              B        |L11.40|
                  |L11.10|
00000a  2300              MOVS     r3,#0                 ;634
00000c  e005              B        |L11.26|
                  |L11.14|
00000e  1c5b              ADDS     r3,r3,#1              ;637
000010  42ab              CMP      r3,r5
000012  d302              BCC      |L11.26|
;;;639           	       return SPI_ERR_TIMEOUT;   
000014  2000              MOVS     r0,#0
000016  43c0              MVNS     r0,r0
;;;640    				   
;;;641            }
;;;642            pu16RxBuf[u32Count] = SpiPort->RX0;
;;;643        }
;;;644        
;;;645        return E_SUCCESS;
;;;646    }
000018  bd70              POP      {r4-r6,pc}
                  |L11.26|
00001a  6846              LDR      r6,[r0,#4]            ;635
00001c  07f6              LSLS     r6,r6,#31             ;635
00001e  d1f6              BNE      |L11.14|
000020  6903              LDR      r3,[r0,#0x10]         ;642
000022  0066              LSLS     r6,r4,#1              ;642
000024  538b              STRH     r3,[r1,r6]            ;642
000026  1c64              ADDS     r4,r4,#1              ;632
                  |L11.40|
000028  4294              CMP      r4,r2                 ;632
00002a  d3ee              BCC      |L11.10|
00002c  2000              MOVS     r0,#0                 ;645
00002e  bd70              POP      {r4-r6,pc}
;;;647    
                          ENDP


                          AREA ||i.SPI_FIFORead32||, CODE, READONLY, ALIGN=1

                  SPI_FIFORead32 PROC
;;;655      */
;;;656    int32_t SPI_FIFORead32(SPI_TypeDef *SpiPort, uint32_t *pu32RxBuf, uint32_t u32ReadLength)
000000  b570              PUSH     {r4-r6,lr}
;;;657    {
;;;658    	uint32_t  u32Count, u32delayno;
;;;659    		 	
;;;660    	for (u32Count=0; u32Count<u32ReadLength; u32Count++)
000002  2400              MOVS     r4,#0
;;;661        {
;;;662        	u32delayno = 0;
;;;663    	   	while (SpiPort->STATUS & SPI_STATUS_RX_EMPTY)  /* Wait Rx is not empty and Time-out manner */
;;;664            {
;;;665           	    u32delayno++;
;;;666           	    if ( u32delayno >= 0x40000000 )     	    
000004  2501              MOVS     r5,#1
000006  07ad              LSLS     r5,r5,#30
000008  e00e              B        |L12.40|
                  |L12.10|
00000a  2300              MOVS     r3,#0                 ;662
00000c  e005              B        |L12.26|
                  |L12.14|
00000e  1c5b              ADDS     r3,r3,#1              ;665
000010  42ab              CMP      r3,r5
000012  d302              BCC      |L12.26|
;;;667           	       return SPI_ERR_TIMEOUT;   
000014  2000              MOVS     r0,#0
000016  43c0              MVNS     r0,r0
;;;668    				   
;;;669            }
;;;670            pu32RxBuf[u32Count] = SpiPort->RX0;
;;;671        }
;;;672        
;;;673        return E_SUCCESS;
;;;674    }
000018  bd70              POP      {r4-r6,pc}
                  |L12.26|
00001a  6846              LDR      r6,[r0,#4]            ;663
00001c  07f6              LSLS     r6,r6,#31             ;663
00001e  d1f6              BNE      |L12.14|
000020  6903              LDR      r3,[r0,#0x10]         ;670
000022  00a6              LSLS     r6,r4,#2              ;670
000024  518b              STR      r3,[r1,r6]            ;670
000026  1c64              ADDS     r4,r4,#1              ;660
                  |L12.40|
000028  4294              CMP      r4,r2                 ;660
00002a  d3ee              BCC      |L12.10|
00002c  2000              MOVS     r0,#0                 ;673
00002e  bd70              POP      {r4-r6,pc}
;;;675    
                          ENDP


                          AREA ||i.SPI_FIFORead8||, CODE, READONLY, ALIGN=1

                  SPI_FIFORead8 PROC
;;;599      */
;;;600    int32_t SPI_FIFORead8(SPI_TypeDef *SpiPort, uint8_t *pu8RxBuf, uint32_t u32ReadLength)
000000  b570              PUSH     {r4-r6,lr}
;;;601    {
;;;602    	uint32_t  u32Count, u32delayno;
;;;603    		 	
;;;604    	for (u32Count=0; u32Count<u32ReadLength; u32Count++)
000002  2400              MOVS     r4,#0
;;;605        {
;;;606        	u32delayno = 0;
;;;607    	   	while (SpiPort->STATUS & SPI_STATUS_RX_EMPTY)  /* Wait Rx is not empty and Time-out manner */
;;;608            {
;;;609           	    u32delayno++;
;;;610           	    if ( u32delayno >= 0x40000000 )     	    
000004  2501              MOVS     r5,#1
000006  07ad              LSLS     r5,r5,#30
000008  e00d              B        |L13.38|
                  |L13.10|
00000a  2300              MOVS     r3,#0                 ;606
00000c  e005              B        |L13.26|
                  |L13.14|
00000e  1c5b              ADDS     r3,r3,#1              ;609
000010  42ab              CMP      r3,r5
000012  d302              BCC      |L13.26|
;;;611           	       return SPI_ERR_TIMEOUT;   
000014  2000              MOVS     r0,#0
000016  43c0              MVNS     r0,r0
;;;612    				   
;;;613            }
;;;614            pu8RxBuf[u32Count] = SpiPort->RX0;
;;;615        }
;;;616        
;;;617        return E_SUCCESS;
;;;618    }
000018  bd70              POP      {r4-r6,pc}
                  |L13.26|
00001a  6846              LDR      r6,[r0,#4]            ;607
00001c  07f6              LSLS     r6,r6,#31             ;607
00001e  d1f6              BNE      |L13.14|
000020  6903              LDR      r3,[r0,#0x10]         ;614
000022  550b              STRB     r3,[r1,r4]            ;614
000024  1c64              ADDS     r4,r4,#1              ;604
                  |L13.38|
000026  4294              CMP      r4,r2                 ;604
000028  d3ef              BCC      |L13.10|
00002a  2000              MOVS     r0,#0                 ;617
00002c  bd70              POP      {r4-r6,pc}
;;;619    
                          ENDP


                          AREA ||i.SPI_FIFOReadWrite16||, CODE, READONLY, ALIGN=1

                  SPI_FIFOReadWrite16 PROC
;;;731      */  
;;;732    void SPI_FIFOReadWrite16(SPI_TypeDef *SpiPort, uint16_t *pu16TxBuf, uint32_t *pu16RxBuf, uint32_t u32Length)
000000  b5f0              PUSH     {r4-r7,lr}
;;;733    {
;;;734    	uint32_t  u32Count, u32RxCount = 0;
000002  2400              MOVS     r4,#0
;;;735    	 
;;;736    	for (u32Count=0; u32Count<u32Length; u32Count++)
000004  4625              MOV      r5,r4
000006  e01d              B        |L14.68|
                  |L14.8|
;;;737        {    	
;;;738    	   	while (SpiPort->STATUS & SPI_STATUS_TX_FULL)  /* if Tx is full, process Rx */
;;;739            {
;;;740           	    while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;741       	    		pu16RxBuf[u32RxCount++] = SpiPort->RX0;				   
000008  6906              LDR      r6,[r0,#0x10]
00000a  00a7              LSLS     r7,r4,#2
00000c  51d6              STR      r6,[r2,r7]
00000e  1c64              ADDS     r4,r4,#1
                  |L14.16|
000010  6846              LDR      r6,[r0,#4]            ;740
000012  07f6              LSLS     r6,r6,#31             ;740
000014  d0f8              BEQ      |L14.8|
                  |L14.22|
000016  6846              LDR      r6,[r0,#4]            ;738
000018  0736              LSLS     r6,r6,#28             ;738
00001a  d4f9              BMI      |L14.16|
;;;742            }
;;;743            
;;;744            if(pu16TxBuf == NULL)
00001c  2900              CMP      r1,#0
00001e  d006              BEQ      |L14.46|
;;;745            	SpiPort->TX0 = 0xFFFFFFFF;
;;;746            else
;;;747            	SpiPort->TX0 = pu16TxBuf[u32Count];
000020  006e              LSLS     r6,r5,#1
000022  5b8e              LDRH     r6,[r1,r6]
                  |L14.36|
000024  6206              STR      r6,[r0,#0x20]
;;;748    
;;;749            if(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))	/* check if rx has something */
000026  6846              LDR      r6,[r0,#4]
000028  07f6              LSLS     r6,r6,#31
00002a  d007              BEQ      |L14.60|
00002c  e009              B        |L14.66|
                  |L14.46|
00002e  2600              MOVS     r6,#0                 ;745
000030  43f6              MVNS     r6,r6                 ;745
000032  e7f7              B        |L14.36|
                  |L14.52|
;;;750        	{
;;;751        		while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;752        			pu16RxBuf[u32RxCount++] = SpiPort->RX0;
000034  6906              LDR      r6,[r0,#0x10]
000036  00a7              LSLS     r7,r4,#2
000038  51d6              STR      r6,[r2,r7]
00003a  1c64              ADDS     r4,r4,#1
                  |L14.60|
00003c  6846              LDR      r6,[r0,#4]            ;751
00003e  07f6              LSLS     r6,r6,#31             ;751
000040  d0f8              BEQ      |L14.52|
                  |L14.66|
000042  1c6d              ADDS     r5,r5,#1              ;736
                  |L14.68|
000044  429d              CMP      r5,r3                 ;736
000046  d3e6              BCC      |L14.22|
000048  e006              B        |L14.88|
                  |L14.74|
;;;753        	}
;;;754        }
;;;755        
;;;756        // SPI is still in progress, check Rx if something is in FIFO 
;;;757        while(SpiPort->CTL & SPI_CTL_GO_BUSY)
;;;758        {
;;;759        	while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;760        		pu16RxBuf[u32RxCount++] = SpiPort->RX0;
00004a  6901              LDR      r1,[r0,#0x10]
00004c  00a3              LSLS     r3,r4,#2
00004e  50d1              STR      r1,[r2,r3]
000050  1c64              ADDS     r4,r4,#1
                  |L14.82|
000052  6841              LDR      r1,[r0,#4]            ;759
000054  07c9              LSLS     r1,r1,#31             ;759
000056  d0f8              BEQ      |L14.74|
                  |L14.88|
000058  6801              LDR      r1,[r0,#0]            ;757
00005a  07c9              LSLS     r1,r1,#31             ;757
00005c  d1f9              BNE      |L14.82|
00005e  e003              B        |L14.104|
                  |L14.96|
;;;761        }
;;;762        
;;;763        // SPI is finisned, but still need to check FIFO status
;;;764        while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;765        	pu16RxBuf[u32RxCount++] = SpiPort->RX0;
000060  6901              LDR      r1,[r0,#0x10]
000062  00a3              LSLS     r3,r4,#2
000064  50d1              STR      r1,[r2,r3]
000066  1c64              ADDS     r4,r4,#1
                  |L14.104|
000068  6841              LDR      r1,[r0,#4]            ;764
00006a  07c9              LSLS     r1,r1,#31             ;764
00006c  d0f8              BEQ      |L14.96|
;;;766    }
00006e  bdf0              POP      {r4-r7,pc}
;;;767    
                          ENDP


                          AREA ||i.SPI_FIFOReadWrite32||, CODE, READONLY, ALIGN=1

                  SPI_FIFOReadWrite32 PROC
;;;777      */  
;;;778    void SPI_FIFOReadWrite32(SPI_TypeDef *SpiPort, uint32_t *pu32TxBuf, uint32_t *pu32RxBuf, uint32_t u32Length)
000000  b5f0              PUSH     {r4-r7,lr}
;;;779    {
;;;780    	uint32_t  u32Count, u32RxCount = 0;
000002  2400              MOVS     r4,#0
;;;781    	 
;;;782    	for (u32Count=0; u32Count<u32Length; u32Count++)
000004  4625              MOV      r5,r4
000006  e01d              B        |L15.68|
                  |L15.8|
;;;783        {    	
;;;784    	   	while (SpiPort->STATUS & SPI_STATUS_TX_FULL)  /* if Tx is full, process Rx */
;;;785            {
;;;786           	    while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;787       	    		pu32RxBuf[u32RxCount++] = SpiPort->RX0;				   
000008  6906              LDR      r6,[r0,#0x10]
00000a  00a7              LSLS     r7,r4,#2
00000c  51d6              STR      r6,[r2,r7]
00000e  1c64              ADDS     r4,r4,#1
                  |L15.16|
000010  6846              LDR      r6,[r0,#4]            ;786
000012  07f6              LSLS     r6,r6,#31             ;786
000014  d0f8              BEQ      |L15.8|
                  |L15.22|
000016  6846              LDR      r6,[r0,#4]            ;784
000018  0736              LSLS     r6,r6,#28             ;784
00001a  d4f9              BMI      |L15.16|
;;;788            }
;;;789            
;;;790            if(pu32TxBuf == NULL)
00001c  2900              CMP      r1,#0
00001e  d006              BEQ      |L15.46|
;;;791            	SpiPort->TX0 = 0xFFFFFFFF;
;;;792            else
;;;793            	SpiPort->TX0 = pu32TxBuf[u32Count];
000020  00ae              LSLS     r6,r5,#2
000022  598e              LDR      r6,[r1,r6]
                  |L15.36|
000024  6206              STR      r6,[r0,#0x20]
;;;794    
;;;795            if(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))	/* check if rx has something */
000026  6846              LDR      r6,[r0,#4]
000028  07f6              LSLS     r6,r6,#31
00002a  d007              BEQ      |L15.60|
00002c  e009              B        |L15.66|
                  |L15.46|
00002e  2600              MOVS     r6,#0                 ;791
000030  43f6              MVNS     r6,r6                 ;791
000032  e7f7              B        |L15.36|
                  |L15.52|
;;;796        	{
;;;797        		while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;798        			pu32RxBuf[u32RxCount++] = SpiPort->RX0;
000034  6906              LDR      r6,[r0,#0x10]
000036  00a7              LSLS     r7,r4,#2
000038  51d6              STR      r6,[r2,r7]
00003a  1c64              ADDS     r4,r4,#1
                  |L15.60|
00003c  6846              LDR      r6,[r0,#4]            ;797
00003e  07f6              LSLS     r6,r6,#31             ;797
000040  d0f8              BEQ      |L15.52|
                  |L15.66|
000042  1c6d              ADDS     r5,r5,#1              ;782
                  |L15.68|
000044  429d              CMP      r5,r3                 ;782
000046  d3e6              BCC      |L15.22|
000048  e006              B        |L15.88|
                  |L15.74|
;;;799        	}
;;;800        }
;;;801        
;;;802        // SPI is still in progress, check Rx if something is in FIFO 
;;;803        while(SpiPort->CTL & SPI_CTL_GO_BUSY)
;;;804        {
;;;805        	while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;806        		pu32RxBuf[u32RxCount++] = SpiPort->RX0;
00004a  6901              LDR      r1,[r0,#0x10]
00004c  00a3              LSLS     r3,r4,#2
00004e  50d1              STR      r1,[r2,r3]
000050  1c64              ADDS     r4,r4,#1
                  |L15.82|
000052  6841              LDR      r1,[r0,#4]            ;805
000054  07c9              LSLS     r1,r1,#31             ;805
000056  d0f8              BEQ      |L15.74|
                  |L15.88|
000058  6801              LDR      r1,[r0,#0]            ;803
00005a  07c9              LSLS     r1,r1,#31             ;803
00005c  d1f9              BNE      |L15.82|
00005e  e003              B        |L15.104|
                  |L15.96|
;;;807        }
;;;808        
;;;809        // SPI is finisned, but still need to check FIFO status
;;;810        while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;811        	pu32RxBuf[u32RxCount++] = SpiPort->RX0;
000060  6901              LDR      r1,[r0,#0x10]
000062  00a3              LSLS     r3,r4,#2
000064  50d1              STR      r1,[r2,r3]
000066  1c64              ADDS     r4,r4,#1
                  |L15.104|
000068  6841              LDR      r1,[r0,#4]            ;810
00006a  07c9              LSLS     r1,r1,#31             ;810
00006c  d0f8              BEQ      |L15.96|
;;;812    }
00006e  bdf0              POP      {r4-r7,pc}
;;;813    
                          ENDP


                          AREA ||i.SPI_FIFOReadWrite8||, CODE, READONLY, ALIGN=1

                  SPI_FIFOReadWrite8 PROC
;;;685      */  
;;;686    void SPI_FIFOReadWrite8(SPI_TypeDef *SpiPort, uint8_t *pu8TxBuf, uint8_t *pu8RxBuf, uint32_t u32Length)
000000  b570              PUSH     {r4-r6,lr}
;;;687    {
;;;688    	uint32_t  u32Count, u32RxCount = 0;
000002  2400              MOVS     r4,#0
;;;689    	 
;;;690    	for (u32Count=0; u32Count<u32Length; u32Count++)
000004  4625              MOV      r5,r4
000006  e01a              B        |L16.62|
                  |L16.8|
;;;691        {    	
;;;692    	   	while (SpiPort->STATUS & SPI_STATUS_TX_FULL)  /* if Tx is full, process Rx */
;;;693            {
;;;694           	    while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;695       	    		pu8RxBuf[u32RxCount++] = SpiPort->RX0;				   
000008  6906              LDR      r6,[r0,#0x10]
00000a  5516              STRB     r6,[r2,r4]
00000c  1c64              ADDS     r4,r4,#1
                  |L16.14|
00000e  6846              LDR      r6,[r0,#4]            ;694
000010  07f6              LSLS     r6,r6,#31             ;694
000012  d0f9              BEQ      |L16.8|
                  |L16.20|
000014  6846              LDR      r6,[r0,#4]            ;692
000016  0736              LSLS     r6,r6,#28             ;692
000018  d4f9              BMI      |L16.14|
;;;696            }
;;;697            
;;;698            if(pu8TxBuf == NULL)
00001a  2900              CMP      r1,#0
00001c  d005              BEQ      |L16.42|
;;;699            	SpiPort->TX0 = 0xFFFFFFFF;
;;;700            else
;;;701            	SpiPort->TX0 = pu8TxBuf[u32Count];
00001e  5d4e              LDRB     r6,[r1,r5]
                  |L16.32|
000020  6206              STR      r6,[r0,#0x20]
;;;702    
;;;703            if(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))	/* check if rx has something */
000022  6846              LDR      r6,[r0,#4]
000024  07f6              LSLS     r6,r6,#31
000026  d006              BEQ      |L16.54|
000028  e008              B        |L16.60|
                  |L16.42|
00002a  2600              MOVS     r6,#0                 ;699
00002c  43f6              MVNS     r6,r6                 ;699
00002e  e7f7              B        |L16.32|
                  |L16.48|
;;;704        	{
;;;705        		while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;706        			pu8RxBuf[u32RxCount++] = SpiPort->RX0;
000030  6906              LDR      r6,[r0,#0x10]
000032  5516              STRB     r6,[r2,r4]
000034  1c64              ADDS     r4,r4,#1
                  |L16.54|
000036  6846              LDR      r6,[r0,#4]            ;705
000038  07f6              LSLS     r6,r6,#31             ;705
00003a  d0f9              BEQ      |L16.48|
                  |L16.60|
00003c  1c6d              ADDS     r5,r5,#1              ;690
                  |L16.62|
00003e  429d              CMP      r5,r3                 ;690
000040  d3e8              BCC      |L16.20|
000042  e005              B        |L16.80|
                  |L16.68|
;;;707        	}
;;;708        }
;;;709        
;;;710        // SPI is still in progress, check Rx if something is in FIFO 
;;;711        while(SpiPort->CTL & SPI_CTL_GO_BUSY)
;;;712        {
;;;713        	while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;714        		pu8RxBuf[u32RxCount++] = SpiPort->RX0;
000044  6901              LDR      r1,[r0,#0x10]
000046  5511              STRB     r1,[r2,r4]
000048  1c64              ADDS     r4,r4,#1
                  |L16.74|
00004a  6841              LDR      r1,[r0,#4]            ;713
00004c  07c9              LSLS     r1,r1,#31             ;713
00004e  d0f9              BEQ      |L16.68|
                  |L16.80|
000050  6801              LDR      r1,[r0,#0]            ;711
000052  07c9              LSLS     r1,r1,#31             ;711
000054  d1f9              BNE      |L16.74|
000056  e002              B        |L16.94|
                  |L16.88|
;;;715        }
;;;716        
;;;717        // SPI is finisned, but still need to check FIFO status
;;;718        while(!(SpiPort->STATUS & SPI_STATUS_RX_EMPTY))
;;;719        	pu8RxBuf[u32RxCount++] = SpiPort->RX0;
000058  6901              LDR      r1,[r0,#0x10]
00005a  5511              STRB     r1,[r2,r4]
00005c  1c64              ADDS     r4,r4,#1
                  |L16.94|
00005e  6841              LDR      r1,[r0,#4]            ;718
000060  07c9              LSLS     r1,r1,#31             ;718
000062  d0f9              BEQ      |L16.88|
;;;720    }
000064  bd70              POP      {r4-r6,pc}
;;;721    
                          ENDP


                          AREA ||i.SPI_FIFOWrite16||, CODE, READONLY, ALIGN=1

                  SPI_FIFOWrite16 PROC
;;;543      */
;;;544    int32_t SPI_FIFOWrite16(SPI_TypeDef *SpiPort, uint16_t *pu16TxBuf, uint32_t u32WriteLength)
000000  b570              PUSH     {r4-r6,lr}
;;;545    {
;;;546    	uint32_t  u32Count, u32delayno;
;;;547    	 
;;;548    	for (u32Count=0; u32Count<u32WriteLength; u32Count++)
000002  2400              MOVS     r4,#0
;;;549        {
;;;550        	u32delayno = 0;
;;;551    	   	while (SpiPort->STATUS & SPI_STATUS_TX_FULL)  /* Wait Tx is empty and Time-out manner */
;;;552            {
;;;553           	    u32delayno++;
;;;554           	    if ( u32delayno >= 0x40000000 )     	    
000004  2501              MOVS     r5,#1
000006  07ad              LSLS     r5,r5,#30
000008  e00e              B        |L17.40|
                  |L17.10|
00000a  2300              MOVS     r3,#0                 ;550
00000c  e005              B        |L17.26|
                  |L17.14|
00000e  1c5b              ADDS     r3,r3,#1              ;553
000010  42ab              CMP      r3,r5
000012  d302              BCC      |L17.26|
;;;555           	       return SPI_ERR_TIMEOUT;   
000014  2000              MOVS     r0,#0
000016  43c0              MVNS     r0,r0
;;;556    				   
;;;557            }
;;;558            SpiPort->TX0 = pu16TxBuf[u32Count];
;;;559        }
;;;560        
;;;561        return E_SUCCESS;
;;;562    }
000018  bd70              POP      {r4-r6,pc}
                  |L17.26|
00001a  6846              LDR      r6,[r0,#4]            ;551
00001c  0736              LSLS     r6,r6,#28             ;551
00001e  d4f6              BMI      |L17.14|
000020  0063              LSLS     r3,r4,#1              ;558
000022  5acb              LDRH     r3,[r1,r3]            ;558
000024  6203              STR      r3,[r0,#0x20]         ;558
000026  1c64              ADDS     r4,r4,#1              ;548
                  |L17.40|
000028  4294              CMP      r4,r2                 ;548
00002a  d3ee              BCC      |L17.10|
00002c  2000              MOVS     r0,#0                 ;561
00002e  bd70              POP      {r4-r6,pc}
;;;563    
                          ENDP


                          AREA ||i.SPI_FIFOWrite32||, CODE, READONLY, ALIGN=1

                  SPI_FIFOWrite32 PROC
;;;571      */
;;;572    int32_t SPI_FIFOWrite32(SPI_TypeDef *SpiPort, uint32_t *pu32TxBuf, uint32_t u32WriteLength)
000000  b570              PUSH     {r4-r6,lr}
;;;573    {
;;;574    	uint32_t  u32Count, u32delayno;
;;;575    	 
;;;576    	for (u32Count=0; u32Count<u32WriteLength; u32Count++)
000002  2400              MOVS     r4,#0
;;;577        {
;;;578        	u32delayno = 0;
;;;579    	   	while (SpiPort->STATUS & SPI_STATUS_TX_FULL)  /* Wait Tx is empty and Time-out manner */
;;;580            {
;;;581           	    u32delayno++;
;;;582           	    if ( u32delayno >= 0x40000000 )     	    
000004  2501              MOVS     r5,#1
000006  07ad              LSLS     r5,r5,#30
000008  e00e              B        |L18.40|
                  |L18.10|
00000a  2300              MOVS     r3,#0                 ;578
00000c  e005              B        |L18.26|
                  |L18.14|
00000e  1c5b              ADDS     r3,r3,#1              ;581
000010  42ab              CMP      r3,r5
000012  d302              BCC      |L18.26|
;;;583           	       return SPI_ERR_TIMEOUT;   
000014  2000              MOVS     r0,#0
000016  43c0              MVNS     r0,r0
;;;584    				   
;;;585            }
;;;586            SpiPort->TX0 = pu32TxBuf[u32Count];
;;;587        }
;;;588        
;;;589        return E_SUCCESS;
;;;590    }
000018  bd70              POP      {r4-r6,pc}
                  |L18.26|
00001a  6846              LDR      r6,[r0,#4]            ;579
00001c  0736              LSLS     r6,r6,#28             ;579
00001e  d4f6              BMI      |L18.14|
000020  00a3              LSLS     r3,r4,#2              ;586
000022  58cb              LDR      r3,[r1,r3]            ;586
000024  6203              STR      r3,[r0,#0x20]         ;586
000026  1c64              ADDS     r4,r4,#1              ;576
                  |L18.40|
000028  4294              CMP      r4,r2                 ;576
00002a  d3ee              BCC      |L18.10|
00002c  2000              MOVS     r0,#0                 ;589
00002e  bd70              POP      {r4-r6,pc}
;;;591    
                          ENDP


                          AREA ||i.SPI_FIFOWrite8||, CODE, READONLY, ALIGN=1

                  SPI_FIFOWrite8 PROC
;;;515      */
;;;516    int32_t SPI_FIFOWrite8(SPI_TypeDef *SpiPort, uint8_t *pu8TxBuf, uint32_t u32WriteLength)
000000  b570              PUSH     {r4-r6,lr}
;;;517    {
;;;518    	uint32_t  u32Count, u32delayno;
;;;519    	 
;;;520    	for (u32Count=0; u32Count<u32WriteLength; u32Count++)
000002  2400              MOVS     r4,#0
;;;521        {
;;;522        	u32delayno = 0;
;;;523    	   	while (SpiPort->STATUS & SPI_STATUS_TX_FULL)  /* Wait Tx is empty and Time-out manner */
;;;524            {
;;;525           	    u32delayno++;
;;;526           	    if ( u32delayno >= 0x40000000 )     	    
000004  2501              MOVS     r5,#1
000006  07ad              LSLS     r5,r5,#30
000008  e00d              B        |L19.38|
                  |L19.10|
00000a  2300              MOVS     r3,#0                 ;522
00000c  e005              B        |L19.26|
                  |L19.14|
00000e  1c5b              ADDS     r3,r3,#1              ;525
000010  42ab              CMP      r3,r5
000012  d302              BCC      |L19.26|
;;;527           	       return SPI_ERR_TIMEOUT;   
000014  2000              MOVS     r0,#0
000016  43c0              MVNS     r0,r0
;;;528    				   
;;;529            }
;;;530            SpiPort->TX0 = pu8TxBuf[u32Count];
;;;531        }
;;;532        
;;;533        return E_SUCCESS;
;;;534    }
000018  bd70              POP      {r4-r6,pc}
                  |L19.26|
00001a  6846              LDR      r6,[r0,#4]            ;523
00001c  0736              LSLS     r6,r6,#28             ;523
00001e  d4f6              BMI      |L19.14|
000020  5d0b              LDRB     r3,[r1,r4]            ;530
000022  6203              STR      r3,[r0,#0x20]         ;530
000024  1c64              ADDS     r4,r4,#1              ;520
                  |L19.38|
000026  4294              CMP      r4,r2                 ;520
000028  d3ef              BCC      |L19.10|
00002a  2000              MOVS     r0,#0                 ;533
00002c  bd70              POP      {r4-r6,pc}
;;;535    
                          ENDP


                          AREA ||i.SPI_GetClock1Freq||, CODE, READONLY, ALIGN=1

                  SPI_GetClock1Freq PROC
;;;270      */
;;;271    uint32_t SPI_GetClock1Freq(SPI_TypeDef *SpiPort)
000000  b510              PUSH     {r4,lr}
;;;272    {
000002  4604              MOV      r4,r0
;;;273    	uint32_t u32Div;
;;;274    	uint32_t u32ApbClock;
;;;275    
;;;276    	u32ApbClock = SPI_GetSourceClockFreq(SpiPort);
000004  f7fffffe          BL       SPI_GetSourceClockFreq
;;;277    	u32Div = SpiPort->CLKDIV & SPI_CLKDIV_DIVIDER1_MASK;
000008  68a1              LDR      r1,[r4,#8]
00000a  0609              LSLS     r1,r1,#24
00000c  0e09              LSRS     r1,r1,#24
;;;278    	
;;;279    	if(u32Div == 0)	return u32ApbClock;
00000e  d002              BEQ      |L20.22|
;;;280    	else return ((u32ApbClock >> 1) / u32Div);   /* SPI_CLK = APB_CLK / (Divider * 2) */
000010  0840              LSRS     r0,r0,#1
000012  f7fffffe          BL       __aeabi_uidivmod
                  |L20.22|
;;;281    }
000016  bd10              POP      {r4,pc}
;;;282    
                          ENDP


                          AREA ||i.SPI_GetClock2Freq||, CODE, READONLY, ALIGN=1

                  SPI_GetClock2Freq PROC
;;;287      */
;;;288    uint32_t SPI_GetClock2Freq(SPI_TypeDef *SpiPort)
000000  b510              PUSH     {r4,lr}
;;;289    {
000002  4604              MOV      r4,r0
;;;290    	uint32_t u32Div;
;;;291    	uint32_t u32ApbClock;
;;;292    
;;;293    	u32ApbClock = SPI_GetSourceClockFreq(SpiPort);
000004  f7fffffe          BL       SPI_GetSourceClockFreq
;;;294    	u32Div = (SpiPort->CLKDIV & SPI_CLKDIV_DIVIDER2_MASK) >> 16;
000008  68a1              LDR      r1,[r4,#8]
;;;295    	return ((u32ApbClock >> 1) / (u32Div + 1));   /* SPI_CLK = APB_CLK / ((Divider + 1) * 2) */
00000a  0840              LSRS     r0,r0,#1
00000c  0209              LSLS     r1,r1,#8              ;294
00000e  0e09              LSRS     r1,r1,#24             ;294
000010  1c49              ADDS     r1,r1,#1
000012  f7fffffe          BL       __aeabi_uidivmod
;;;296    }
000016  bd10              POP      {r4,pc}
;;;297    
                          ENDP


                          AREA ||i.SPI_GetSourceClockFreq||, CODE, READONLY, ALIGN=2

                  SPI_GetSourceClockFreq PROC
;;;818      */
;;;819    uint32_t SPI_GetSourceClockFreq(SPI_TypeDef *SpiPort)
000000  b570              PUSH     {r4-r6,lr}
;;;820    {	
;;;821    	//	Clock Source is form:
;;;822    	//  (PLL, HXT, HIRC, LXT, LIRC) --> [HCLK_Div] ---> HCLK --->
;;;823    	//    |                                                      [SPI_Div] ====> SPI clock
;;;824    	//    +--------------------------------------------PLL------>
;;;825    	//
;;;826    	uint32_t u32Freq = 12000000, u32ClkSrcSel;
;;;827    	
;;;828    	if((uint32_t)SpiPort == SPI0_BASE)
;;;829    		u32ClkSrcSel = CLK->CLKSEL2 & CLK_CLKSEL2_SPI0_MASK;
000002  4913              LDR      r1,|L22.80|
000004  4e11              LDR      r6,|L22.76|
000006  4a10              LDR      r2,|L22.72|
000008  02cb              LSLS     r3,r1,#11
;;;830    	else if((uint32_t)SpiPort == SPI1_BASE)
;;;831    		u32ClkSrcSel = CLK->CLKSEL2 & CLK_CLKSEL2_SPI1_MASK;
00000a  030c              LSLS     r4,r1,#12
;;;832    	else 
;;;833    		u32ClkSrcSel = CLK->CLKSEL2 & CLK_CLKSEL2_SPI2_MASK;
00000c  034d              LSLS     r5,r1,#13
00000e  42b0              CMP      r0,r6                 ;828
000010  d102              BNE      |L22.24|
000012  6988              LDR      r0,[r1,#0x18]         ;829
000014  4018              ANDS     r0,r0,r3              ;829
000016  e006              B        |L22.38|
                  |L22.24|
000018  4e0e              LDR      r6,|L22.84|
00001a  42b0              CMP      r0,r6                 ;830
00001c  6988              LDR      r0,[r1,#0x18]
00001e  d101              BNE      |L22.36|
000020  4020              ANDS     r0,r0,r4              ;831
000022  e000              B        |L22.38|
                  |L22.36|
000024  4028              ANDS     r0,r0,r5
                  |L22.38|
;;;834    		
;;;835    		
;;;836    	if((u32ClkSrcSel == CLK_CLKSEL2_SPI0_PLL)  ||
000026  2800              CMP      r0,#0
000028  d008              BEQ      |L22.60|
;;;837    		(u32ClkSrcSel == CLK_CLKSEL2_SPI1_PLL) ||
;;;838    		(u32ClkSrcSel == CLK_CLKSEL2_SPI2_PLL))
;;;839    	{
;;;840    		return SYS_GetPLLClockFreq();
;;;841    	}
;;;842    	
;;;843    	if((u32ClkSrcSel == CLK_CLKSEL2_SPI0_HCLK)  ||
00002a  4298              CMP      r0,r3
00002c  d003              BEQ      |L22.54|
;;;844    		(u32ClkSrcSel == CLK_CLKSEL2_SPI1_HCLK) ||
00002e  42a0              CMP      r0,r4
000030  d001              BEQ      |L22.54|
;;;845    		(u32ClkSrcSel == CLK_CLKSEL2_SPI2_HCLK))
000032  42a8              CMP      r0,r5
000034  d105              BNE      |L22.66|
                  |L22.54|
;;;846    	{
;;;847    		return SYS_GetHCLKFreq();
000036  f7fffffe          BL       SYS_GetHCLKFreq
;;;848    	}
;;;849    	
;;;850    	return u32Freq;
;;;851    }
00003a  bd70              POP      {r4-r6,pc}
                  |L22.60|
00003c  f7fffffe          BL       SYS_GetPLLClockFreq
000040  bd70              POP      {r4-r6,pc}
                  |L22.66|
000042  4610              MOV      r0,r2                 ;850
000044  bd70              POP      {r4-r6,pc}
;;;852    
                          ENDP

000046  0000              DCW      0x0000
                  |L22.72|
                          DCD      0x00b71b00
                  |L22.76|
                          DCD      0x40030000
                  |L22.80|
                          DCD      0x50000200
                  |L22.84|
                          DCD      0x40130000

                          AREA ||i.SPI_Init||, CODE, READONLY, ALIGN=2

                  SPI_Init PROC
;;;30       
;;;31     void SPI_Init(SPI_TypeDef *SpiPort)
000000  4a0b              LDR      r2,|L23.48|
;;;32     {	
;;;33     	if((uint32_t)SpiPort == SPI0_BASE)
;;;34     		CLK->APBCLK |= CLK_APBCLK_SPI0_EN;		
000002  490c              LDR      r1,|L23.52|
000004  4290              CMP      r0,r2                 ;33
000006  d102              BNE      |L23.14|
000008  6888              LDR      r0,[r1,#8]
00000a  1492              ASRS     r2,r2,#18
00000c  e005              B        |L23.26|
                  |L23.14|
;;;35     	else if((uint32_t)SpiPort == SPI1_BASE)
00000e  4a0a              LDR      r2,|L23.56|
000010  4290              CMP      r0,r2
000012  d105              BNE      |L23.32|
;;;36     		CLK->APBCLK |= CLK_APBCLK_SPI1_EN;	
000014  6888              LDR      r0,[r1,#8]
000016  2201              MOVS     r2,#1
000018  0352              LSLS     r2,r2,#13
                  |L23.26|
00001a  4310              ORRS     r0,r0,r2              ;34
00001c  6088              STR      r0,[r1,#8]            ;34
                  |L23.30|
;;;37     	else if((uint32_t)SpiPort == SPI2_BASE)		
;;;38     		CLK->APBCLK |= CLK_APBCLK_SPI2_EN;	
;;;39     }
00001e  4770              BX       lr
                  |L23.32|
000020  4a06              LDR      r2,|L23.60|
000022  4290              CMP      r0,r2                 ;37
000024  d1fb              BNE      |L23.30|
000026  6888              LDR      r0,[r1,#8]            ;38
000028  2201              MOVS     r2,#1                 ;38
00002a  0392              LSLS     r2,r2,#14             ;38
00002c  e7f5              B        |L23.26|
;;;40     
                          ENDP

00002e  0000              DCW      0x0000
                  |L23.48|
                          DCD      0x40030000
                  |L23.52|
                          DCD      0x50000200
                  |L23.56|
                          DCD      0x40130000
                  |L23.60|
                          DCD      0x400d0000

                          AREA ||i.SPI_Open||, CODE, READONLY, ALIGN=2

                  SPI_Open PROC
;;;111    */
;;;112    int32_t SPI_Open(SPI_TypeDef *SpiPort, SPI_DATA_T *sParam)
000000  4b22              LDR      r3,|L24.140|
;;;113    {
;;;114    	int32_t i32TimeOut;
;;;115    	            
;;;116        /* Bit length 8 ~ 32 */
;;;117        assert_param(SPI_CHECK_BIT_LENGTH_0);
;;;118        	
;;;119    	if((uint32_t)SpiPort == SPI0_BASE)
;;;120    	{		
;;;121    		GCR->IPRST_CTL2 |= GCR_IPRSTCTL2_SPI0;
000002  2205              MOVS     r2,#5
000004  b510              PUSH     {r4,lr}               ;113
000006  0712              LSLS     r2,r2,#28
000008  4298              CMP      r0,r3                 ;119
00000a  d102              BNE      |L24.18|
00000c  68d4              LDR      r4,[r2,#0xc]
00000e  1483              ASRS     r3,r0,#18
;;;122    		GCR->IPRST_CTL2 &= ~GCR_IPRSTCTL2_SPI0;			
000010  e00c              B        |L24.44|
                  |L24.18|
;;;123    	}	
;;;124    	else if((uint32_t)SpiPort == SPI1_BASE)
000012  4b1f              LDR      r3,|L24.144|
000014  4298              CMP      r0,r3
000016  d103              BNE      |L24.32|
;;;125    	{	
;;;126    		GCR->IPRST_CTL2 |= GCR_IPRSTCTL2_SPI1;
000018  68d4              LDR      r4,[r2,#0xc]
00001a  2301              MOVS     r3,#1
00001c  035b              LSLS     r3,r3,#13
;;;127    		GCR->IPRST_CTL2 &= ~GCR_IPRSTCTL2_SPI1;		
00001e  e005              B        |L24.44|
                  |L24.32|
;;;128    	}	
;;;129    	else if((uint32_t)SpiPort == SPI2_BASE)
000020  4b1c              LDR      r3,|L24.148|
000022  4298              CMP      r0,r3
000024  d10e              BNE      |L24.68|
;;;130    	{	
;;;131    		GCR->IPRST_CTL2 |= GCR_IPRSTCTL2_SPI2;
000026  68d4              LDR      r4,[r2,#0xc]
000028  2301              MOVS     r3,#1
00002a  039b              LSLS     r3,r3,#14
                  |L24.44|
00002c  431c              ORRS     r4,r4,r3
00002e  60d4              STR      r4,[r2,#0xc]
;;;132    		GCR->IPRST_CTL2 &= ~GCR_IPRSTCTL2_SPI2;		
000030  68d4              LDR      r4,[r2,#0xc]
000032  439c              BICS     r4,r4,r3
000034  60d4              STR      r4,[r2,#0xc]
;;;133    	}
;;;134    	else	
;;;135    		return 0;
;;;136    			
;;;137    	/* Check busy*/
;;;138    	i32TimeOut = 0x10000;
000036  2201              MOVS     r2,#1
000038  0412              LSLS     r2,r2,#16
;;;139    	while(SpiPort->CTL & SPI_CTL_GO_BUSY)
00003a  e005              B        |L24.72|
                  |L24.60|
;;;140    	{
;;;141    		if(i32TimeOut-- <= 0)
00003c  4613              MOV      r3,r2
00003e  1e52              SUBS     r2,r2,#1
000040  2b00              CMP      r3,#0
000042  dc01              BGT      |L24.72|
                  |L24.68|
;;;142    			return SPI_ERR_BUSY;
000044  2000              MOVS     r0,#0
;;;143    	}
;;;144    	
;;;145    	/* "i32BitLength = 0" means 32 bits */
;;;146    	if(sParam->i32BitLength == 32)
;;;147    		sParam->i32BitLength = 0;
;;;148    		
;;;149    	SpiPort->CTL = (SpiPort->CTL & ~SPI_CTL_TX_BIT_LEN_MASK) | (sParam->i32BitLength << 3);
;;;150    	
;;;151    	SpiPort->CTL = (SpiPort->CTL & ~0x40000) | sParam->u32Mode;
;;;152    
;;;153    	/* Default to automatic slave select and it is low active */
;;;154    	SpiPort->SSR |= SPI_SSR_AUTOSS;
;;;155    	
;;;156    	/* Transition types */	
;;;157    	SpiPort->CTL = (SpiPort->CTL & ~0x806) | sParam->u32Type;
;;;158    	
;;;159        return E_SUCCESS;
;;;160    }
000046  bd10              POP      {r4,pc}
                  |L24.72|
000048  6803              LDR      r3,[r0,#0]            ;139
00004a  07db              LSLS     r3,r3,#31             ;139
00004c  d1f6              BNE      |L24.60|
00004e  688a              LDR      r2,[r1,#8]            ;146
000050  2a20              CMP      r2,#0x20              ;146
000052  d101              BNE      |L24.88|
000054  2200              MOVS     r2,#0                 ;147
000056  608a              STR      r2,[r1,#8]            ;147
                  |L24.88|
000058  6802              LDR      r2,[r0,#0]            ;149
00005a  23f8              MOVS     r3,#0xf8              ;149
00005c  439a              BICS     r2,r2,r3              ;149
00005e  688b              LDR      r3,[r1,#8]            ;149
000060  00db              LSLS     r3,r3,#3              ;149
000062  431a              ORRS     r2,r2,r3              ;149
000064  6002              STR      r2,[r0,#0]            ;149
000066  6802              LDR      r2,[r0,#0]            ;151
000068  2301              MOVS     r3,#1                 ;151
00006a  049b              LSLS     r3,r3,#18             ;151
00006c  439a              BICS     r2,r2,r3              ;151
00006e  680b              LDR      r3,[r1,#0]            ;151
000070  431a              ORRS     r2,r2,r3              ;151
000072  6002              STR      r2,[r0,#0]            ;151
000074  68c2              LDR      r2,[r0,#0xc]          ;154
000076  2308              MOVS     r3,#8                 ;154
000078  431a              ORRS     r2,r2,r3              ;154
00007a  60c2              STR      r2,[r0,#0xc]          ;154
00007c  6802              LDR      r2,[r0,#0]            ;157
00007e  4b06              LDR      r3,|L24.152|
000080  6849              LDR      r1,[r1,#4]            ;157
000082  401a              ANDS     r2,r2,r3              ;157
000084  430a              ORRS     r2,r2,r1              ;157
000086  6002              STR      r2,[r0,#0]            ;157
000088  e7dc              B        |L24.68|
;;;161    
                          ENDP

00008a  0000              DCW      0x0000
                  |L24.140|
                          DCD      0x40030000
                  |L24.144|
                          DCD      0x40130000
                  |L24.148|
                          DCD      0x400d0000
                  |L24.152|
                          DCD      0xfffff7f9

                          AREA ||i.SPI_SetBitLength||, CODE, READONLY, ALIGN=1

                  SPI_SetBitLength PROC
;;;182      */
;;;183    void SPI_SetBitLength(SPI_TypeDef *SpiPort, int32_t i32BitLength)
000000  2920              CMP      r1,#0x20
;;;184    {
;;;185    	assert_param(SPI_CHECK_BIT_LENGTH_1);
;;;186       
;;;187        if(i32BitLength == 32)
000002  d100              BNE      |L25.6|
;;;188            i32BitLength = 0;
000004  2100              MOVS     r1,#0
                  |L25.6|
;;;189    
;;;190    	SpiPort->CTL = (SpiPort->CTL & ~SPI_CTL_TX_BIT_LEN_MASK) | (i32BitLength << 3);
000006  6802              LDR      r2,[r0,#0]
000008  23f8              MOVS     r3,#0xf8
00000a  439a              BICS     r2,r2,r3
00000c  00c9              LSLS     r1,r1,#3
00000e  430a              ORRS     r2,r2,r1
000010  6002              STR      r2,[r0,#0]
;;;191    }
000012  4770              BX       lr
;;;192    
                          ENDP


                          AREA ||i.SPI_SetClockFreq||, CODE, READONLY, ALIGN=1

                  SPI_SetClockFreq PROC
;;;218      */
;;;219    uint32_t SPI_SetClockFreq(SPI_TypeDef *SpiPort, uint32_t u32Clock1, uint32_t u32Clock2)
000000  b5f7              PUSH     {r0-r2,r4-r7,lr}
;;;220    {
000002  b082              SUB      sp,sp,#8
000004  4605              MOV      r5,r0
000006  4617              MOV      r7,r2
;;;221        uint32_t u32Div;
;;;222        uint32_t u32Pclk, u32CalculatedSpeed=0;
000008  2600              MOVS     r6,#0
;;;223        
;;;224        u32Pclk = SPI_GetSourceClockFreq(SpiPort);
00000a  f7fffffe          BL       SPI_GetSourceClockFreq
;;;225        
;;;226    	if(u32Clock2!=0)
00000e  9000              STR      r0,[sp,#0]
000010  2f00              CMP      r7,#0
000012  d024              BEQ      |L26.94|
;;;227    	{
;;;228    		u32Div = (((u32Pclk / u32Clock2) + 1) >> 1) - 1;
000014  4639              MOV      r1,r7
000016  f7fffffe          BL       __aeabi_uidivmod
00001a  1c40              ADDS     r0,r0,#1
00001c  0844              LSRS     r4,r0,#1
00001e  1e64              SUBS     r4,r4,#1
;;;229    		if(u32Div > 0xFF)
000020  2cff              CMP      r4,#0xff
000022  d900              BLS      |L26.38|
;;;230    		    u32Div = 0xFF;
000024  24ff              MOVS     r4,#0xff
                  |L26.38|
;;;231    		
;;;232    		u32CalculatedSpeed = u32Pclk / (2*(u32Div+1));
000026  0061              LSLS     r1,r4,#1
000028  1c89              ADDS     r1,r1,#2
00002a  9800              LDR      r0,[sp,#0]
00002c  f7fffffe          BL       __aeabi_uidivmod
000030  4606              MOV      r6,r0
;;;233    		if(u32CalculatedSpeed > u32Clock2)
000032  42b8              CMP      r0,r7
000034  d900              BLS      |L26.56|
;;;234    			u32Div ++;			
000036  1c64              ADDS     r4,r4,#1
                  |L26.56|
;;;235    		
;;;236    		SpiPort->CLKDIV = (SpiPort->CLKDIV & ~SPI_CLKDIV_DIVIDER2_MASK) | (u32Div << 16);
000038  68a8              LDR      r0,[r5,#8]
00003a  21ff              MOVS     r1,#0xff
00003c  0409              LSLS     r1,r1,#16
00003e  4388              BICS     r0,r0,r1
000040  0421              LSLS     r1,r4,#16
                  |L26.66|
;;;237    	}
;;;238    	else
;;;239    		SpiPort->CLKDIV |= SPI_CLKDIV_DIVIDER2_MASK;
000042  4308              ORRS     r0,r0,r1
000044  60a8              STR      r0,[r5,#8]
;;;240    	
;;;241    	if(u32Clock1!=0)
000046  9803              LDR      r0,[sp,#0xc]
000048  2800              CMP      r0,#0
00004a  d026              BEQ      |L26.154|
;;;242    	{
;;;243    		u32Div = ((u32Pclk / u32Clock1) >> 1);
00004c  4601              MOV      r1,r0
00004e  9800              LDR      r0,[sp,#0]
000050  f7fffffe          BL       __aeabi_uidivmod
000054  0844              LSRS     r4,r0,#1
;;;244    		if(u32Div > 0x7F)
000056  2c7f              CMP      r4,#0x7f
000058  d905              BLS      |L26.102|
;;;245    		    u32Div = 0x7F;
00005a  247f              MOVS     r4,#0x7f
00005c  e005              B        |L26.106|
                  |L26.94|
00005e  68a8              LDR      r0,[r5,#8]            ;239
000060  21ff              MOVS     r1,#0xff              ;239
000062  0409              LSLS     r1,r1,#16             ;239
000064  e7ed              B        |L26.66|
                  |L26.102|
;;;246    		
;;;247    		if(u32Div == 0)
000066  2c00              CMP      r4,#0
000068  d015              BEQ      |L26.150|
                  |L26.106|
;;;248    			u32CalculatedSpeed = u32Pclk;
;;;249    		else
;;;250    			u32CalculatedSpeed = u32Pclk / (u32Div << 1);
00006a  0061              LSLS     r1,r4,#1
00006c  9800              LDR      r0,[sp,#0]
00006e  f7fffffe          BL       __aeabi_uidivmod
000072  4606              MOV      r6,r0
                  |L26.116|
;;;251    		
;;;252    		if(u32CalculatedSpeed > u32Clock1)
000074  9803              LDR      r0,[sp,#0xc]
000076  4286              CMP      r6,r0
000078  d905              BLS      |L26.134|
;;;253    		{	
;;;254    			u32Div ++;
00007a  1c64              ADDS     r4,r4,#1
;;;255    			u32CalculatedSpeed = u32Pclk / (u32Div << 1);
00007c  0061              LSLS     r1,r4,#1
00007e  9800              LDR      r0,[sp,#0]
000080  f7fffffe          BL       __aeabi_uidivmod
000084  4606              MOV      r6,r0
                  |L26.134|
;;;256    		}
;;;257    		
;;;258    		SpiPort->CLKDIV = (SpiPort->CLKDIV & ~SPI_CLKDIV_DIVIDER1_MASK) | u32Div;
000086  68a8              LDR      r0,[r5,#8]
000088  0a00              LSRS     r0,r0,#8
00008a  0200              LSLS     r0,r0,#8
00008c  4320              ORRS     r0,r0,r4
                  |L26.142|
;;;259    	}
;;;260    	else
;;;261    		SpiPort->CLKDIV |= SPI_CLKDIV_DIVIDER1_MASK;
00008e  60a8              STR      r0,[r5,#8]
;;;262    	
;;;263    	return u32CalculatedSpeed;
000090  4630              MOV      r0,r6
;;;264    }
000092  b005              ADD      sp,sp,#0x14
000094  bdf0              POP      {r4-r7,pc}
                  |L26.150|
000096  9e00              LDR      r6,[sp,#0]            ;248
000098  e7ec              B        |L26.116|
                  |L26.154|
00009a  68a8              LDR      r0,[r5,#8]            ;261
00009c  21ff              MOVS     r1,#0xff              ;261
00009e  4308              ORRS     r0,r0,r1              ;261
0000a0  e7f5              B        |L26.142|
;;;265    
                          ENDP


                          AREA ||i.SPI_SetFIFOMode||, CODE, READONLY, ALIGN=1

                  SPI_SetFIFOMode PROC
;;;498      */
;;;499    void SPI_SetFIFOMode(SPI_TypeDef *SpiPort, uint8_t bEnable, int32_t i32Interval)
000000  b510              PUSH     {r4,lr}
;;;500    {    
;;;501        SpiPort->CTL = (SpiPort->CTL & ~SPI_CTL_SP_CYCLE) | (i32Interval << 12);
000002  6803              LDR      r3,[r0,#0]
000004  240f              MOVS     r4,#0xf
000006  0324              LSLS     r4,r4,#12
000008  43a3              BICS     r3,r3,r4
00000a  0312              LSLS     r2,r2,#12
00000c  4313              ORRS     r3,r3,r2
00000e  6003              STR      r3,[r0,#0]
;;;502        if(bEnable)
;;;503        	SpiPort->CTL |= SPI_CTL_FIFOM;
000010  2201              MOVS     r2,#1
000012  0552              LSLS     r2,r2,#21
000014  2900              CMP      r1,#0                 ;502
;;;504        else
;;;505        	SpiPort->CTL &= ~SPI_CTL_FIFOM;
000016  6801              LDR      r1,[r0,#0]
000018  d001              BEQ      |L27.30|
00001a  4311              ORRS     r1,r1,r2              ;503
00001c  e000              B        |L27.32|
                  |L27.30|
00001e  4391              BICS     r1,r1,r2
                  |L27.32|
000020  6001              STR      r1,[r0,#0]            ;503
;;;506    }
000022  bd10              POP      {r4,pc}
;;;507    
                          ENDP


                          AREA ||i.SPI_SetRxPDMA||, CODE, READONLY, ALIGN=1

                  SPI_SetRxPDMA PROC
;;;425      */
;;;426    void SPI_SetRxPDMA(SPI_TypeDef *SpiPort, uint8_t bEnable)
000000  2202              MOVS     r2,#2
;;;427    {
;;;428    	if(bEnable)
000002  2900              CMP      r1,#0
;;;429    		SpiPort->PDMA |= SPI_PDMA_RX_DMA_EN;
;;;430    	else
;;;431    		SpiPort->PDMA &= ~SPI_PDMA_RX_DMA_EN;
000004  6b81              LDR      r1,[r0,#0x38]
000006  d001              BEQ      |L28.12|
000008  4311              ORRS     r1,r1,r2              ;429
00000a  e000              B        |L28.14|
                  |L28.12|
00000c  4391              BICS     r1,r1,r2
                  |L28.14|
00000e  6381              STR      r1,[r0,#0x38]         ;429
;;;432    }
000010  4770              BX       lr
;;;433    
                          ENDP


                          AREA ||i.SPI_SetSuspendCycle||, CODE, READONLY, ALIGN=1

                  SPI_SetSuspendCycle PROC
;;;199      */
;;;200    void SPI_SetSuspendCycle(SPI_TypeDef *SpiPort, int32_t i32Interval)
000000  6802              LDR      r2,[r0,#0]
;;;201    {
;;;202        if(SpiPort->CTL & SPI_CTL_FIFOM) 
;;;203        	SpiPort->CTL = (SpiPort->CTL & ~SPI_CTL_SP_CYCLE) | (i32Interval << 12);
000002  0309              LSLS     r1,r1,#12
000004  0293              LSLS     r3,r2,#10             ;202
000006  220f              MOVS     r2,#0xf
000008  0312              LSLS     r2,r2,#12
00000a  2b00              CMP      r3,#0                 ;202
;;;204        else 
;;;205        {    
;;;206        	assert_param(SPI_CHECK_BYTE_SUS);
;;;207    		SpiPort->CTL = (SpiPort->CTL & ~SPI_CTL_SP_CYCLE) | ((i32Interval-2) << 12);
00000c  6803              LDR      r3,[r0,#0]
00000e  da01              BGE      |L29.20|
000010  4393              BICS     r3,r3,r2              ;203
000012  e003              B        |L29.28|
                  |L29.20|
000014  4393              BICS     r3,r3,r2
000016  2201              MOVS     r2,#1
000018  0352              LSLS     r2,r2,#13
00001a  1a89              SUBS     r1,r1,r2
                  |L29.28|
00001c  430b              ORRS     r3,r3,r1              ;203
00001e  6003              STR      r3,[r0,#0]            ;203
;;;208    	}
;;;209    }
000020  4770              BX       lr
;;;210    
                          ENDP


                          AREA ||i.SPI_SetTxPDMA||, CODE, READONLY, ALIGN=1

                  SPI_SetTxPDMA PROC
;;;411      */
;;;412    void SPI_SetTxPDMA(SPI_TypeDef *SpiPort, uint8_t bEnable)
000000  2900              CMP      r1,#0
;;;413    {
;;;414    	if(bEnable)
;;;415    		SpiPort->PDMA |= SPI_PDMA_TX_DMA_EN;
;;;416    	else
;;;417    		SpiPort->PDMA &= ~SPI_PDMA_TX_DMA_EN;
000002  6b81              LDR      r1,[r0,#0x38]
000004  d002              BEQ      |L30.12|
000006  2201              MOVS     r2,#1                 ;415
000008  4311              ORRS     r1,r1,r2              ;415
00000a  e001              B        |L30.16|
                  |L30.12|
00000c  0849              LSRS     r1,r1,#1
00000e  0049              LSLS     r1,r1,#1
                  |L30.16|
000010  6381              STR      r1,[r0,#0x38]         ;415
;;;418    }
000012  4770              BX       lr
;;;419    
                          ENDP


                          AREA ||i.SPI_SetTxRegister||, CODE, READONLY, ALIGN=1

                  SPI_SetTxRegister PROC
;;;393      */
;;;394    uint32_t SPI_SetTxRegister(SPI_TypeDef *SpiPort, uint32_t *pu32Buf, uint32_t u32DataCount)
000000  680b              LDR      r3,[r1,#0]
;;;395    {
;;;396    	assert_param(SPI_CHECK_SET_DATAREG_NUM);
;;;397    	
;;;398    	SpiPort->TX0 = pu32Buf[0];
000002  6203              STR      r3,[r0,#0x20]
;;;399    	
;;;400    	if(u32DataCount == 2)
000004  2a02              CMP      r2,#2
000006  d101              BNE      |L31.12|
;;;401    		SpiPort->TX1 = pu32Buf[1];
000008  6849              LDR      r1,[r1,#4]
00000a  6241              STR      r1,[r0,#0x24]
                  |L31.12|
;;;402    		
;;;403        return u32DataCount;
00000c  4610              MOV      r0,r2
;;;404    }
00000e  4770              BX       lr
;;;405    
                          ENDP


                          AREA ||i.SPI_SingleRead||, CODE, READONLY, ALIGN=1

                  SPI_SingleRead PROC
;;;340      */
;;;341    uint8_t SPI_SingleRead(SPI_TypeDef *SpiPort, uint32_t *pu32Data)
000000  6802              LDR      r2,[r0,#0]
;;;342    {
;;;343    	if(SpiPort->CTL & SPI_CTL_GO_BUSY)
000002  07d2              LSLS     r2,r2,#31
000004  d001              BEQ      |L32.10|
;;;344    		return FALSE;
000006  2000              MOVS     r0,#0
;;;345    
;;;346    	*pu32Data = SpiPort->RX0;
;;;347    	SpiPort->CTL |= SPI_CTL_GO_BUSY;
;;;348    	return TRUE;
;;;349    }
000008  4770              BX       lr
                  |L32.10|
00000a  6902              LDR      r2,[r0,#0x10]         ;346
00000c  600a              STR      r2,[r1,#0]            ;347
00000e  6801              LDR      r1,[r0,#0]            ;347
000010  2201              MOVS     r2,#1                 ;347
000012  4311              ORRS     r1,r1,r2              ;347
000014  6001              STR      r1,[r0,#0]            ;347
000016  4610              MOV      r0,r2                 ;348
000018  4770              BX       lr
;;;350    
                          ENDP


                          AREA ||i.SPI_SingleWrite||, CODE, READONLY, ALIGN=1

                  SPI_SingleWrite PROC
;;;357      */
;;;358    uint8_t SPI_SingleWrite(SPI_TypeDef *SpiPort, uint32_t *pu32Data)
000000  6802              LDR      r2,[r0,#0]
;;;359    {
;;;360    	if(SpiPort->CTL & SPI_CTL_GO_BUSY)
000002  07d2              LSLS     r2,r2,#31
000004  d001              BEQ      |L33.10|
;;;361    		return FALSE;
000006  2000              MOVS     r0,#0
;;;362    
;;;363    	SpiPort->TX0 = *pu32Data;
;;;364    	SpiPort->CTL |= SPI_CTL_GO_BUSY;
;;;365    	return TRUE;
;;;366    }
000008  4770              BX       lr
                  |L33.10|
00000a  6809              LDR      r1,[r1,#0]            ;363
00000c  6201              STR      r1,[r0,#0x20]         ;363
00000e  6801              LDR      r1,[r0,#0]            ;364
000010  2201              MOVS     r2,#1                 ;364
000012  4311              ORRS     r1,r1,r2              ;364
000014  6001              STR      r1,[r0,#0]            ;364
000016  4610              MOV      r0,r2                 ;365
000018  4770              BX       lr
;;;367    
                          ENDP


                          AREA ||i.SPI_WakeupConfigure||, CODE, READONLY, ALIGN=1

                  SPI_WakeupConfigure PROC
;;;482      */
;;;483    void SPI_WakeupConfigure(SPI_TypeDef *SpiPort, uint8_t bEnable)
000000  2900              CMP      r1,#0
;;;484    {
;;;485    	if(bEnable)
;;;486    		SpiPort->CTL |= SPI_CTL_WKEUP_EN;
;;;487    	else
;;;488    		SpiPort->CTL &= ~SPI_CTL_WKEUP_EN;
000002  6801              LDR      r1,[r0,#0]
000004  d003              BEQ      |L34.14|
000006  2201              MOVS     r2,#1                 ;486
000008  07d2              LSLS     r2,r2,#31             ;486
00000a  4311              ORRS     r1,r1,r2              ;486
00000c  e001              B        |L34.18|
                  |L34.14|
00000e  0049              LSLS     r1,r1,#1
000010  0849              LSRS     r1,r1,#1
                  |L34.18|
000012  6001              STR      r1,[r0,#0]            ;486
;;;489    }
000014  4770              BX       lr
;;;490    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\bsp\\Driver\\nano1xx_spi.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_spi_c_SPI_Init____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___13_nano1xx_spi_c_SPI_Init____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___13_nano1xx_spi_c_SPI_Init____REVSH|
#line 130
|__asm___13_nano1xx_spi_c_SPI_Init____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
