; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o.\obj\system_nano1xx.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_nano1xx.d --cpu=Cortex-M0 --apcs=interwork -I..\inc -I..\drv -I..\bsp -I..\bsp\Cmsis -I..\bsp\Driver -I..\bsp\system -I..\lib -I..\lib\libtk -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB -D__LCDDISPLAY_BTL001_H --omf_browse=.\obj\system_nano1xx.crf ..\bsp\Cmsis\system_nano1xx.c]
                          THUMB

                          AREA ||i.SysGet_HCLKFreq||, CODE, READONLY, ALIGN=2

                  SysGet_HCLKFreq PROC
;;;112      */
;;;113    uint32_t SysGet_HCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;114    {
;;;115    	
;;;116    	uint32_t u32Freqout, u32AHBDivider, u32ClkSel;
;;;117    
;;;118    	u32ClkSel = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_MASK;
000002  4c0d              LDR      r4,|L1.56|
000004  6920              LDR      r0,[r4,#0x10]
000006  0741              LSLS     r1,r0,#29
;;;119    
;;;120    	if (u32ClkSel == CLK_CLKSEL0_HCLK_HXT)	/* external HXT crystal clock */
;;;121    	{
;;;122    		u32Freqout = __XTAL;	
000008  480c              LDR      r0,|L1.60|
00000a  0f49              LSRS     r1,r1,#29             ;118
00000c  d00d              BEQ      |L1.42|
;;;123    	}
;;;124    	else if(u32ClkSel == CLK_CLKSEL0_HCLK_LXT)		/* external LXT crystal clock */ 
00000e  2901              CMP      r1,#1
000010  d004              BEQ      |L1.28|
;;;125    	{
;;;126    		u32Freqout = __RTC_XTAL;
;;;127    	}
;;;128    	else if(u32ClkSel == CLK_CLKSEL0_HCLK_PLL)		/* PLL clock */
000012  2902              CMP      r1,#2
000014  d005              BEQ      |L1.34|
;;;129    	{
;;;130    		u32Freqout = SysGet_PLLClockFreq();
;;;131    	}
;;;132    	else if(u32ClkSel == CLK_CLKSEL0_HCLK_LIRC)	/* internal LIRC oscillator clock */
000016  2903              CMP      r1,#3
000018  d006              BEQ      |L1.40|
00001a  e006              B        |L1.42|
                  |L1.28|
00001c  2001              MOVS     r0,#1                 ;126
00001e  03c0              LSLS     r0,r0,#15             ;126
000020  e003              B        |L1.42|
                  |L1.34|
000022  f7fffffe          BL       SysGet_PLLClockFreq
000026  e000              B        |L1.42|
                  |L1.40|
;;;133    	{
;;;134    	 	u32Freqout = __IRC10K;
000028  4805              LDR      r0,|L1.64|
                  |L1.42|
;;;135    	}
;;;136    	else									/* internal HIRC oscillator clock */
;;;137    	{
;;;138    	 	u32Freqout = __IRC12M;
;;;139    	
;;;140    	}
;;;141    	u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK_MASK) + 1 ;
00002a  69e1              LDR      r1,[r4,#0x1c]
00002c  0709              LSLS     r1,r1,#28
00002e  0f09              LSRS     r1,r1,#28
000030  1c49              ADDS     r1,r1,#1
;;;142    	
;;;143    	return (u32Freqout/u32AHBDivider);	
000032  f7fffffe          BL       __aeabi_uidivmod
;;;144    }
000036  bd10              POP      {r4,pc}
;;;145    
                          ENDP

                  |L1.56|
                          DCD      0x50000200
                  |L1.60|
                          DCD      0x00b71b00
                  |L1.64|
                          DCD      0x00002710

                          AREA ||i.SysGet_PLLClockFreq||, CODE, READONLY, ALIGN=2

                  SysGet_PLLClockFreq PROC
;;;74       */
;;;75     uint32_t SysGet_PLLClockFreq(void)
000000  b510              PUSH     {r4,lr}
;;;76     {
;;;77     	uint32_t u32Freq =0, u32PLLSrc;
;;;78         uint32_t u32NO, u32NR, u32IN_DV, u32PllReg;
;;;79     
;;;80     	u32PllReg = CLK->PLLCTL;
000002  4812              LDR      r0,|L2.76|
000004  6a40              LDR      r0,[r0,#0x24]
;;;81     
;;;82     	if (u32PllReg & CLK_PLLCTL_PD)  
000006  03c1              LSLS     r1,r0,#15
000008  d501              BPL      |L2.14|
;;;83     		return 0;	 /* PLL is in power down mode */
00000a  2000              MOVS     r0,#0
;;;84     	
;;;85     	if (u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
;;;86     		u32PLLSrc = __IRC12M;
;;;87     	else
;;;88     		u32PLLSrc = __XTAL;
;;;89     
;;;90         u32NO = (u32PllReg & CLK_PLLCTL_OUT_DV) ? 2: 1;
;;;91     
;;;92     	u32IN_DV = (u32PllReg & CLK_PLLCTL_IN_DIVIDER_MASK) >> 8;
;;;93     	if (u32IN_DV == 0)
;;;94     		u32NR = 2;
;;;95     	else if (u32IN_DV == 1)
;;;96     		u32NR = 4;
;;;97     	else if (u32IN_DV == 2)
;;;98     		u32NR = 8;
;;;99     	else
;;;100    		u32NR = 16;
;;;101    
;;;102    	u32Freq = u32PLLSrc * ((u32PllReg & CLK_PLLCTL_FB_DIVIDER_MASK) +32) / u32NR / u32NO;
;;;103    
;;;104    	return u32Freq;
;;;105    }
00000c  bd10              POP      {r4,pc}
                  |L2.14|
00000e  04c1              LSLS     r1,r0,#19             ;90
000010  d501              BPL      |L2.22|
000012  2402              MOVS     r4,#2                 ;90
000014  e000              B        |L2.24|
                  |L2.22|
000016  2401              MOVS     r4,#1                 ;90
                  |L2.24|
000018  0581              LSLS     r1,r0,#22             ;92
00001a  0f89              LSRS     r1,r1,#30             ;92
00001c  d00f              BEQ      |L2.62|
00001e  2901              CMP      r1,#1                 ;95
000020  d00f              BEQ      |L2.66|
000022  2902              CMP      r1,#2                 ;97
000024  d00f              BEQ      |L2.70|
000026  2110              MOVS     r1,#0x10              ;100
                  |L2.40|
000028  0680              LSLS     r0,r0,#26             ;102
00002a  0e80              LSRS     r0,r0,#26             ;102
00002c  4a08              LDR      r2,|L2.80|
00002e  3020              ADDS     r0,r0,#0x20           ;102
000030  4350              MULS     r0,r2,r0              ;102
000032  f7fffffe          BL       __aeabi_uidivmod
000036  4621              MOV      r1,r4                 ;102
000038  f7fffffe          BL       __aeabi_uidivmod
00003c  bd10              POP      {r4,pc}
                  |L2.62|
00003e  2102              MOVS     r1,#2                 ;94
000040  e7f2              B        |L2.40|
                  |L2.66|
000042  2104              MOVS     r1,#4                 ;96
000044  e7f0              B        |L2.40|
                  |L2.70|
000046  2108              MOVS     r1,#8                 ;98
000048  e7ee              B        |L2.40|
;;;106    
                          ENDP

00004a  0000              DCW      0x0000
                  |L2.76|
                          DCD      0x50000200
                  |L2.80|
                          DCD      0x00b71b00

                          AREA ||i.SysInit_Clock||, CODE, READONLY, ALIGN=2

                  SysInit_Clock PROC
;;;146    
;;;147    void SysInit_Clock(void)
000000  b5f8              PUSH     {r3-r7,lr}
;;;148    {
;;;149      __IO uint32_t delayCnt;
;;;150     
;;;151      /* Enable system clock source, HIRC and LIRC are default enabled */	
;;;152      UNLOCKREG();
000002  491e              LDR      r1,|L3.124|
000004  2259              MOVS     r2,#0x59
000006  600a              STR      r2,[r1,#0]
000008  2316              MOVS     r3,#0x16
00000a  600b              STR      r3,[r1,#0]
00000c  2688              MOVS     r6,#0x88
00000e  600e              STR      r6,[r1,#0]
;;;153      CLK->PWRCTL |= (CLK_PWRCTL_HXT_EN | CLK_PWRCTL_LXT_EN);	   
000010  481b              LDR      r0,|L3.128|
000012  6804              LDR      r4,[r0,#0]
000014  2503              MOVS     r5,#3
000016  432c              ORRS     r4,r4,r5
000018  6004              STR      r4,[r0,#0]
;;;154      LOCKREG();
00001a  2400              MOVS     r4,#0
00001c  600c              STR      r4,[r1,#0]
;;;155    
;;;156      /* Enable PLL out to 96MHz */
;;;157      CLK->PLLCTL = (CLK_PLLCTL_PLLSRC_HXT | PLL_IN_12M_OUT_96M);
00001e  25ff              MOVS     r5,#0xff
000020  3501              ADDS     r5,#1
000022  6245              STR      r5,[r0,#0x24]
;;;158    
;;;159      /* Waits for PLL clock stable */
;;;160      for (delayCnt=0; delayCnt<100000; delayCnt++)	
000024  4625              MOV      r5,r4
                  |L3.38|
;;;161    		if (CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB)	break;
000026  68c7              LDR      r7,[r0,#0xc]
000028  077f              LSLS     r7,r7,#29
00002a  d403              BMI      |L3.52|
00002c  4f15              LDR      r7,|L3.132|
00002e  1c6d              ADDS     r5,r5,#1              ;160
000030  42bd              CMP      r5,r7                 ;160
000032  d3f8              BCC      |L3.38|
                  |L3.52|
;;;162    
;;;163      /* Change HCLK to PLL output */		  
;;;164      if (delayCnt < 100000) {
000034  4f13              LDR      r7,|L3.132|
000036  42bd              CMP      r5,r7
000038  d20d              BCS      |L3.86|
;;;165    	  CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_MASK) | 2; /* divider is 3 */
00003a  69c5              LDR      r5,[r0,#0x1c]
00003c  092d              LSRS     r5,r5,#4
00003e  012d              LSLS     r5,r5,#4
000040  1cad              ADDS     r5,r5,#2
000042  61c5              STR      r5,[r0,#0x1c]
;;;166    	  UNLOCKREG();
000044  600a              STR      r2,[r1,#0]
000046  600b              STR      r3,[r1,#0]
000048  600e              STR      r6,[r1,#0]
;;;167          CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_MASK) | CLK_CLKSEL0_HCLK_PLL;	 /* HCLK = 32MHz */
00004a  6905              LDR      r5,[r0,#0x10]
00004c  08ed              LSRS     r5,r5,#3
00004e  00ed              LSLS     r5,r5,#3
000050  1cad              ADDS     r5,r5,#2
000052  6105              STR      r5,[r0,#0x10]
;;;168          LOCKREG();
000054  600c              STR      r4,[r1,#0]
                  |L3.86|
;;;169      }
;;;170    
;;;171      /* Set HCLK back to HIRC if error happens */
;;;172      if (CLK->CLKSTATUS  & CLK_CLKSTATUS_CLK_SW_FAIL) 	{
000056  68c5              LDR      r5,[r0,#0xc]
000058  062d              LSLS     r5,r5,#24
00005a  d50b              BPL      |L3.116|
;;;173    	  CLK->CLKDIV0 &= ~CLK_CLKDIV0_HCLK_MASK; /* divider is 0 */
00005c  69c5              LDR      r5,[r0,#0x1c]
00005e  092d              LSRS     r5,r5,#4
000060  012d              LSLS     r5,r5,#4
000062  61c5              STR      r5,[r0,#0x1c]
;;;174    	  UNLOCKREG();
000064  600a              STR      r2,[r1,#0]
000066  600b              STR      r3,[r1,#0]
000068  600e              STR      r6,[r1,#0]
;;;175          CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_MASK) | CLK_CLKSEL0_HCLK_HIRC;	 /* HCLK = 12MHz */
00006a  6902              LDR      r2,[r0,#0x10]
00006c  2307              MOVS     r3,#7
00006e  431a              ORRS     r2,r2,r3
000070  6102              STR      r2,[r0,#0x10]
;;;176          LOCKREG();
000072  600c              STR      r4,[r1,#0]
                  |L3.116|
;;;177      }  
;;;178    
;;;179      /* Update CPU Clock Frequency */
;;;180      SystemCoreClockUpdate();
000074  f7fffffe          BL       SystemCoreClockUpdate
;;;181    }
000078  bdf8              POP      {r3-r7,pc}
;;;182    
                          ENDP

00007a  0000              DCW      0x0000
                  |L3.124|
                          DCD      0x50000100
                  |L3.128|
                          DCD      0x50000200
                  |L3.132|
                          DCD      0x000186a0

                          AREA ||i.SysInit_DebugConsole||, CODE, READONLY, ALIGN=2

                  SysInit_DebugConsole PROC
;;;42     
;;;43     void SysInit_DebugConsole()
000000  2105              MOVS     r1,#5
;;;44     {
;;;45     
;;;46       /* Enable UART0 for debug console */
;;;47       GCR->PB_L_MFP = (GCR->PB_L_MFP & ~0x77) | (PB1_MFP_UART0_TX | PB0_MFP_UART0_RX);  /* Select multi-function pin for UART0 */
000002  0709              LSLS     r1,r1,#28
000004  6b88              LDR      r0,[r1,#0x38]
000006  2277              MOVS     r2,#0x77
000008  4390              BICS     r0,r0,r2
00000a  3011              ADDS     r0,r0,#0x11
00000c  6388              STR      r0,[r1,#0x38]
;;;48       CLK->APBCLK |= CLK_APBCLK_UART0_EN;    /* Enable UART0 clock */
00000e  480a              LDR      r0,|L4.56|
000010  6881              LDR      r1,[r0,#8]
000012  01c2              LSLS     r2,r0,#7
000014  4311              ORRS     r1,r1,r2
000016  6081              STR      r1,[r0,#8]
;;;49       CLK->CLKDIV0 &= ~CLK_CLKDIV0_UART_MASK;
000018  69c1              LDR      r1,[r0,#0x1c]
00001a  220f              MOVS     r2,#0xf
00001c  0212              LSLS     r2,r2,#8
00001e  4391              BICS     r1,r1,r2
000020  61c1              STR      r1,[r0,#0x1c]
;;;50       CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UART_MASK) | CLK_CLKSEL1_UART_HXT;  /* Select 12 Mhz XTAL */
000022  6941              LDR      r1,[r0,#0x14]
000024  0889              LSRS     r1,r1,#2
000026  0089              LSLS     r1,r1,#2
000028  6141              STR      r1,[r0,#0x14]
;;;51     
;;;52       UART0->BAUD = 0x67;              /* Baud Rate:115200  OSC:12MHz */
00002a  4804              LDR      r0,|L4.60|
00002c  2167              MOVS     r1,#0x67
00002e  6241              STR      r1,[r0,#0x24]
;;;53       UART0->TLCTL = 0x03;             /* Character len is 8 bits */
000030  2103              MOVS     r1,#3
000032  6081              STR      r1,[r0,#8]
;;;54     
;;;55     
;;;56     }
000034  4770              BX       lr
;;;57     
                          ENDP

000036  0000              DCW      0x0000
                  |L4.56|
                          DCD      0x50000200
                  |L4.60|
                          DCD      0x40050000

                          AREA ||i.SysInit_PinFunc||, CODE, READONLY, ALIGN=1

                  SysInit_PinFunc PROC
;;;60      *----------------------------------------------------------------------------*/
;;;61     void SysInit_PinFunc(void)
000000  4770              BX       lr
;;;62     {
;;;63     	/* Select pin function at here. */
;;;64     }
;;;65     
                          ENDP


                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;182    
;;;183    void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
000000  b510              PUSH     {r4,lr}
;;;184    {
;;;185      SystemCoreClock = SysGet_HCLKFreq();
000002  f7fffffe          BL       SysGet_HCLKFreq
000006  4901              LDR      r1,|L6.12|
000008  6008              STR      r0,[r1,#0]  ; SystemCoreClock
;;;186    }
00000a  bd10              POP      {r4,pc}
;;;187    
                          ENDP

                  |L6.12|
                          DCD      ||.data||

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=1

                  SystemInit PROC
;;;196     */
;;;197    void SystemInit (void)
000000  b510              PUSH     {r4,lr}
;;;198    {
;;;199    /* ToDo: add code to initialize the system
;;;200             do not use global variables because this function is called before
;;;201             reaching pre-main. RW section maybe overwritten afterwards.          */
;;;202    
;;;203    
;;;204      //SystemCoreClock = __SYSTEM_CLOCK;
;;;205      /* Init CPU clock */
;;;206      SysInit_Clock();
000002  f7fffffe          BL       SysInit_Clock
;;;207    
;;;208      /* Select pin functions */
;;;209      SysInit_PinFunc();
;;;210    
;;;211      /* Enable UART0 as debug console */
;;;212      SysInit_DebugConsole();
000006  f7fffffe          BL       SysInit_DebugConsole
;;;213    
;;;214    }
00000a  bd10              POP      {r4,pc}
                          ENDP


                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x00b71b00

;*** Start embedded assembler ***

#line 1 "..\\bsp\\Cmsis\\system_nano1xx.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___16_system_nano1xx_c_5d646a67____REV16|
#line 115 "C:\\Keil\\ARM\\CMSIS\\Include\\core_cmInstr.h"
|__asm___16_system_nano1xx_c_5d646a67____REV16| PROC
#line 116

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___16_system_nano1xx_c_5d646a67____REVSH|
#line 130
|__asm___16_system_nano1xx_c_5d646a67____REVSH| PROC
#line 131

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
