; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\adc.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\adc.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\Device\Nuvoton\Nano1X2Series\Include -I..\..\..\..\Library\StdDriver\inc -I..\..\..\..\Library\CMSIS\Include -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\adc.crf ..\..\..\..\Library\StdDriver\src\adc.c]
                          THUMB

                          AREA ||i.ADC_Close||, CODE, READONLY, ALIGN=1

                  ADC_Close PROC
;;;57       */
;;;58     void ADC_Close(ADC_T *adc)
000000  2005              MOVS     r0,#5
;;;59     {
;;;60         SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_ADC_RST_Msk;
000002  0700              LSLS     r0,r0,#28
000004  68c2              LDR      r2,[r0,#0xc]
000006  2101              MOVS     r1,#1
000008  0709              LSLS     r1,r1,#28
00000a  430a              ORRS     r2,r2,r1
00000c  60c2              STR      r2,[r0,#0xc]
;;;61         SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_ADC_RST_Msk;
00000e  68c2              LDR      r2,[r0,#0xc]
000010  438a              BICS     r2,r2,r1
000012  60c2              STR      r2,[r0,#0xc]
;;;62         return;
;;;63     
;;;64     }
000014  4770              BX       lr
;;;65     
                          ENDP


                          AREA ||i.ADC_DisableHWTrigger||, CODE, READONLY, ALIGN=2

                  ADC_DisableHWTrigger PROC
;;;98       */
;;;99     void ADC_DisableHWTrigger(ADC_T *adc)
000000  4803              LDR      r0,|L2.16|
;;;100    {
;;;101        ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk);
000002  6881              LDR      r1,[r0,#8]
000004  22ff              MOVS     r2,#0xff
000006  32f1              ADDS     r2,r2,#0xf1
000008  4391              BICS     r1,r1,r2
00000a  6081              STR      r1,[r0,#8]
;;;102        return;
;;;103    }
00000c  4770              BX       lr
;;;104    
                          ENDP

00000e  0000              DCW      0x0000
                  |L2.16|
                          DCD      0x400e0040

                          AREA ||i.ADC_DisableInt||, CODE, READONLY, ALIGN=2

                  ADC_DisableInt PROC
;;;185      */
;;;186    void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
000000  07cb              LSLS     r3,r1,#31
;;;187    {
;;;188        if(u32Mask & ADC_ADF_INT)
;;;189            ADC->CR &= ~ADC_CR_ADIE_Msk;
000002  4809              LDR      r0,|L3.40|
000004  2202              MOVS     r2,#2
000006  2b00              CMP      r3,#0                 ;188
000008  d002              BEQ      |L3.16|
00000a  6883              LDR      r3,[r0,#8]
00000c  4393              BICS     r3,r3,r2
00000e  6083              STR      r3,[r0,#8]
                  |L3.16|
;;;190        if(u32Mask & ADC_CMP0_INT)
000010  078b              LSLS     r3,r1,#30
000012  d502              BPL      |L3.26|
;;;191            ADC->CMPR0 &= ~ADC_CMPR_CMPIE_Msk;
000014  6903              LDR      r3,[r0,#0x10]
000016  4393              BICS     r3,r3,r2
000018  6103              STR      r3,[r0,#0x10]
                  |L3.26|
;;;192        if(u32Mask & ADC_CMP1_INT)
00001a  0749              LSLS     r1,r1,#29
00001c  d502              BPL      |L3.36|
;;;193            ADC->CMPR1 &= ~ADC_CMPR_CMPIE_Msk;
00001e  6941              LDR      r1,[r0,#0x14]
000020  4391              BICS     r1,r1,r2
000022  6141              STR      r1,[r0,#0x14]
                  |L3.36|
;;;194    
;;;195        return;
;;;196    }
000024  4770              BX       lr
;;;197    
                          ENDP

000026  0000              DCW      0x0000
                  |L3.40|
                          DCD      0x400e0040

                          AREA ||i.ADC_DisableTimerTrigger||, CODE, READONLY, ALIGN=2

                  ADC_DisableTimerTrigger PROC
;;;126      */
;;;127    void ADC_DisableTimerTrigger(ADC_T *adc)
000000  4803              LDR      r0,|L4.16|
;;;128    {
;;;129        ADC->CR &= ~ADC_CR_TMTRGMOD_Msk;
000002  6881              LDR      r1,[r0,#8]
000004  2201              MOVS     r2,#1
000006  03d2              LSLS     r2,r2,#15
000008  4391              BICS     r1,r1,r2
00000a  6081              STR      r1,[r0,#8]
;;;130    
;;;131        return;
;;;132    }
00000c  4770              BX       lr
;;;133    
                          ENDP

00000e  0000              DCW      0x0000
                  |L4.16|
                          DCD      0x400e0040

                          AREA ||i.ADC_EnableHWTrigger||, CODE, READONLY, ALIGN=2

                  ADC_EnableHWTrigger PROC
;;;79       */
;;;80     void ADC_EnableHWTrigger(ADC_T *adc,
000000  b510              PUSH     {r4,lr}
;;;81                              uint32_t u32Source,
;;;82                              uint32_t u32Param)
;;;83     {
;;;84         ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk);
000002  4809              LDR      r0,|L5.40|
000004  6883              LDR      r3,[r0,#8]
000006  24ff              MOVS     r4,#0xff
000008  34f1              ADDS     r4,r4,#0xf1
00000a  43a3              BICS     r3,r3,r4
00000c  6083              STR      r3,[r0,#8]
;;;85         if(u32Source == ADC_TRIGGER_BY_EXT_PIN) {
;;;86             ADC->CR |= u32Source | u32Param | ADC_CR_TRGE_Msk;
00000e  1583              ASRS     r3,r0,#22
000010  2900              CMP      r1,#0                 ;85
000012  d004              BEQ      |L5.30|
;;;87         } else {
;;;88             ADC->CR |= u32Source | ADC_CR_TRGE_Msk;
000014  6882              LDR      r2,[r0,#8]
000016  4319              ORRS     r1,r1,r3
000018  430a              ORRS     r2,r2,r1
00001a  6082              STR      r2,[r0,#8]
;;;89         }
;;;90     
;;;91         return;
;;;92     }
00001c  bd10              POP      {r4,pc}
                  |L5.30|
00001e  6881              LDR      r1,[r0,#8]            ;86
000020  431a              ORRS     r2,r2,r3              ;86
000022  4311              ORRS     r1,r1,r2              ;86
000024  6081              STR      r1,[r0,#8]            ;86
000026  bd10              POP      {r4,pc}
;;;93     
                          ENDP

                  |L5.40|
                          DCD      0x400e0040

                          AREA ||i.ADC_EnableInt||, CODE, READONLY, ALIGN=2

                  ADC_EnableInt PROC
;;;162      */
;;;163    void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
000000  07cb              LSLS     r3,r1,#31
;;;164    {
;;;165        if(u32Mask & ADC_ADF_INT)
;;;166            ADC->CR |= ADC_CR_ADIE_Msk;
000002  4809              LDR      r0,|L6.40|
000004  2202              MOVS     r2,#2
000006  2b00              CMP      r3,#0                 ;165
000008  d002              BEQ      |L6.16|
00000a  6883              LDR      r3,[r0,#8]
00000c  4313              ORRS     r3,r3,r2
00000e  6083              STR      r3,[r0,#8]
                  |L6.16|
;;;167        if(u32Mask & ADC_CMP0_INT)
000010  078b              LSLS     r3,r1,#30
000012  d502              BPL      |L6.26|
;;;168            ADC->CMPR0 |= ADC_CMPR_CMPIE_Msk;
000014  6903              LDR      r3,[r0,#0x10]
000016  4313              ORRS     r3,r3,r2
000018  6103              STR      r3,[r0,#0x10]
                  |L6.26|
;;;169        if(u32Mask & ADC_CMP1_INT)
00001a  0749              LSLS     r1,r1,#29
00001c  d502              BPL      |L6.36|
;;;170            ADC->CMPR1 |= ADC_CMPR_CMPIE_Msk;
00001e  6941              LDR      r1,[r0,#0x14]
000020  4311              ORRS     r1,r1,r2
000022  6141              STR      r1,[r0,#0x14]
                  |L6.36|
;;;171    
;;;172        return;
;;;173    }
000024  4770              BX       lr
;;;174    
                          ENDP

000026  0000              DCW      0x0000
                  |L6.40|
                          DCD      0x400e0040

                          AREA ||i.ADC_EnableTimerTrigger||, CODE, READONLY, ALIGN=2

                  ADC_EnableTimerTrigger PROC
;;;111      */
;;;112    void ADC_EnableTimerTrigger(ADC_T *adc,
000000  b510              PUSH     {r4,lr}
;;;113                                uint32_t u32Source,
;;;114                                uint32_t u32PDMACnt)
;;;115    {
;;;116        ADC->CR &= ~(ADC_CR_TMPDMACNT_Msk | ADC_CR_TMSEL_Msk);
000002  4807              LDR      r0,|L7.32|
000004  6883              LDR      r3,[r0,#8]
000006  4c07              LDR      r4,|L7.36|
000008  4023              ANDS     r3,r3,r4
00000a  6083              STR      r3,[r0,#8]
;;;117        ADC->CR |= (u32PDMACnt << ADC_CR_TMPDMACNT_Pos) | (u32Source << ADC_CR_TMSEL_Pos) | ADC_CR_TMTRGMOD_Msk;
00000c  6883              LDR      r3,[r0,#8]
00000e  0612              LSLS     r2,r2,#24
000010  4313              ORRS     r3,r3,r2
000012  0309              LSLS     r1,r1,#12
000014  2201              MOVS     r2,#1
000016  03d2              LSLS     r2,r2,#15
000018  4311              ORRS     r1,r1,r2
00001a  430b              ORRS     r3,r3,r1
00001c  6083              STR      r3,[r0,#8]
;;;118    
;;;119        return;
;;;120    }
00001e  bd10              POP      {r4,pc}
;;;121    
                          ENDP

                  |L7.32|
                          DCD      0x400e0040
                  |L7.36|
                          DCD      0x00ffcfff

                          AREA ||i.ADC_Open||, CODE, READONLY, ALIGN=2

                  ADC_Open PROC
;;;39       */
;;;40     void ADC_Open(ADC_T *adc,
000000  b530              PUSH     {r4,r5,lr}
;;;41                   uint32_t u32InputMode,
;;;42                   uint32_t u32OpMode,
;;;43                   uint32_t u32ChMask)
;;;44     {
;;;45     
;;;46         ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32InputMode;
000002  4808              LDR      r0,|L8.36|
000004  6884              LDR      r4,[r0,#8]
000006  1505              ASRS     r5,r0,#20
000008  43ac              BICS     r4,r4,r5
00000a  430c              ORRS     r4,r4,r1
00000c  6084              STR      r4,[r0,#8]
;;;47         ADC->CR = (ADC->CR & ~ADC_CR_ADMD_Msk) | u32OpMode;
00000e  6881              LDR      r1,[r0,#8]
000010  240c              MOVS     r4,#0xc
000012  43a1              BICS     r1,r1,r4
000014  4311              ORRS     r1,r1,r2
000016  6081              STR      r1,[r0,#8]
;;;48         ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk);
000018  6881              LDR      r1,[r0,#8]
00001a  03a2              LSLS     r2,r4,#14
00001c  4391              BICS     r1,r1,r2
00001e  6081              STR      r1,[r0,#8]
;;;49         ADC->CHEN  = u32ChMask;
000020  60c3              STR      r3,[r0,#0xc]
;;;50         return;
;;;51     }
000022  bd30              POP      {r4,r5,pc}
;;;52     
                          ENDP

                  |L8.36|
                          DCD      0x400e0040

                          AREA ||i.ADC_SetExtraSampleTime||, CODE, READONLY, ALIGN=2

                  ADC_SetExtraSampleTime PROC
;;;140      */
;;;141    void ADC_SetExtraSampleTime(ADC_T *adc,
000000  b510              PUSH     {r4,lr}
;;;142                                uint32_t u32ChNum,
;;;143                                uint32_t u32SampleTime)
;;;144    {
;;;145    
;;;146        if (u32ChNum < 8)
;;;147            ADC->SMPLCNT0 = (ADC->SMPLCNT0 & ~(ADC_SMPLCNT0_CH0SAMPCNT_Msk << (u32ChNum * 4))) | (u32SampleTime << (u32ChNum * 4));
000002  4b0a              LDR      r3,|L9.44|
000004  2908              CMP      r1,#8                 ;146
000006  d208              BCS      |L9.26|
000008  6b1c              LDR      r4,[r3,#0x30]
00000a  0088              LSLS     r0,r1,#2
00000c  210f              MOVS     r1,#0xf
00000e  4081              LSLS     r1,r1,r0
000010  438c              BICS     r4,r4,r1
000012  4082              LSLS     r2,r2,r0
000014  4314              ORRS     r4,r4,r2
000016  631c              STR      r4,[r3,#0x30]
;;;148        else
;;;149            ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~ADC_SMPLCNT1_INTCHSAMPCNT_Msk) | (u32SampleTime << ADC_SMPLCNT1_INTCHSAMPCNT_Pos);
;;;150    }
000018  bd10              POP      {r4,pc}
                  |L9.26|
00001a  6b58              LDR      r0,[r3,#0x34]         ;149
00001c  210f              MOVS     r1,#0xf               ;149
00001e  0409              LSLS     r1,r1,#16             ;149
000020  4388              BICS     r0,r0,r1              ;149
000022  0411              LSLS     r1,r2,#16             ;149
000024  4308              ORRS     r0,r0,r1              ;149
000026  6358              STR      r0,[r3,#0x34]         ;149
000028  bd10              POP      {r4,pc}
;;;151    
                          ENDP

00002a  0000              DCW      0x0000
                  |L9.44|
                          DCD      0x400e0040

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\adc.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_adc_c_ADC_Open____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_adc_c_ADC_Open____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_adc_c_ADC_Open____REVSH|
#line 132
|__asm___5_adc_c_ADC_Open____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
