; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\clk.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\clk.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\Device\Nuvoton\Nano1X2Series\Include -I..\..\..\..\Library\StdDriver\inc -I..\..\..\..\Library\CMSIS\Include -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\clk.crf ..\..\..\..\Library\StdDriver\src\clk.c]
                          THUMB

                          AREA ||i.CLK_DisableCKO||, CODE, READONLY, ALIGN=1

                  CLK_DisableCKO PROC
;;;30       */
;;;31     void CLK_DisableCKO(void)
000000  b500              PUSH     {lr}
;;;32     {
;;;33         CLK_DisableCKO0();
000002  f7fffffe          BL       CLK_DisableCKO0
;;;34     }
000006  bd00              POP      {pc}
;;;35     /**
                          ENDP


                          AREA ||i.CLK_DisableCKO0||, CODE, READONLY, ALIGN=2

                  CLK_DisableCKO0 PROC
;;;38       */
;;;39     void CLK_DisableCKO0(void)
000000  4802              LDR      r0,|L2.12|
;;;40     {
;;;41         /* Disable CKO0 clock source */
;;;42         CLK->APBCLK &= (~CLK_APBCLK_FDIV0_EN_Msk);
000002  6881              LDR      r1,[r0,#8]
000004  2240              MOVS     r2,#0x40
000006  4391              BICS     r1,r1,r2
000008  6081              STR      r1,[r0,#8]
;;;43     }
00000a  4770              BX       lr
;;;44     
                          ENDP

                  |L2.12|
                          DCD      0x50000200

                          AREA ||i.CLK_DisableCKO1||, CODE, READONLY, ALIGN=2

                  CLK_DisableCKO1 PROC
;;;48       */
;;;49     void CLK_DisableCKO1(void)
000000  4802              LDR      r0,|L3.12|
;;;50     {
;;;51         /* Disable CKO clock source */
;;;52         CLK->APBCLK &= (~CLK_APBCLK_FDIV1_EN_Msk);
000002  6881              LDR      r1,[r0,#8]
000004  2280              MOVS     r2,#0x80
000006  4391              BICS     r1,r1,r2
000008  6081              STR      r1,[r0,#8]
;;;53     }
00000a  4770              BX       lr
;;;54     
                          ENDP

                  |L3.12|
                          DCD      0x50000200

                          AREA ||i.CLK_DisableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_DisableModuleClock PROC
;;;494      */
;;;495    void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
000000  0fc1              LSRS     r1,r0,#31
;;;496    {
;;;497        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4))  &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
000002  008a              LSLS     r2,r1,#2
000004  4904              LDR      r1,|L4.24|
000006  1851              ADDS     r1,r2,r1
000008  684a              LDR      r2,[r1,#4]
00000a  06c3              LSLS     r3,r0,#27
00000c  0edb              LSRS     r3,r3,#27
00000e  2001              MOVS     r0,#1
000010  4098              LSLS     r0,r0,r3
000012  4382              BICS     r2,r2,r0
000014  604a              STR      r2,[r1,#4]
;;;498    }
000016  4770              BX       lr
;;;499    
                          ENDP

                  |L4.24|
                          DCD      0x50000200

                          AREA ||i.CLK_DisablePLL||, CODE, READONLY, ALIGN=2

                  CLK_DisablePLL PROC
;;;554      */
;;;555    void CLK_DisablePLL(void)
000000  4802              LDR      r0,|L5.12|
;;;556    {
;;;557        CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
000002  6a41              LDR      r1,[r0,#0x24]
000004  01c2              LSLS     r2,r0,#7
000006  4311              ORRS     r1,r1,r2
000008  6241              STR      r1,[r0,#0x24]
;;;558    }
00000a  4770              BX       lr
;;;559    
                          ENDP

                  |L5.12|
                          DCD      0x50000200

                          AREA ||i.CLK_DisableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_DisableXtalRC PROC
;;;418      */
;;;419    void CLK_DisableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L6.12|
;;;420    {
;;;421        CLK->PWRCTL &= ~u32ClkMask;
000002  680a              LDR      r2,[r1,#0]
000004  4382              BICS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;422    }
000008  4770              BX       lr
;;;423    
                          ENDP

00000a  0000              DCW      0x0000
                  |L6.12|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableCKO||, CODE, READONLY, ALIGN=1

                  CLK_EnableCKO PROC
;;;72       */
;;;73     void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
000000  b500              PUSH     {lr}
;;;74     {
;;;75         CLK_EnableCKO0(u32ClkSrc, u32ClkDiv, u32ClkDivBy1En);
000002  f7fffffe          BL       CLK_EnableCKO0
;;;76     }
000006  bd00              POP      {pc}
;;;77     /**
                          ENDP


                          AREA ||i.CLK_EnableCKO0||, CODE, READONLY, ALIGN=2

                  CLK_EnableCKO0 PROC
;;;94       */
;;;95     void CLK_EnableCKO0(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
000000  b530              PUSH     {r4,r5,lr}
;;;96     {
;;;97         /* Select CKO clock source */
;;;98         CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV0_S_Msk)) | u32ClkSrc;
000002  4b08              LDR      r3,|L8.36|
000004  699c              LDR      r4,[r3,#0x18]
000006  250c              MOVS     r5,#0xc
000008  43ac              BICS     r4,r4,r5
00000a  4304              ORRS     r4,r4,r0
00000c  619c              STR      r4,[r3,#0x18]
;;;99     
;;;100        /* CKO = clock source / 2^(u32ClkDiv + 1) */
;;;101        CLK->FRQDIV0 = CLK_FRQDIV0_FDIV_EN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_FRQDIV0_DIV1_Pos;
00000e  0150              LSLS     r0,r2,#5
000010  4308              ORRS     r0,r0,r1
000012  2110              MOVS     r1,#0x10
000014  4308              ORRS     r0,r0,r1
000016  6298              STR      r0,[r3,#0x28]
;;;102    
;;;103        /* Enable CKO clock source */
;;;104        CLK->APBCLK |= CLK_APBCLK_FDIV0_EN_Msk;
000018  6898              LDR      r0,[r3,#8]
00001a  2140              MOVS     r1,#0x40
00001c  4308              ORRS     r0,r0,r1
00001e  6098              STR      r0,[r3,#8]
;;;105    }
000020  bd30              POP      {r4,r5,pc}
;;;106    
                          ENDP

000022  0000              DCW      0x0000
                  |L8.36|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableCKO1||, CODE, READONLY, ALIGN=2

                  CLK_EnableCKO1 PROC
;;;124      */
;;;125    void CLK_EnableCKO1(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
000000  b510              PUSH     {r4,lr}
;;;126    {
;;;127        /* Select CKO clock source */
;;;128        CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV1_S_Msk)) | u32ClkSrc;
000002  4b08              LDR      r3,|L9.36|
000004  699c              LDR      r4,[r3,#0x18]
000006  08a4              LSRS     r4,r4,#2
000008  00a4              LSLS     r4,r4,#2
00000a  4304              ORRS     r4,r4,r0
00000c  619c              STR      r4,[r3,#0x18]
;;;129    
;;;130        /* CKO = clock source / 2^(u32ClkDiv + 1) */
;;;131        CLK->FRQDIV1 = CLK_FRQDIV1_FDIV_EN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_FRQDIV1_DIV1_Pos;
00000e  0150              LSLS     r0,r2,#5
000010  4308              ORRS     r0,r0,r1
000012  2110              MOVS     r1,#0x10
000014  4308              ORRS     r0,r0,r1
000016  6398              STR      r0,[r3,#0x38]
;;;132    
;;;133        /* Enable CKO clock source */
;;;134        CLK->APBCLK |= CLK_APBCLK_FDIV1_EN_Msk;
000018  6898              LDR      r0,[r3,#8]
00001a  2180              MOVS     r1,#0x80
00001c  4308              ORRS     r0,r0,r1
00001e  6098              STR      r0,[r3,#8]
;;;135    }
000020  bd10              POP      {r4,pc}
;;;136    
                          ENDP

000022  0000              DCW      0x0000
                  |L9.36|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_EnableModuleClock PROC
;;;456      */
;;;457    void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
000000  0fc1              LSRS     r1,r0,#31
;;;458    {
;;;459        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4))  |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
000002  008a              LSLS     r2,r1,#2
000004  4904              LDR      r1,|L10.24|
000006  1851              ADDS     r1,r2,r1
000008  684a              LDR      r2,[r1,#4]
00000a  06c3              LSLS     r3,r0,#27
00000c  0edb              LSRS     r3,r3,#27
00000e  2001              MOVS     r0,#1
000010  4098              LSLS     r0,r0,r3
000012  4302              ORRS     r2,r2,r0
000014  604a              STR      r2,[r1,#4]
;;;460    }
000016  4770              BX       lr
;;;461    
                          ENDP

                  |L10.24|
                          DCD      0x50000200

                          AREA ||i.CLK_EnablePLL||, CODE, READONLY, ALIGN=2

                  CLK_EnablePLL PROC
;;;507      */
;;;508    uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
000000  b5f3              PUSH     {r0,r1,r4-r7,lr}
;;;509    {
;;;510        uint32_t u32PllCr,u32PLL_N,u32PLL_M,u32PLLReg;
;;;511        if ( u32PllFreq < FREQ_16MHZ)
000002  4822              LDR      r0,|L11.140|
000004  b081              SUB      sp,sp,#4              ;509
000006  460f              MOV      r7,r1                 ;509
000008  4281              CMP      r1,r0
00000a  d201              BCS      |L11.16|
;;;512            u32PllFreq=FREQ_16MHZ;
00000c  4607              MOV      r7,r0
00000e  e003              B        |L11.24|
                  |L11.16|
;;;513        else if(u32PllFreq > FREQ_32MHZ)
000010  491f              LDR      r1,|L11.144|
000012  428f              CMP      r7,r1
000014  d900              BLS      |L11.24|
;;;514            u32PllFreq=FREQ_32MHZ;
000016  460f              MOV      r7,r1
                  |L11.24|
;;;515    
;;;516        if(u32PllClkSrc == CLK_PLLCTL_PLL_SRC_HXT) {
;;;517            /* PLL source clock from HXT */
;;;518            CLK->PLLCTL &= ~CLK_PLLCTL_PLL_SRC_HIRC;
000018  2601              MOVS     r6,#1
00001a  9a01              LDR      r2,[sp,#4]            ;516
;;;519            u32PllCr = __HXT;
00001c  491d              LDR      r1,|L11.148|
00001e  0476              LSLS     r6,r6,#17             ;518
000020  4d1d              LDR      r5,|L11.152|
000022  2a00              CMP      r2,#0                 ;516
000024  d015              BEQ      |L11.82|
;;;520        } else {
;;;521            /* PLL source clock from HIRC */
;;;522            CLK->PLLCTL |= CLK_PLLCTL_PLL_SRC_HIRC;
000026  6a6a              LDR      r2,[r5,#0x24]
000028  4332              ORRS     r2,r2,r6
00002a  626a              STR      r2,[r5,#0x24]
;;;523            if(CLK->PWRCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
00002c  682a              LDR      r2,[r5,#0]
00002e  04d2              LSLS     r2,r2,#19
000030  d400              BMI      |L11.52|
                  |L11.50|
;;;524                u32PllCr =__HIRC16M;
;;;525            else
;;;526                u32PllCr =__HIRC12M;
000032  4608              MOV      r0,r1
                  |L11.52|
;;;527        }
;;;528    
;;;529    
;;;530        u32PLL_N=u32PllCr/1000000;
000034  4919              LDR      r1,|L11.156|
000036  f7fffffe          BL       __aeabi_uidivmod
00003a  4604              MOV      r4,r0
;;;531        u32PLL_M=u32PllFreq/1000000;
00003c  4917              LDR      r1,|L11.156|
00003e  4638              MOV      r0,r7
000040  f7fffffe          BL       __aeabi_uidivmod
                  |L11.68|
;;;532        while(1) {
;;;533            if(u32PLL_M<=32 && u32PLL_N<=16 ) break;
000044  2820              CMP      r0,#0x20
000046  d801              BHI      |L11.76|
000048  2c10              CMP      r4,#0x10
00004a  d906              BLS      |L11.90|
                  |L11.76|
;;;534            u32PLL_M >>=1;
00004c  0840              LSRS     r0,r0,#1
;;;535            u32PLL_N >>=1;
00004e  0864              LSRS     r4,r4,#1
000050  e7f8              B        |L11.68|
                  |L11.82|
000052  6a68              LDR      r0,[r5,#0x24]         ;518
000054  43b0              BICS     r0,r0,r6              ;518
000056  6268              STR      r0,[r5,#0x24]         ;518
000058  e7eb              B        |L11.50|
                  |L11.90|
;;;536        }
;;;537        u32PLLReg = (u32PLL_M<<CLK_PLLCTL_PLL_MLP_Pos) | ((u32PLL_N-1)<<CLK_PLLCTL_PLL_SRC_N_Pos);
00005a  0221              LSLS     r1,r4,#8
00005c  39ff              SUBS     r1,r1,#0xff
00005e  3901              SUBS     r1,#1
000060  4301              ORRS     r1,r1,r0
;;;538        CLK->PLLCTL = ( CLK->PLLCTL & ~(CLK_PLLCTL_PLL_MLP_Msk | CLK_PLLCTL_PLL_SRC_N_Msk ) )| u32PLLReg;
000062  6a68              LDR      r0,[r5,#0x24]
000064  4a0e              LDR      r2,|L11.160|
000066  4010              ANDS     r0,r0,r2
000068  4308              ORRS     r0,r0,r1
00006a  6268              STR      r0,[r5,#0x24]
;;;539    
;;;540        if(u32PllClkSrc==CLK_PLLCTL_PLL_SRC_HIRC)
00006c  9801              LDR      r0,[sp,#4]
00006e  42b0              CMP      r0,r6
;;;541            CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC) | (CLK_PLLCTL_PLL_SRC_HIRC);
;;;542        else
;;;543            CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC);
000070  6a68              LDR      r0,[r5,#0x24]
000072  d101              BNE      |L11.120|
000074  4330              ORRS     r0,r0,r6              ;541
000076  e000              B        |L11.122|
                  |L11.120|
000078  43b0              BICS     r0,r0,r6
                  |L11.122|
00007a  6268              STR      r0,[r5,#0x24]
;;;544    
;;;545        CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
00007c  6a68              LDR      r0,[r5,#0x24]
00007e  2101              MOVS     r1,#1
000080  0409              LSLS     r1,r1,#16
000082  4388              BICS     r0,r0,r1
000084  6268              STR      r0,[r5,#0x24]
;;;546    
;;;547        return CLK_GetPLLClockFreq();
000086  f7fffffe          BL       CLK_GetPLLClockFreq
;;;548    }
00008a  bdfe              POP      {r1-r7,pc}
;;;549    
                          ENDP

                  |L11.140|
                          DCD      0x00f42400
                  |L11.144|
                          DCD      0x01e84800
                  |L11.148|
                          DCD      0x00b71b00
                  |L11.152|
                          DCD      0x50000200
                  |L11.156|
                          DCD      0x000f4240
                  |L11.160|
                          DCD      0xfffff0c0

                          AREA ||i.CLK_EnableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_EnableXtalRC PROC
;;;404      */
;;;405    void CLK_EnableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L12.12|
;;;406    {
;;;407        CLK->PWRCTL |= u32ClkMask;
000002  680a              LDR      r2,[r1,#0]
000004  4302              ORRS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;408    }
000008  4770              BX       lr
;;;409    
                          ENDP

00000a  0000              DCW      0x0000
                  |L12.12|
                          DCD      0x50000200

                          AREA ||i.CLK_GetCPUFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetCPUFreq PROC
;;;215      */
;;;216    uint32_t CLK_GetCPUFreq(void)
000000  b510              PUSH     {r4,lr}
;;;217    {
;;;218        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;219        return SystemCoreClock;
000006  4801              LDR      r0,|L13.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;220    }
00000a  bd10              POP      {r4,pc}
;;;221    
                          ENDP

                  |L13.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHCLKFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHCLKFreq PROC
;;;190      */
;;;191    uint32_t CLK_GetHCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;192    {
;;;193        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;194        return SystemCoreClock;
000006  4801              LDR      r0,|L14.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;195    }
00000a  bd10              POP      {r4,pc}
;;;196    
                          ENDP

                  |L14.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHXTFreq PROC
;;;164      */
;;;165    uint32_t CLK_GetHXTFreq(void)
000000  4802              LDR      r0,|L15.12|
;;;166    {
;;;167        if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN )
000002  6800              LDR      r0,[r0,#0]
000004  07c0              LSLS     r0,r0,#31
000006  d000              BEQ      |L15.10|
;;;168            return __HXT;
000008  4801              LDR      r0,|L15.16|
                  |L15.10|
;;;169        else
;;;170            return 0;
;;;171    }
00000a  4770              BX       lr
;;;172    
                          ENDP

                  |L15.12|
                          DCD      0x50000200
                  |L15.16|
                          DCD      0x00b71b00

                          AREA ||i.CLK_GetLXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetLXTFreq PROC
;;;177      */
;;;178    uint32_t CLK_GetLXTFreq(void)
000000  4804              LDR      r0,|L16.20|
;;;179    {
;;;180        if(CLK->PWRCTL & CLK_PWRCTL_LXT_EN )
000002  6800              LDR      r0,[r0,#0]
000004  0780              LSLS     r0,r0,#30
000006  d502              BPL      |L16.14|
;;;181            return __LXT;
000008  2001              MOVS     r0,#1
00000a  03c0              LSLS     r0,r0,#15
;;;182        else
;;;183            return 0;
;;;184    }
00000c  4770              BX       lr
                  |L16.14|
00000e  2000              MOVS     r0,#0                 ;183
000010  4770              BX       lr
;;;185    
                          ENDP

000012  0000              DCW      0x0000
                  |L16.20|
                          DCD      0x50000200

                          AREA ||i.CLK_GetPCLKFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetPCLKFreq PROC
;;;201      */
;;;202    uint32_t CLK_GetPCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;203    {
000002  b088              SUB      sp,sp,#0x20
;;;204        uint32_t Div[]= {1,2,4,8,16,1,1,1};
000004  2220              MOVS     r2,#0x20
000006  4909              LDR      r1,|L17.44|
000008  4668              MOV      r0,sp
00000a  f7fffffe          BL       __aeabi_memcpy4
;;;205        uint32_t PCLK_Div;
;;;206        PCLK_Div = CLK->APB_DIV & CLK_APB_DIV_APBDIV_Msk;
00000e  4808              LDR      r0,|L17.48|
000010  6b40              LDR      r0,[r0,#0x34]
000012  0744              LSLS     r4,r0,#29
000014  0f64              LSRS     r4,r4,#29
;;;207        SystemCoreClockUpdate();
000016  f7fffffe          BL       SystemCoreClockUpdate
;;;208        return SystemCoreClock/Div[PCLK_Div];
00001a  00a0              LSLS     r0,r4,#2
00001c  4669              MOV      r1,sp
00001e  5809              LDR      r1,[r1,r0]
000020  4804              LDR      r0,|L17.52|
000022  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
000024  f7fffffe          BL       __aeabi_uidivmod
;;;209    }
000028  b008              ADD      sp,sp,#0x20
00002a  bd10              POP      {r4,pc}
;;;210    
                          ENDP

                  |L17.44|
                          DCD      ||.constdata||
                  |L17.48|
                          DCD      0x50000200
                  |L17.52|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetPLLClockFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetPLLClockFreq PROC
;;;226      */
;;;227    uint32_t CLK_GetPLLClockFreq(void)
000000  b510              PUSH     {r4,lr}
;;;228    {
;;;229        uint32_t u32Freq =0, u32PLLSrc;
;;;230        uint32_t u32SRC_N,u32PLL_M,u32PllReg;
;;;231    
;;;232        u32PllReg = CLK->PLLCTL;
000002  490b              LDR      r1,|L18.48|
000004  6a4a              LDR      r2,[r1,#0x24]
;;;233    
;;;234        if (u32PllReg & CLK_PLLCTL_PD)
000006  03d0              LSLS     r0,r2,#15
000008  d501              BPL      |L18.14|
;;;235            return 0;    /* PLL is in power down mode */
00000a  2000              MOVS     r0,#0
;;;236    
;;;237        if (u32PllReg & CLK_PLLCTL_PLL_SRC_HIRC) {
;;;238            if(CLK->PLLCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
;;;239                u32PLLSrc =__HIRC16M;
;;;240            else
;;;241                u32PLLSrc =__HIRC12M;
;;;242        } else
;;;243            u32PLLSrc = __HXT;
;;;244    
;;;245        u32SRC_N = (u32PllReg & CLK_PLLCTL_PLL_SRC_N_Msk) >> CLK_PLLCTL_PLL_SRC_N_Pos;
;;;246        u32PLL_M = (u32PllReg & CLK_PLLCTL_PLL_MLP_Msk) >> CLK_PLLCTL_PLL_MLP_Pos;
;;;247    
;;;248        u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
;;;249    
;;;250        return u32Freq;
;;;251    }
00000c  bd10              POP      {r4,pc}
                  |L18.14|
00000e  4809              LDR      r0,|L18.52|
000010  0393              LSLS     r3,r2,#14             ;237
000012  d503              BPL      |L18.28|
000014  6a49              LDR      r1,[r1,#0x24]         ;238
000016  04c9              LSLS     r1,r1,#19             ;238
000018  d500              BPL      |L18.28|
00001a  4807              LDR      r0,|L18.56|
                  |L18.28|
00001c  0511              LSLS     r1,r2,#20             ;245
00001e  0692              LSLS     r2,r2,#26             ;246
000020  0f09              LSRS     r1,r1,#28             ;245
000022  0e92              LSRS     r2,r2,#26             ;246
000024  4350              MULS     r0,r2,r0              ;248
000026  1c49              ADDS     r1,r1,#1              ;248
000028  f7fffffe          BL       __aeabi_uidivmod
00002c  bd10              POP      {r4,pc}
;;;252    
                          ENDP

00002e  0000              DCW      0x0000
                  |L18.48|
                          DCD      0x50000200
                  |L18.52|
                          DCD      0x00b71b00
                  |L18.56|
                          DCD      0x00f42400

                          AREA ||i.CLK_Idle||, CODE, READONLY, ALIGN=2

                  CLK_Idle PROC
;;;153      */
;;;154    void CLK_Idle(void)
000000  4803              LDR      r0,|L19.16|
;;;155    {
;;;156        CLK->PWRCTL |= (CLK_PWRCTL_PD_EN_Msk );
000002  6801              LDR      r1,[r0,#0]
000004  2240              MOVS     r2,#0x40
000006  4311              ORRS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;157        __WFI();
00000a  bf30              WFI      
;;;158    }
00000c  4770              BX       lr
;;;159    
                          ENDP

00000e  0000              DCW      0x0000
                  |L19.16|
                          DCD      0x50000200

                          AREA ||i.CLK_PowerDown||, CODE, READONLY, ALIGN=2

                  CLK_PowerDown PROC
;;;141      */
;;;142    void CLK_PowerDown(void)
000000  4904              LDR      r1,|L20.20|
;;;143    {
;;;144        SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
000002  2004              MOVS     r0,#4
000004  6108              STR      r0,[r1,#0x10]
;;;145        CLK->PWRCTL |= (CLK_PWRCTL_PD_EN_Msk | CLK_PWRCTL_WK_DLY_Msk );
000006  4804              LDR      r0,|L20.24|
000008  6801              LDR      r1,[r0,#0]
00000a  2250              MOVS     r2,#0x50
00000c  4311              ORRS     r1,r1,r2
00000e  6001              STR      r1,[r0,#0]
;;;146        __WFI();
000010  bf30              WFI      
;;;147    }
000012  4770              BX       lr
;;;148    
                          ENDP

                  |L20.20|
                          DCD      0xe000ed00
                  |L20.24|
                          DCD      0x50000200

                          AREA ||i.CLK_SetCoreClock||, CODE, READONLY, ALIGN=2

                  CLK_SetCoreClock PROC
;;;257      */
;;;258    uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
000000  b510              PUSH     {r4,lr}
;;;259    {
;;;260        if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN) {
000002  490a              LDR      r1,|L21.44|
000004  6809              LDR      r1,[r1,#0]
000006  07c9              LSLS     r1,r1,#31
;;;261            CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HXT,u32Hclk);
;;;262        } else {
;;;263            CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HIRC,u32Hclk);
000008  4601              MOV      r1,r0
00000a  d001              BEQ      |L21.16|
00000c  2000              MOVS     r0,#0                 ;261
00000e  e001              B        |L21.20|
                  |L21.16|
000010  2001              MOVS     r0,#1
000012  0440              LSLS     r0,r0,#17
                  |L21.20|
000014  f7fffffe          BL       CLK_EnablePLL
;;;264        }
;;;265        CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
000018  2004              MOVS     r0,#4
00001a  f7fffffe          BL       CLK_WaitClockReady
;;;266        CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(1));
00001e  2100              MOVS     r1,#0
000020  2002              MOVS     r0,#2
000022  f7fffffe          BL       CLK_SetHCLK
;;;267        return SystemCoreClock;
000026  4802              LDR      r0,|L21.48|
000028  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;268    }
00002a  bd10              POP      {r4,pc}
;;;269    
                          ENDP

                  |L21.44|
                          DCD      0x50000200
                  |L21.48|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_SetHCLK||, CODE, READONLY, ALIGN=2

                  CLK_SetHCLK PROC
;;;281      */
;;;282    void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b510              PUSH     {r4,lr}
;;;283    {
;;;284        CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_N_Msk) | u32ClkDiv;
000002  4a07              LDR      r2,|L22.32|
000004  69d3              LDR      r3,[r2,#0x1c]
000006  091b              LSRS     r3,r3,#4
000008  011b              LSLS     r3,r3,#4
00000a  430b              ORRS     r3,r3,r1
00000c  61d3              STR      r3,[r2,#0x1c]
;;;285        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc;
00000e  6911              LDR      r1,[r2,#0x10]
000010  08c9              LSRS     r1,r1,#3
000012  00c9              LSLS     r1,r1,#3
000014  4301              ORRS     r1,r1,r0
000016  6111              STR      r1,[r2,#0x10]
;;;286        SystemCoreClockUpdate();
000018  f7fffffe          BL       SystemCoreClockUpdate
;;;287    }
00001c  bd10              POP      {r4,pc}
;;;288    
                          ENDP

00001e  0000              DCW      0x0000
                  |L22.32|
                          DCD      0x50000200

                          AREA ||i.CLK_SetModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_SetModuleClock PROC
;;;376    
;;;377    void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b570              PUSH     {r4-r6,lr}
;;;378    {
;;;379        uint32_t u32tmp=0,u32sel=0,u32div=0;
;;;380    
;;;381        if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
000002  0a84              LSRS     r4,r0,#10
000004  0623              LSLS     r3,r4,#24
000006  0e1b              LSRS     r3,r3,#24
000008  d00c              BEQ      |L23.36|
;;;382            u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4);
00000a  0303              LSLS     r3,r0,#12
00000c  0f9b              LSRS     r3,r3,#30
00000e  4d0f              LDR      r5,|L23.76|
000010  009b              LSLS     r3,r3,#2
000012  195b              ADDS     r3,r3,r5
;;;383            u32tmp = *(volatile uint32_t *)(u32div);
000014  681d              LDR      r5,[r3,#0]
;;;384            u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
000016  0586              LSLS     r6,r0,#22
000018  b2e4              UXTB     r4,r4
00001a  0ef6              LSRS     r6,r6,#27
00001c  40b4              LSLS     r4,r4,r6
00001e  43a5              BICS     r5,r5,r4
000020  4315              ORRS     r5,r5,r2
;;;385            *(volatile uint32_t *)(u32div) = u32tmp;
000022  601d              STR      r5,[r3,#0]
                  |L23.36|
;;;386        }
;;;387    
;;;388        if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
000024  0e42              LSRS     r2,r0,#25
000026  0712              LSLS     r2,r2,#28
000028  d00e              BEQ      |L23.72|
;;;389            u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
00002a  0042              LSLS     r2,r0,#1
00002c  4b07              LDR      r3,|L23.76|
00002e  0f92              LSRS     r2,r2,#30
000030  0092              LSLS     r2,r2,#2
000032  3b0c              SUBS     r3,r3,#0xc
000034  18d2              ADDS     r2,r2,r3
;;;390            u32tmp = *(volatile uint32_t *)(u32sel);
000036  6813              LDR      r3,[r2,#0]
;;;391            u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
000038  00c4              LSLS     r4,r0,#3
00003a  0f24              LSRS     r4,r4,#28
00003c  01c0              LSLS     r0,r0,#7
00003e  0ec0              LSRS     r0,r0,#27
000040  4084              LSLS     r4,r4,r0
000042  43a3              BICS     r3,r3,r4
000044  430b              ORRS     r3,r3,r1
;;;392            *(volatile uint32_t *)(u32sel) = u32tmp;
000046  6013              STR      r3,[r2,#0]
                  |L23.72|
;;;393        }
;;;394    }
000048  bd70              POP      {r4-r6,pc}
;;;395    
                          ENDP

00004a  0000              DCW      0x0000
                  |L23.76|
                          DCD      0x5000021c

                          AREA ||i.CLK_SysTickDelay||, CODE, READONLY, ALIGN=2

                  CLK_SysTickDelay PROC
;;;567      */
;;;568    void CLK_SysTickDelay(uint32_t us)
000000  4906              LDR      r1,|L24.28|
;;;569    {
;;;570        SysTick->LOAD = us * CyclesPerUs;
000002  6809              LDR      r1,[r1,#0]  ; CyclesPerUs
000004  4348              MULS     r0,r1,r0
000006  4906              LDR      r1,|L24.32|
000008  6148              STR      r0,[r1,#0x14]
;;;571        SysTick->VAL  =  (0x00);
00000a  2200              MOVS     r2,#0
00000c  618a              STR      r2,[r1,#0x18]
;;;572        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
00000e  2005              MOVS     r0,#5
000010  6108              STR      r0,[r1,#0x10]
                  |L24.18|
;;;573    
;;;574        /* Waiting for down-count to zero */
;;;575        while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
000012  6908              LDR      r0,[r1,#0x10]
000014  03c0              LSLS     r0,r0,#15
000016  d5fc              BPL      |L24.18|
;;;576        SysTick->CTRL = 0;
000018  610a              STR      r2,[r1,#0x10]
;;;577    }
00001a  4770              BX       lr
;;;578    
                          ENDP

                  |L24.28|
                          DCD      CyclesPerUs
                  |L24.32|
                          DCD      0xe000e000

                          AREA ||i.CLK_WaitClockReady||, CODE, READONLY, ALIGN=2

                  CLK_WaitClockReady PROC
;;;592      */
;;;593    uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
000000  b510              PUSH     {r4,lr}
;;;594    {
000002  4604              MOV      r4,r0
;;;595        int32_t i32TimeOutCnt=2160000;    
000004  4907              LDR      r1,|L25.36|
;;;596    
;;;597        while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask) {
000006  4a08              LDR      r2,|L25.40|
;;;598            if(i32TimeOutCnt-- <= 0)
;;;599                return 0;
000008  e005              B        |L25.22|
                  |L25.10|
00000a  460b              MOV      r3,r1                 ;598
00000c  1e49              SUBS     r1,r1,#1              ;598
00000e  2b00              CMP      r3,#0                 ;598
000010  dc01              BGT      |L25.22|
000012  2000              MOVS     r0,#0
;;;600        }
;;;601        return 1;
;;;602    }
000014  bd10              POP      {r4,pc}
                  |L25.22|
000016  68d3              LDR      r3,[r2,#0xc]          ;597
000018  4620              MOV      r0,r4                 ;597
00001a  4398              BICS     r0,r0,r3              ;597
00001c  d1f5              BNE      |L25.10|
00001e  2001              MOVS     r0,#1                 ;601
000020  bd10              POP      {r4,pc}
;;;603    
                          ENDP

000022  0000              DCW      0x0000
                  |L25.36|
                          DCD      0x0020f580
                  |L25.40|
                          DCD      0x50000200

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00000001
                          DCD      0x00000002
                          DCD      0x00000004
                          DCD      0x00000008
                          DCD      0x00000010
                          DCD      0x00000001
                          DCD      0x00000001
                          DCD      0x00000001

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\clk.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_clk_c_9b5832dc____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REVSH|
#line 132
|__asm___5_clk_c_9b5832dc____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
