; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\pwm.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\pwm.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\Device\Nuvoton\Nano1X2Series\Include -I..\..\..\..\Library\StdDriver\inc -I..\..\..\..\Library\CMSIS\Include -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\pwm.crf ..\..\..\..\Library\StdDriver\src\pwm.c]
                          THUMB

                          AREA ||i.PWM_ClearADCTriggerFlag||, CODE, READONLY, ALIGN=1

                  PWM_ClearADCTriggerFlag PROC
;;;289     */
;;;290    void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
000000  3080              ADDS     r0,r0,#0x80
;;;291    {
;;;292        pwm->ADTRGSTS |= (PWM_ADTRGSTS_ADTRG0Flag_Msk << u32ChannelNum);
000002  68c2              LDR      r2,[r0,#0xc]
000004  2301              MOVS     r3,#1
000006  408b              LSLS     r3,r3,r1
000008  431a              ORRS     r2,r2,r3
00000a  60c2              STR      r2,[r0,#0xc]
;;;293    }
00000c  4770              BX       lr
;;;294    
                          ENDP


                          AREA ||i.PWM_ClearCaptureIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_ClearCaptureIntFlag PROC
;;;453     */
;;;454    void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
000000  00c9              LSLS     r1,r1,#3
;;;455    {
;;;456        // disable capture interrupt flag
;;;457        pwm->CAPINTSTS = (u32Edge + 1)  << (u32ChannelNum * 8);
000002  1c52              ADDS     r2,r2,#1
000004  408a              LSLS     r2,r2,r1
000006  65c2              STR      r2,[r0,#0x5c]
;;;458    }
000008  4770              BX       lr
;;;459    
                          ENDP


                          AREA ||i.PWM_ClearDutyIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_ClearDutyIntFlag PROC
;;;480     */
;;;481    void PWM_ClearDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  2201              MOVS     r2,#1
;;;482    {
;;;483        // write 1 clear
;;;484        pwm->INTSTS = (PWM_INTEN_TMIE0_Msk << u32ChannelNum);
000002  408a              LSLS     r2,r2,r1
000004  6102              STR      r2,[r0,#0x10]
;;;485    }
000006  4770              BX       lr
;;;486    
                          ENDP


                          AREA ||i.PWM_ClearPeriodIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_ClearPeriodIntFlag PROC
;;;530     */
;;;531    void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  2201              MOVS     r2,#1
;;;532    {
;;;533        // write 1 clear
;;;534        pwm->INTSTS = (PWM_INTSTS_TMINT0_Msk << u32ChannelNum);
000002  408a              LSLS     r2,r2,r1
000004  6102              STR      r2,[r0,#0x10]
;;;535    }
000006  4770              BX       lr
;;;536    
                          ENDP


                          AREA ||i.PWM_ConfigCaptureChannel||, CODE, READONLY, ALIGN=2

                  PWM_ConfigCaptureChannel PROC
;;;132     */
;;;133    uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
000000  b5ff              PUSH     {r0-r7,lr}
;;;134                                       uint32_t u32ChannelNum,
;;;135                                       uint32_t u32UnitTimeNsec,
;;;136                                       uint32_t u32CaptureEdge)
;;;137    {
000002  4605              MOV      r5,r0
;;;138        uint32_t i;
;;;139        uint32_t u32PWM_Clock = SystemCoreClock;
000004  4841              LDR      r0,|L5.268|
000006  b083              SUB      sp,sp,#0xc            ;137
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;140        uint8_t  u8Divider = 1, u8Prescale = 0xFF;
;;;141        uint16_t u16CNR = 0xFFFF;
00000a  9000              STR      r0,[sp,#0]
00000c  4840              LDR      r0,|L5.272|
;;;142    
;;;143        switch ((CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2))) {
00000e  4b41              LDR      r3,|L5.276|
000010  9001              STR      r0,[sp,#4]
000012  2401              MOVS     r4,#1                 ;140
000014  6958              LDR      r0,[r3,#0x14]
000016  460e              MOV      r6,r1                 ;137
000018  27ff              MOVS     r7,#0xff              ;140
00001a  2202              MOVS     r2,#2
00001c  4011              ANDS     r1,r1,r2
00001e  2230              MOVS     r2,#0x30
000020  408a              LSLS     r2,r2,r1
000022  4010              ANDS     r0,r0,r2
000024  1d09              ADDS     r1,r1,#4
000026  40c8              LSRS     r0,r0,r1
;;;144        case 0:
;;;145            u32PWM_Clock = __HXT;
000028  493b              LDR      r1,|L5.280|
00002a  d006              BEQ      |L5.58|
00002c  2801              CMP      r0,#1                 ;143
00002e  d006              BEQ      |L5.62|
000030  2802              CMP      r0,#2                 ;143
000032  d00c              BEQ      |L5.78|
000034  2803              CMP      r0,#3                 ;143
000036  d10a              BNE      |L5.78|
000038  e004              B        |L5.68|
                  |L5.58|
;;;146            break;
00003a  9100              STR      r1,[sp,#0]
00003c  e007              B        |L5.78|
                  |L5.62|
;;;147        case 1:
;;;148            u32PWM_Clock = __LXT;
00003e  2001              MOVS     r0,#1
000040  03c0              LSLS     r0,r0,#15
;;;149            break;
000042  e003              B        |L5.76|
                  |L5.68|
;;;150        case 2:
;;;151            u32PWM_Clock = SystemCoreClock;
;;;152            break;
;;;153        case 3:
;;;154            if (CLK->PWRCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
000044  6818              LDR      r0,[r3,#0]
000046  04c0              LSLS     r0,r0,#19
000048  d5f7              BPL      |L5.58|
;;;155                u32PWM_Clock = __HIRC16M;
00004a  4834              LDR      r0,|L5.284|
                  |L5.76|
00004c  9000              STR      r0,[sp,#0]            ;148
                  |L5.78|
;;;156            else
;;;157                u32PWM_Clock = __HIRC12M;
;;;158            break;
;;;159        }
;;;160    
;;;161        for(; u8Divider < 17; u8Divider <<= 1) {  // clk divider could only be 1, 2, 4, 8, 16
;;;162            i = ((u32PWM_Clock / u8Divider) * u32UnitTimeNsec) / 1000000000;
00004e  4621              MOV      r1,r4
000050  9800              LDR      r0,[sp,#0]
000052  f7fffffe          BL       __aeabi_uidivmod
000056  9905              LDR      r1,[sp,#0x14]
000058  4348              MULS     r0,r1,r0
00005a  4931              LDR      r1,|L5.288|
00005c  f7fffffe          BL       __aeabi_uidivmod
;;;163    
;;;164            // If target value is larger than 0xFF, need to use a larger divider
;;;165            if(i > (0xFF))
000060  28ff              CMP      r0,#0xff
000062  d804              BHI      |L5.110|
;;;166                continue;
;;;167    
;;;168            u8Prescale = i;
000064  b2c7              UXTB     r7,r0
;;;169    
;;;170            // u8Prescale must at least be 2, otherwise the output stop
;;;171            if(u8Prescale < 3)
000066  2f03              CMP      r7,#3
000068  d205              BCS      |L5.118|
;;;172                u8Prescale = 2;
00006a  2702              MOVS     r7,#2
00006c  e003              B        |L5.118|
                  |L5.110|
00006e  0660              LSLS     r0,r4,#25             ;161
000070  0e04              LSRS     r4,r0,#24             ;161
000072  2c11              CMP      r4,#0x11              ;161
000074  d3eb              BCC      |L5.78|
                  |L5.118|
;;;173    
;;;174            break;
;;;175        }
;;;176    
;;;177        // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
;;;178        i = (u8Prescale * u8Divider) * 1000000000/ u32PWM_Clock;
000076  4638              MOV      r0,r7
000078  4929              LDR      r1,|L5.288|
00007a  4360              MULS     r0,r4,r0
00007c  4348              MULS     r0,r1,r0
00007e  9900              LDR      r1,[sp,#0]
000080  f7fffffe          BL       __aeabi_uidivmod
000084  4684              MOV      r12,r0
;;;179    
;;;180        u8Prescale -= 1;
;;;181        u16CNR -= 1;
000086  9801              LDR      r0,[sp,#4]
000088  1e7f              SUBS     r7,r7,#1              ;180
00008a  1e40              SUBS     r0,r0,#1
00008c  b2fa              UXTB     r2,r7                 ;180
00008e  b287              UXTH     r7,r0
;;;182        // convert to real register value
;;;183        if(u8Divider == 1)
000090  2c01              CMP      r4,#1
000092  d033              BEQ      |L5.252|
;;;184            u8Divider = 4;
;;;185        else if (u8Divider == 2)
000094  2c02              CMP      r4,#2
000096  d033              BEQ      |L5.256|
;;;186            u8Divider = 0;
;;;187        else if (u8Divider == 4)
000098  2c04              CMP      r4,#4
00009a  d033              BEQ      |L5.260|
;;;188            u8Divider = 1;
;;;189        else if (u8Divider == 8)
00009c  2c08              CMP      r4,#8
00009e  d033              BEQ      |L5.264|
;;;190            u8Divider = 2;
;;;191        else // 16
;;;192            u8Divider = 3;
0000a0  2003              MOVS     r0,#3
                  |L5.162|
;;;193    
;;;194        // every two channels share a prescaler
;;;195        while((pwm->INTSTS & PWM_INTSTS_PresSyncFlag_Msk ) == PWM_INTSTS_PresSyncFlag_Msk);
0000a2  6929              LDR      r1,[r5,#0x10]
0000a4  05c9              LSLS     r1,r1,#23
0000a6  d4fc              BMI      |L5.162|
;;;196        pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
0000a8  682b              LDR      r3,[r5,#0]
0000aa  0871              LSRS     r1,r6,#1
0000ac  00c9              LSLS     r1,r1,#3
0000ae  24ff              MOVS     r4,#0xff
0000b0  408c              LSLS     r4,r4,r1
0000b2  43a3              BICS     r3,r3,r4
0000b4  408a              LSLS     r2,r2,r1
0000b6  4313              ORRS     r3,r3,r2
0000b8  602b              STR      r3,[r5,#0]
;;;197        pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
0000ba  686a              LDR      r2,[r5,#4]
0000bc  00b1              LSLS     r1,r6,#2
0000be  2307              MOVS     r3,#7
0000c0  408b              LSLS     r3,r3,r1
0000c2  439a              BICS     r2,r2,r3
0000c4  4088              LSLS     r0,r0,r1
0000c6  4302              ORRS     r2,r2,r0
0000c8  606a              STR      r2,[r5,#4]
;;;198        pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
0000ca  68a8              LDR      r0,[r5,#8]
0000cc  00f2              LSLS     r2,r6,#3
0000ce  2108              MOVS     r1,#8
0000d0  4091              LSLS     r1,r1,r2
0000d2  4308              ORRS     r0,r0,r1
0000d4  60a8              STR      r0,[r5,#8]
;;;199        while((pwm->INTSTS & (PWM_INTSTS_Duty0Syncflag_Msk << u32ChannelNum)) == (PWM_INTSTS_Duty0Syncflag_Msk << u32ChannelNum));
0000d6  2210              MOVS     r2,#0x10
0000d8  40b2              LSLS     r2,r2,r6
                  |L5.218|
0000da  6929              LDR      r1,[r5,#0x10]
0000dc  4610              MOV      r0,r2
0000de  4388              BICS     r0,r0,r1
0000e0  d0fb              BEQ      |L5.218|
;;;200        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY0_CN_Msk;
0000e2  200c              MOVS     r0,#0xc
0000e4  4346              MULS     r6,r0,r6
0000e6  1970              ADDS     r0,r6,r5
0000e8  69c1              LDR      r1,[r0,#0x1c]
0000ea  0c09              LSRS     r1,r1,#16
0000ec  0409              LSLS     r1,r1,#16
0000ee  61c1              STR      r1,[r0,#0x1c]
;;;201        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
0000f0  69c1              LDR      r1,[r0,#0x1c]
0000f2  4339              ORRS     r1,r1,r7
0000f4  61c1              STR      r1,[r0,#0x1c]
;;;202    
;;;203        return(i);
0000f6  4660              MOV      r0,r12
;;;204    }
0000f8  b007              ADD      sp,sp,#0x1c
0000fa  bdf0              POP      {r4-r7,pc}
                  |L5.252|
0000fc  2004              MOVS     r0,#4                 ;184
0000fe  e7d0              B        |L5.162|
                  |L5.256|
000100  2000              MOVS     r0,#0                 ;186
000102  e7ce              B        |L5.162|
                  |L5.260|
000104  2001              MOVS     r0,#1                 ;188
000106  e7cc              B        |L5.162|
                  |L5.264|
000108  2002              MOVS     r0,#2                 ;190
00010a  e7ca              B        |L5.162|
;;;205    
                          ENDP

                  |L5.268|
                          DCD      SystemCoreClock
                  |L5.272|
                          DCD      0x0000ffff
                  |L5.276|
                          DCD      0x50000200
                  |L5.280|
                          DCD      0x00b71b00
                  |L5.284|
                          DCD      0x00f42400
                  |L5.288|
                          DCD      0x3b9aca00

                          AREA ||i.PWM_ConfigOutputChannel||, CODE, READONLY, ALIGN=2

                  PWM_ConfigOutputChannel PROC
;;;35      */
;;;36     uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
000000  b5ff              PUSH     {r0-r7,lr}
;;;37                                       uint32_t u32ChannelNum,
;;;38                                       uint32_t u32Frequency,
;;;39                                       uint32_t u32DutyCycle)
;;;40     {
000002  4605              MOV      r5,r0
;;;41         uint32_t i;
;;;42         uint32_t u32PWM_Clock = SystemCoreClock;
000004  4854              LDR      r0,|L6.344|
000006  b083              SUB      sp,sp,#0xc            ;40
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00000a  4694              MOV      r12,r2                ;40
;;;43         uint8_t  u8Divider = 1, u8Prescale = 0xFF;
;;;44         uint16_t u16CNR = 0xFFFF;
00000c  9000              STR      r0,[sp,#0]
00000e  4853              LDR      r0,|L6.348|
;;;45     
;;;46         switch ((CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2))) {
000010  4a53              LDR      r2,|L6.352|
000012  460e              MOV      r6,r1                 ;40
000014  9001              STR      r0,[sp,#4]
000016  2401              MOVS     r4,#1                 ;43
000018  6951              LDR      r1,[r2,#0x14]
00001a  27ff              MOVS     r7,#0xff              ;43
00001c  4630              MOV      r0,r6
00001e  2302              MOVS     r3,#2
000020  4018              ANDS     r0,r0,r3
000022  2330              MOVS     r3,#0x30
000024  4083              LSLS     r3,r3,r0
000026  4019              ANDS     r1,r1,r3
000028  1d00              ADDS     r0,r0,#4
00002a  40c1              LSRS     r1,r1,r0
;;;47         case 0:
;;;48             u32PWM_Clock = __HXT;
00002c  484d              LDR      r0,|L6.356|
00002e  d00d              BEQ      |L6.76|
000030  2901              CMP      r1,#1                 ;46
000032  d004              BEQ      |L6.62|
000034  2902              CMP      r1,#2                 ;46
000036  d00a              BEQ      |L6.78|
000038  2903              CMP      r1,#3                 ;46
00003a  d108              BNE      |L6.78|
00003c  e002              B        |L6.68|
                  |L6.62|
;;;49             break;
;;;50         case 1:
;;;51             u32PWM_Clock = __LXT;
00003e  2001              MOVS     r0,#1
000040  03c0              LSLS     r0,r0,#15
;;;52             break;
000042  e003              B        |L6.76|
                  |L6.68|
;;;53         case 2:
;;;54             u32PWM_Clock = SystemCoreClock;
;;;55             break;
;;;56         case 3:
;;;57             if (CLK->PWRCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
000044  6811              LDR      r1,[r2,#0]
000046  04c9              LSLS     r1,r1,#19
000048  d500              BPL      |L6.76|
;;;58                 u32PWM_Clock = __HIRC16M;
00004a  4847              LDR      r0,|L6.360|
                  |L6.76|
;;;59             else
;;;60                 u32PWM_Clock = __HIRC12M;
00004c  9000              STR      r0,[sp,#0]
                  |L6.78|
00004e  4661              MOV      r1,r12                ;40
;;;61             break;
;;;62         }
;;;63     
;;;64         for(; u8Divider < 17; u8Divider <<= 1) {  // clk divider could only be 1, 2, 4, 8, 16
;;;65             i = (u32PWM_Clock / u32Frequency) / u8Divider;
000050  9800              LDR      r0,[sp,#0]
000052  f7fffffe          BL       __aeabi_uidivmod
000056  9002              STR      r0,[sp,#8]
                  |L6.88|
000058  4621              MOV      r1,r4
00005a  f7fffffe          BL       __aeabi_uidivmod
;;;66             // If target value is larger than CNR * prescale, need to use a larger divider
;;;67             if(i > (0x10000 * 0x100))
00005e  2101              MOVS     r1,#1
000060  0609              LSLS     r1,r1,#24
000062  4288              CMP      r0,r1
000064  d812              BHI      |L6.140|
;;;68                 continue;
;;;69     
;;;70             // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
;;;71             u8Prescale = (i + 0xFFFF)/ 0x10000;
000066  493d              LDR      r1,|L6.348|
000068  1841              ADDS     r1,r0,r1
00006a  0209              LSLS     r1,r1,#8
00006c  0e0f              LSRS     r7,r1,#24
;;;72     
;;;73             // u8Prescale must at least be 2, otherwise the output stop
;;;74             if(u8Prescale < 3)
00006e  2f03              CMP      r7,#3
000070  d200              BCS      |L6.116|
;;;75                 u8Prescale = 2;
000072  2702              MOVS     r7,#2
                  |L6.116|
;;;76     
;;;77             i /= u8Prescale;
000074  4639              MOV      r1,r7
000076  f7fffffe          BL       __aeabi_uidivmod
;;;78     
;;;79             if(i <= 0x10000) {
00007a  2101              MOVS     r1,#1
00007c  0409              LSLS     r1,r1,#16
00007e  4288              CMP      r0,r1
000080  d804              BHI      |L6.140|
;;;80                 if(i == 1)
000082  2801              CMP      r0,#1
000084  d000              BEQ      |L6.136|
;;;81                     u16CNR = 1;     // Too fast, and PWM cannot generate expected frequency...
;;;82                 else
;;;83                     u16CNR = i;
000086  b280              UXTH     r0,r0
                  |L6.136|
000088  9001              STR      r0,[sp,#4]            ;81
00008a  e005              B        |L6.152|
                  |L6.140|
00008c  0660              LSLS     r0,r4,#25             ;64
00008e  0e04              LSRS     r4,r0,#24             ;64
000090  2c11              CMP      r4,#0x11              ;64
000092  d201              BCS      |L6.152|
000094  9802              LDR      r0,[sp,#8]            ;64
000096  e7df              B        |L6.88|
                  |L6.152|
;;;84                 break;
;;;85             }
;;;86     
;;;87         }
;;;88         // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
;;;89         i = u32PWM_Clock / (u8Prescale * u8Divider * u16CNR);
000098  4639              MOV      r1,r7
00009a  9801              LDR      r0,[sp,#4]
00009c  4361              MULS     r1,r4,r1
00009e  4341              MULS     r1,r0,r1
0000a0  9800              LDR      r0,[sp,#0]
0000a2  f7fffffe          BL       __aeabi_uidivmod
;;;90     
;;;91         u8Prescale -= 1;
;;;92         u16CNR -= 1;
0000a6  9000              STR      r0,[sp,#0]
0000a8  9801              LDR      r0,[sp,#4]
0000aa  1e7f              SUBS     r7,r7,#1              ;91
0000ac  1e40              SUBS     r0,r0,#1
0000ae  b2fa              UXTB     r2,r7                 ;91
0000b0  b287              UXTH     r7,r0
;;;93         // convert to real register value
;;;94         if(u8Divider == 1)
0000b2  2c01              CMP      r4,#1
0000b4  d046              BEQ      |L6.324|
;;;95             u8Divider = 4;
;;;96         else if (u8Divider == 2)
0000b6  2c02              CMP      r4,#2
0000b8  d046              BEQ      |L6.328|
;;;97             u8Divider = 0;
;;;98         else if (u8Divider == 4)
0000ba  2c04              CMP      r4,#4
0000bc  d046              BEQ      |L6.332|
;;;99             u8Divider = 1;
;;;100        else if (u8Divider == 8)
0000be  2c08              CMP      r4,#8
0000c0  d046              BEQ      |L6.336|
;;;101            u8Divider = 2;
;;;102        else // 16
;;;103            u8Divider = 3;
0000c2  2003              MOVS     r0,#3
                  |L6.196|
;;;104    
;;;105        // every two channels share a prescaler
;;;106        while((pwm->INTSTS & PWM_INTSTS_PresSyncFlag_Msk ) == PWM_INTSTS_PresSyncFlag_Msk);
0000c4  6929              LDR      r1,[r5,#0x10]
0000c6  05c9              LSLS     r1,r1,#23
0000c8  d4fc              BMI      |L6.196|
;;;107        pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
0000ca  682b              LDR      r3,[r5,#0]
0000cc  0871              LSRS     r1,r6,#1
0000ce  00c9              LSLS     r1,r1,#3
0000d0  24ff              MOVS     r4,#0xff
0000d2  408c              LSLS     r4,r4,r1
0000d4  43a3              BICS     r3,r3,r4
0000d6  408a              LSLS     r2,r2,r1
0000d8  4313              ORRS     r3,r3,r2
0000da  602b              STR      r3,[r5,#0]
;;;108        pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
0000dc  686a              LDR      r2,[r5,#4]
0000de  00b1              LSLS     r1,r6,#2
0000e0  2307              MOVS     r3,#7
0000e2  408b              LSLS     r3,r3,r1
0000e4  439a              BICS     r2,r2,r3
0000e6  4088              LSLS     r0,r0,r1
0000e8  4302              ORRS     r2,r2,r0
0000ea  606a              STR      r2,[r5,#4]
;;;109        pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
0000ec  68a8              LDR      r0,[r5,#8]
0000ee  00f2              LSLS     r2,r6,#3
0000f0  2108              MOVS     r1,#8
0000f2  4091              LSLS     r1,r1,r2
0000f4  4308              ORRS     r0,r0,r1
0000f6  60a8              STR      r0,[r5,#8]
;;;110        while((pwm->INTSTS & (PWM_INTSTS_Duty0Syncflag_Msk << u32ChannelNum)) == (PWM_INTSTS_Duty0Syncflag_Msk << u32ChannelNum));
0000f8  2210              MOVS     r2,#0x10
0000fa  40b2              LSLS     r2,r2,r6
                  |L6.252|
0000fc  6929              LDR      r1,[r5,#0x10]
0000fe  4610              MOV      r0,r2
000100  4388              BICS     r0,r0,r1
000102  d0fb              BEQ      |L6.252|
;;;111        if(u32DutyCycle == 0)
;;;112            *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY0_CM_Msk;
000104  210c              MOVS     r1,#0xc
000106  434e              MULS     r6,r1,r6
000108  9806              LDR      r0,[sp,#0x18]         ;111
00010a  1974              ADDS     r4,r6,r5
00010c  2800              CMP      r0,#0                 ;111
;;;113        else {
;;;114            *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY0_CM_Msk;
00010e  69e0              LDR      r0,[r4,#0x1c]
000110  d020              BEQ      |L6.340|
000112  b280              UXTH     r0,r0
000114  61e0              STR      r0,[r4,#0x1c]
;;;115            *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 100 - 1) << PWM_DUTY0_CM_Pos);
000116  9806              LDR      r0,[sp,#0x18]
000118  1c79              ADDS     r1,r7,#1
00011a  4348              MULS     r0,r1,r0
00011c  2164              MOVS     r1,#0x64
00011e  f7fffffe          BL       __aeabi_uidivmod
000122  0401              LSLS     r1,r0,#16
000124  2001              MOVS     r0,#1
000126  0400              LSLS     r0,r0,#16
000128  1a08              SUBS     r0,r1,r0
00012a  69e1              LDR      r1,[r4,#0x1c]
00012c  4308              ORRS     r0,r0,r1
                  |L6.302|
00012e  61e0              STR      r0,[r4,#0x1c]
;;;116        }
;;;117        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY0_CN_Msk;
000130  69e0              LDR      r0,[r4,#0x1c]
000132  0c00              LSRS     r0,r0,#16
000134  0400              LSLS     r0,r0,#16
000136  61e0              STR      r0,[r4,#0x1c]
;;;118        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
000138  69e0              LDR      r0,[r4,#0x1c]
00013a  4338              ORRS     r0,r0,r7
00013c  61e0              STR      r0,[r4,#0x1c]
;;;119    
;;;120        return(i);
00013e  9800              LDR      r0,[sp,#0]
;;;121    }
000140  b007              ADD      sp,sp,#0x1c
000142  bdf0              POP      {r4-r7,pc}
                  |L6.324|
000144  2004              MOVS     r0,#4                 ;95
000146  e7bd              B        |L6.196|
                  |L6.328|
000148  2000              MOVS     r0,#0                 ;97
00014a  e7bb              B        |L6.196|
                  |L6.332|
00014c  2001              MOVS     r0,#1                 ;99
00014e  e7b9              B        |L6.196|
                  |L6.336|
000150  2002              MOVS     r0,#2                 ;101
000152  e7b7              B        |L6.196|
                  |L6.340|
000154  b280              UXTH     r0,r0                 ;112
000156  e7ea              B        |L6.302|
;;;122    
                          ENDP

                  |L6.344|
                          DCD      SystemCoreClock
                  |L6.348|
                          DCD      0x0000ffff
                  |L6.352|
                          DCD      0x50000200
                  |L6.356|
                          DCD      0x00b71b00
                  |L6.360|
                          DCD      0x00f42400

                          AREA ||i.PWM_DisableADCTrigger||, CODE, READONLY, ALIGN=1

                  PWM_DisableADCTrigger PROC
;;;277     */
;;;278    void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
000000  3080              ADDS     r0,r0,#0x80
;;;279    {
;;;280        pwm->ADTRGEN &= ~(PWM_ADTRGEN_TRGCH0EN_Msk << u32ChannelNum);
000002  6882              LDR      r2,[r0,#8]
000004  2301              MOVS     r3,#1
000006  408b              LSLS     r3,r3,r1
000008  439a              BICS     r2,r2,r3
00000a  6082              STR      r2,[r0,#8]
;;;281    }
00000c  4770              BX       lr
;;;282    
                          ENDP


                          AREA ||i.PWM_DisableCapture||, CODE, READONLY, ALIGN=1

                  PWM_DisableCapture PROC
;;;336     */
;;;337    void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b5f0              PUSH     {r4-r7,lr}
;;;338    {
;;;339        uint8_t i;
;;;340        uint32_t u32CTLMask = 0;
000002  2300              MOVS     r3,#0
;;;341        uint32_t u32CAPCTLMask = 0;
000004  461c              MOV      r4,r3
;;;342    
;;;343    
;;;344        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
000006  461a              MOV      r2,r3
;;;345            if ( u32ChannelMask  & (1 << i)) {
000008  2701              MOVS     r7,#1
                  |L8.10|
00000a  463d              MOV      r5,r7
00000c  4095              LSLS     r5,r5,r2
00000e  420d              TST      r5,r1
000010  d006              BEQ      |L8.32|
;;;346                u32CTLMask |= (PWM_CTL_CH0EN_Msk << (i * 8));
000012  00d5              LSLS     r5,r2,#3
000014  463e              MOV      r6,r7
000016  40ae              LSLS     r6,r6,r5
000018  4333              ORRS     r3,r3,r6
;;;347                u32CAPCTLMask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
00001a  2606              MOVS     r6,#6
00001c  40ae              LSLS     r6,r6,r5
00001e  4334              ORRS     r4,r4,r6
                  |L8.32|
000020  1c52              ADDS     r2,r2,#1              ;344
000022  b2d2              UXTB     r2,r2                 ;344
000024  2a04              CMP      r2,#4                 ;344
000026  d3f0              BCC      |L8.10|
;;;348            }
;;;349        }
;;;350    
;;;351        pwm->CTL &= ~u32CTLMask;
000028  6881              LDR      r1,[r0,#8]
00002a  4399              BICS     r1,r1,r3
00002c  6081              STR      r1,[r0,#8]
;;;352        pwm->CAPCTL &= ~u32CAPCTLMask;
00002e  6d41              LDR      r1,[r0,#0x54]
000030  43a1              BICS     r1,r1,r4
000032  6541              STR      r1,[r0,#0x54]
;;;353    
;;;354    }
000034  bdf0              POP      {r4-r7,pc}
;;;355    
                          ENDP


                          AREA ||i.PWM_DisableCaptureInt||, CODE, READONLY, ALIGN=1

                  PWM_DisableCaptureInt PROC
;;;437     */
;;;438    void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
000000  6d83              LDR      r3,[r0,#0x58]
;;;439    {
;;;440        // disable capture interrupt
;;;441        pwm->CAPINTEN &= ~(u32Edge << (u32ChannelNum * 8));
000002  00c9              LSLS     r1,r1,#3
000004  408a              LSLS     r2,r2,r1
000006  4393              BICS     r3,r3,r2
000008  6583              STR      r3,[r0,#0x58]
;;;442    }
00000a  4770              BX       lr
;;;443    
                          ENDP


                          AREA ||i.PWM_DisableDeadZone||, CODE, READONLY, ALIGN=1

                  PWM_DisableDeadZone PROC
;;;403     */
;;;404    void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6883              LDR      r3,[r0,#8]
;;;405    {
;;;406        // every two channels shares the same setting
;;;407        u32ChannelNum >>= 1;
000002  0849              LSRS     r1,r1,#1
;;;408        // enable dead zone
;;;409        pwm->CTL &= ~(PWM_CTL_DZEN01_Msk << u32ChannelNum);
000004  2210              MOVS     r2,#0x10
000006  408a              LSLS     r2,r2,r1
000008  4393              BICS     r3,r3,r2
00000a  6083              STR      r3,[r0,#8]
;;;410    }
00000c  4770              BX       lr
;;;411    
                          ENDP


                          AREA ||i.PWM_DisableOutput||, CODE, READONLY, ALIGN=1

                  PWM_DisableOutput PROC
;;;374     */
;;;375    void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
000000  6942              LDR      r2,[r0,#0x14]
;;;376    {
;;;377        pwm->OE &= ~u32ChannelMask;
000002  438a              BICS     r2,r2,r1
000004  6142              STR      r2,[r0,#0x14]
;;;378    }
000006  4770              BX       lr
;;;379    
                          ENDP


                          AREA ||i.PWM_DisablePDMA||, CODE, READONLY, ALIGN=1

                  PWM_DisablePDMA PROC
;;;576     */
;;;577    void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
000000  2900              CMP      r1,#0
;;;578    {
;;;579        if (u32ChannelNum == 0)
;;;580            pwm->CAPCTL &= ~PWM_CAPCTL_CH0PDMAEN_Msk;
;;;581        else
;;;582            pwm->CAPCTL &= ~PWM_CAPCTL_CH2PDMAEN_Msk;
000002  6d41              LDR      r1,[r0,#0x54]
000004  d004              BEQ      |L12.16|
000006  2201              MOVS     r2,#1
000008  04d2              LSLS     r2,r2,#19
                  |L12.10|
00000a  4391              BICS     r1,r1,r2              ;580
00000c  6541              STR      r1,[r0,#0x54]         ;580
;;;583    }
00000e  4770              BX       lr
                  |L12.16|
000010  2208              MOVS     r2,#8                 ;580
000012  e7fa              B        |L12.10|
;;;584    
                          ENDP


                          AREA ||i.PWM_DisablePeriodInt||, CODE, READONLY, ALIGN=1

                  PWM_DisablePeriodInt PROC
;;;519     */
;;;520    void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  68c2              LDR      r2,[r0,#0xc]
;;;521    {
;;;522        pwm->INTEN &= ~(PWM_INTEN_TMIE0_Msk << u32ChannelNum);
000002  2301              MOVS     r3,#1
000004  408b              LSLS     r3,r3,r1
000006  439a              BICS     r2,r2,r3
000008  60c2              STR      r2,[r0,#0xc]
;;;523    }
00000a  4770              BX       lr
;;;524    
                          ENDP


                          AREA ||i.PWM_EnableADCTrigger||, CODE, READONLY, ALIGN=1

                  PWM_EnableADCTrigger PROC
;;;266     */
;;;267    void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
000000  3080              ADDS     r0,r0,#0x80
;;;268    {
;;;269        pwm->ADTRGEN |= (PWM_ADTRGEN_TRGCH0EN_Msk << u32ChannelNum);
000002  6882              LDR      r2,[r0,#8]
000004  2301              MOVS     r3,#1
000006  408b              LSLS     r3,r3,r1
000008  431a              ORRS     r2,r2,r3
00000a  6082              STR      r2,[r0,#8]
;;;270    }
00000c  4770              BX       lr
;;;271    
                          ENDP


                          AREA ||i.PWM_EnableCapture||, CODE, READONLY, ALIGN=1

                  PWM_EnableCapture PROC
;;;315     */
;;;316    void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b5f0              PUSH     {r4-r7,lr}
;;;317    {
;;;318        uint8_t i;
;;;319        uint32_t u32Mask = 0;
000002  2300              MOVS     r3,#0
;;;320    
;;;321        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
;;;322            if ( u32ChannelMask  & (1 << i)) {
000004  2601              MOVS     r6,#1
000006  461a              MOV      r2,r3                 ;321
;;;323                u32Mask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
000008  2706              MOVS     r7,#6
                  |L15.10|
00000a  4635              MOV      r5,r6                 ;322
00000c  4095              LSLS     r5,r5,r2              ;322
00000e  420d              TST      r5,r1                 ;322
000010  d003              BEQ      |L15.26|
000012  00d5              LSLS     r5,r2,#3
000014  463c              MOV      r4,r7
000016  40ac              LSLS     r4,r4,r5
000018  4323              ORRS     r3,r3,r4
                  |L15.26|
00001a  1c52              ADDS     r2,r2,#1              ;321
00001c  b2d2              UXTB     r2,r2                 ;321
00001e  2a04              CMP      r2,#4                 ;321
000020  d3f3              BCC      |L15.10|
;;;324            }
;;;325        }
;;;326    
;;;327        pwm->CAPCTL |= u32Mask;
000022  6d41              LDR      r1,[r0,#0x54]
000024  4319              ORRS     r1,r1,r3
000026  6541              STR      r1,[r0,#0x54]
;;;328    }
000028  bdf0              POP      {r4-r7,pc}
;;;329    
                          ENDP


                          AREA ||i.PWM_EnableCaptureInt||, CODE, READONLY, ALIGN=1

                  PWM_EnableCaptureInt PROC
;;;421     */
;;;422    void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
000000  6d83              LDR      r3,[r0,#0x58]
;;;423    {
;;;424        // enable capture interrupt
;;;425        pwm->CAPINTEN |= (u32Edge << (u32ChannelNum * 8));
000002  00c9              LSLS     r1,r1,#3
000004  408a              LSLS     r2,r2,r1
000006  4313              ORRS     r3,r3,r2
000008  6583              STR      r3,[r0,#0x58]
;;;426    }
00000a  4770              BX       lr
;;;427    
                          ENDP


                          AREA ||i.PWM_EnableDeadZone||, CODE, READONLY, ALIGN=1

                  PWM_EnableDeadZone PROC
;;;387     */
;;;388    void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
000000  b530              PUSH     {r4,r5,lr}
;;;389    {
;;;390        // every two channels shares the same setting
;;;391        u32ChannelNum >>= 1;
;;;392        // set duration
;;;393        pwm->PRES = (pwm->PRES & ~(PWM_PRES_DZ01_Msk << (8 * u32ChannelNum))) | ((u32Duration << PWM_PRES_DZ01_Pos ) << (8 * u32ChannelNum));
000002  6804              LDR      r4,[r0,#0]
000004  0849              LSRS     r1,r1,#1              ;391
000006  00cb              LSLS     r3,r1,#3
000008  25ff              MOVS     r5,#0xff
00000a  042d              LSLS     r5,r5,#16
00000c  409d              LSLS     r5,r5,r3
00000e  409a              LSLS     r2,r2,r3
000010  43ac              BICS     r4,r4,r5
000012  0412              LSLS     r2,r2,#16
000014  4314              ORRS     r4,r4,r2
000016  6004              STR      r4,[r0,#0]
;;;394        // enable dead zone
;;;395        pwm->CTL |= (PWM_CTL_DZEN01_Msk << u32ChannelNum);
000018  6882              LDR      r2,[r0,#8]
00001a  2310              MOVS     r3,#0x10
00001c  408b              LSLS     r3,r3,r1
00001e  431a              ORRS     r2,r2,r3
000020  6082              STR      r2,[r0,#8]
;;;396    }
000022  bd30              POP      {r4,r5,pc}
;;;397    
                          ENDP


                          AREA ||i.PWM_EnableOutput||, CODE, READONLY, ALIGN=1

                  PWM_EnableOutput PROC
;;;362     */
;;;363    void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
000000  6942              LDR      r2,[r0,#0x14]
;;;364    {
;;;365        pwm->OE |= u32ChannelMask;
000002  430a              ORRS     r2,r2,r1
000004  6142              STR      r2,[r0,#0x14]
;;;366    }
000006  4770              BX       lr
;;;367    
                          ENDP


                          AREA ||i.PWM_EnablePDMA||, CODE, READONLY, ALIGN=2

                  PWM_EnablePDMA PROC
;;;562     */
;;;563    void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
000000  b510              PUSH     {r4,lr}
;;;564    {
;;;565        if (u32ChannelNum == 0)
000002  2900              CMP      r1,#0
;;;566            pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD0_Msk | PWM_CAPCTL_CH0RFORDER_Msk)) | u32Mode | u32RisingFirst | PWM_CAPCTL_CH0PDMAEN_Msk;
;;;567        else
;;;568            pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD2_Msk | PWM_CAPCTL_CH2RFORDER_Msk)) | (u32Mode << 16)| (u32RisingFirst << 16)| PWM_CAPCTL_CH2PDMAEN_Msk;
000004  6d41              LDR      r1,[r0,#0x54]
000006  d00a              BEQ      |L19.30|
000008  4c08              LDR      r4,|L19.44|
00000a  041b              LSLS     r3,r3,#16
00000c  4021              ANDS     r1,r1,r4
00000e  4319              ORRS     r1,r1,r3
000010  0412              LSLS     r2,r2,#16
000012  4311              ORRS     r1,r1,r2
000014  2201              MOVS     r2,#1
000016  04d2              LSLS     r2,r2,#19
                  |L19.24|
000018  4311              ORRS     r1,r1,r2              ;566
00001a  6541              STR      r1,[r0,#0x54]         ;566
;;;569    }
00001c  bd10              POP      {r4,pc}
                  |L19.30|
00001e  4c04              LDR      r4,|L19.48|
000020  4021              ANDS     r1,r1,r4              ;566
000022  4319              ORRS     r1,r1,r3              ;566
000024  4311              ORRS     r1,r1,r2              ;566
000026  2208              MOVS     r2,#8                 ;566
000028  e7f6              B        |L19.24|
;;;570    
                          ENDP

00002a  0000              DCW      0x0000
                  |L19.44|
                          DCD      0xefcfffff
                  |L19.48|
                          DCD      0xffffefcf

                          AREA ||i.PWM_EnablePeriodInt||, CODE, READONLY, ALIGN=1

                  PWM_EnablePeriodInt PROC
;;;507     */
;;;508    void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
000000  68c2              LDR      r2,[r0,#0xc]
;;;509    {
;;;510        // enable period interrupt
;;;511        pwm->INTEN |= (PWM_INTEN_TMIE0_Msk << u32ChannelNum);
000002  2301              MOVS     r3,#1
000004  408b              LSLS     r3,r3,r1
000006  431a              ORRS     r2,r2,r3
000008  60c2              STR      r2,[r0,#0xc]
;;;512    }
00000a  4770              BX       lr
;;;513    
                          ENDP


                          AREA ||i.PWM_ForceStop||, CODE, READONLY, ALIGN=1

                  PWM_ForceStop PROC
;;;250     */
;;;251    void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b570              PUSH     {r4-r6,lr}
;;;252    {
;;;253        uint32_t i;
;;;254        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
000002  2200              MOVS     r2,#0
;;;255            if ( u32ChannelMask  & (1 << i))
000004  2501              MOVS     r5,#1
                  |L21.6|
000006  462b              MOV      r3,r5
000008  4093              LSLS     r3,r3,r2
00000a  420b              TST      r3,r1
00000c  d005              BEQ      |L21.26|
;;;256                pwm->CTL &= ~(PWM_CTL_CH0EN_Msk << (i * 8));
00000e  6884              LDR      r4,[r0,#8]
000010  00d6              LSLS     r6,r2,#3
000012  462b              MOV      r3,r5
000014  40b3              LSLS     r3,r3,r6
000016  439c              BICS     r4,r4,r3
000018  6084              STR      r4,[r0,#8]
                  |L21.26|
00001a  1c52              ADDS     r2,r2,#1              ;254
00001c  2a04              CMP      r2,#4                 ;254
00001e  d3f2              BCC      |L21.6|
;;;257        }
;;;258    }
000020  bd70              POP      {r4-r6,pc}
;;;259    
                          ENDP


                          AREA ||i.PWM_GetADCTriggerFlag||, CODE, READONLY, ALIGN=1

                  PWM_GetADCTriggerFlag PROC
;;;302    */
;;;303    uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  3080              ADDS     r0,r0,#0x80
;;;304    {
;;;305        return ((pwm->ADTRGSTS & (PWM_ADTRGSTS_ADTRG0Flag_Msk << u32ChannelNum)) >> u32ChannelNum);
000002  68c0              LDR      r0,[r0,#0xc]
000004  2201              MOVS     r2,#1
000006  408a              LSLS     r2,r2,r1
000008  4010              ANDS     r0,r0,r2
00000a  40c8              LSRS     r0,r0,r1
;;;306    }
00000c  4770              BX       lr
;;;307    
                          ENDP


                          AREA ||i.PWM_GetCaptureIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_GetCaptureIntFlag PROC
;;;469     */
;;;470    uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6dc0              LDR      r0,[r0,#0x5c]
;;;471    {
;;;472        return ((pwm->CAPINTSTS >> (u32ChannelNum * 8)) & (PWM_RISING_FALLING_LATCH_INT_FLAG));
000002  00c9              LSLS     r1,r1,#3
000004  40c8              LSRS     r0,r0,r1
000006  2106              MOVS     r1,#6
000008  4008              ANDS     r0,r0,r1
;;;473    }
00000a  4770              BX       lr
;;;474    
                          ENDP


                          AREA ||i.PWM_GetDutyIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_GetDutyIntFlag PROC
;;;494     */
;;;495    uint32_t PWM_GetDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6900              LDR      r0,[r0,#0x10]
;;;496    {
;;;497        return ((pwm->INTSTS & (PWM_INTEN_TMIE0_Msk << u32ChannelNum)) ? 1 : 0);
000002  2201              MOVS     r2,#1
000004  408a              LSLS     r2,r2,r1
000006  4010              ANDS     r0,r0,r2
000008  d000              BEQ      |L24.12|
00000a  2001              MOVS     r0,#1
                  |L24.12|
;;;498    }
00000c  4770              BX       lr
;;;499    
                          ENDP


                          AREA ||i.PWM_GetPeriodIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_GetPeriodIntFlag PROC
;;;544     */
;;;545    uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  6900              LDR      r0,[r0,#0x10]
;;;546    {
;;;547        return ((pwm->INTSTS & (PWM_INTSTS_TMINT0_Msk << u32ChannelNum)) ? 1 : 0);
000002  2201              MOVS     r2,#1
000004  408a              LSLS     r2,r2,r1
000006  4010              ANDS     r0,r0,r2
000008  d000              BEQ      |L25.12|
00000a  2001              MOVS     r0,#1
                  |L25.12|
;;;548    }
00000c  4770              BX       lr
;;;549    
                          ENDP


                          AREA ||i.PWM_Start||, CODE, READONLY, ALIGN=1

                  PWM_Start PROC
;;;212     */
;;;213    void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b570              PUSH     {r4-r6,lr}
;;;214    {
;;;215        uint8_t i;
;;;216        uint32_t u32Mask = 0;
000002  2300              MOVS     r3,#0
;;;217    
;;;218        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
000004  461a              MOV      r2,r3
;;;219            if ( u32ChannelMask  & (1 << i))
000006  2601              MOVS     r6,#1
                  |L26.8|
000008  4635              MOV      r5,r6
00000a  4095              LSLS     r5,r5,r2
00000c  4634              MOV      r4,r6
00000e  420d              TST      r5,r1
000010  d002              BEQ      |L26.24|
;;;220                u32Mask |= (PWM_CTL_CH0EN_Msk << (i * 8));
000012  00d5              LSLS     r5,r2,#3
000014  40ac              LSLS     r4,r4,r5
000016  4323              ORRS     r3,r3,r4
                  |L26.24|
000018  1c52              ADDS     r2,r2,#1              ;218
00001a  b2d2              UXTB     r2,r2                 ;218
00001c  2a04              CMP      r2,#4                 ;218
00001e  d3f3              BCC      |L26.8|
;;;221        }
;;;222    
;;;223        pwm->CTL |= u32Mask;
000020  6881              LDR      r1,[r0,#8]
000022  4319              ORRS     r1,r1,r3
000024  6081              STR      r1,[r0,#8]
;;;224    }
000026  bd70              POP      {r4-r6,pc}
;;;225    
                          ENDP


                          AREA ||i.PWM_Stop||, CODE, READONLY, ALIGN=1

                  PWM_Stop PROC
;;;232     */
;;;233    void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;234    {
;;;235        uint32_t i;
;;;236        for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
000002  2200              MOVS     r2,#0
;;;237            if(u32ChannelMask & (1 << i)) {
000004  2401              MOVS     r4,#1
                  |L27.6|
000006  4623              MOV      r3,r4
000008  4093              LSLS     r3,r3,r2
00000a  420b              TST      r3,r1
00000c  d006              BEQ      |L27.28|
;;;238                *(__IO uint32_t *) (&pwm->DUTY0 + 3 * i) &= ~PWM_DUTY0_CN_Msk;
00000e  230c              MOVS     r3,#0xc
000010  4353              MULS     r3,r2,r3
000012  181b              ADDS     r3,r3,r0
000014  69dd              LDR      r5,[r3,#0x1c]
000016  0c2d              LSRS     r5,r5,#16
000018  042d              LSLS     r5,r5,#16
00001a  61dd              STR      r5,[r3,#0x1c]
                  |L27.28|
00001c  1c52              ADDS     r2,r2,#1              ;236
00001e  2a04              CMP      r2,#4                 ;236
000020  d3f1              BCC      |L27.6|
;;;239            }
;;;240        }
;;;241    
;;;242    }
000022  bd30              POP      {r4,r5,pc}
;;;243    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\pwm.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_pwm_c_03ee09af____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_pwm_c_03ee09af____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_pwm_c_03ee09af____REVSH|
#line 132
|__asm___5_pwm_c_03ee09af____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
