; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\system_nano1x2series.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_nano1x2series.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\Device\Nuvoton\Nano1X2Series\Include -I..\..\..\..\Library\StdDriver\inc -I..\..\..\..\Library\CMSIS\Include -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\system_nano1x2series.crf ..\..\..\..\Library\Device\Nuvoton\Nano1X2Series\Source\system_Nano1X2Series.c]
                          THUMB

                          AREA ||i.SysGet_HCLKFreq||, CODE, READONLY, ALIGN=2

                  SysGet_HCLKFreq PROC
;;;58       */
;;;59     uint32_t SysGet_HCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;60     {
;;;61     
;;;62         uint32_t u32Freqout, u32AHBDivider, u32ClkSel;
;;;63     
;;;64         u32ClkSel = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
000002  4c0f              LDR      r4,|L1.64|
000004  6920              LDR      r0,[r4,#0x10]
000006  0741              LSLS     r1,r0,#29
;;;65     
;;;66         if (u32ClkSel == CLK_CLKSEL0_HCLK_S_HXT) {  /* external HXT crystal clock */
;;;67             u32Freqout = __HXT;
000008  480e              LDR      r0,|L1.68|
00000a  0f49              LSRS     r1,r1,#29             ;64
00000c  d009              BEQ      |L1.34|
;;;68         } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LXT) {    /* external LXT crystal clock */
00000e  2901              CMP      r1,#1
000010  d00e              BEQ      |L1.48|
;;;69             u32Freqout = __LXT;
;;;70         } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_PLL) {    /* PLL clock */
000012  2902              CMP      r1,#2
000014  d00f              BEQ      |L1.54|
;;;71             u32Freqout = SysGet_PLLClockFreq();
;;;72         } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LIRC) { /* internal LIRC oscillator clock */
000016  2903              CMP      r1,#3
000018  d010              BEQ      |L1.60|
;;;73             u32Freqout = __LIRC;
;;;74         } else {                                /* internal HIRC oscillator clock */
;;;75             if((CLK->PWRCTL & CLK_PWRCTL_HIRC_FSEL_Msk) == CLK_PWRCTL_HIRC_FSEL_Msk)
00001a  6821              LDR      r1,[r4,#0]
00001c  04c9              LSLS     r1,r1,#19
00001e  d500              BPL      |L1.34|
;;;76                 u32Freqout = __HIRC16M;
000020  4809              LDR      r0,|L1.72|
                  |L1.34|
;;;77             else
;;;78                 u32Freqout = __HIRC12M;
;;;79     
;;;80         }
;;;81         u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK_N_Msk) + 1 ;
000022  69e1              LDR      r1,[r4,#0x1c]
000024  0709              LSLS     r1,r1,#28
000026  0f09              LSRS     r1,r1,#28
000028  1c49              ADDS     r1,r1,#1
;;;82     
;;;83         return (u32Freqout/u32AHBDivider);
00002a  f7fffffe          BL       __aeabi_uidivmod
;;;84     }
00002e  bd10              POP      {r4,pc}
                  |L1.48|
000030  2001              MOVS     r0,#1                 ;69
000032  03c0              LSLS     r0,r0,#15             ;69
000034  e7f5              B        |L1.34|
                  |L1.54|
000036  f7fffffe          BL       SysGet_PLLClockFreq
00003a  e7f2              B        |L1.34|
                  |L1.60|
00003c  4803              LDR      r0,|L1.76|
00003e  e7f0              B        |L1.34|
;;;85     
                          ENDP

                  |L1.64|
                          DCD      0x50000200
                  |L1.68|
                          DCD      0x00b71b00
                  |L1.72|
                          DCD      0x00f42400
                  |L1.76|
                          DCD      0x00002710

                          AREA ||i.SysGet_PLLClockFreq||, CODE, READONLY, ALIGN=2

                  SysGet_PLLClockFreq PROC
;;;26       */
;;;27     uint32_t SysGet_PLLClockFreq(void)
000000  b510              PUSH     {r4,lr}
;;;28     {
;;;29         uint32_t u32Freq =0, u32PLLSrc;
;;;30         uint32_t u32SRC_N,u32PLL_M,u32PllReg;
;;;31     
;;;32         u32PllReg = CLK->PLLCTL;
000002  490b              LDR      r1,|L2.48|
000004  6a4a              LDR      r2,[r1,#0x24]
;;;33     
;;;34         if (u32PllReg & CLK_PLLCTL_PD)
000006  03d0              LSLS     r0,r2,#15
000008  d501              BPL      |L2.14|
;;;35             return 0;    /* PLL is in power down mode */
00000a  2000              MOVS     r0,#0
;;;36     
;;;37         if (u32PllReg & CLK_PLLCTL_PLL_SRC_HIRC) {
;;;38             if(CLK->PLLCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
;;;39                 u32PLLSrc =__HIRC16M;
;;;40             else
;;;41                 u32PLLSrc =__HIRC12M;
;;;42         } else
;;;43             u32PLLSrc = __HXT;
;;;44     
;;;45         u32SRC_N = (u32PllReg & CLK_PLLCTL_PLL_SRC_N_Msk) >> CLK_PLLCTL_PLL_SRC_N_Pos;
;;;46         u32PLL_M = (u32PllReg & CLK_PLLCTL_PLL_MLP_Msk) >> CLK_PLLCTL_PLL_MLP_Pos;
;;;47     
;;;48         u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
;;;49     
;;;50         return u32Freq;
;;;51     }
00000c  bd10              POP      {r4,pc}
                  |L2.14|
00000e  4809              LDR      r0,|L2.52|
000010  0393              LSLS     r3,r2,#14             ;37
000012  d503              BPL      |L2.28|
000014  6a49              LDR      r1,[r1,#0x24]         ;38
000016  04c9              LSLS     r1,r1,#19             ;38
000018  d500              BPL      |L2.28|
00001a  4807              LDR      r0,|L2.56|
                  |L2.28|
00001c  0511              LSLS     r1,r2,#20             ;45
00001e  0692              LSLS     r2,r2,#26             ;46
000020  0f09              LSRS     r1,r1,#28             ;45
000022  0e92              LSRS     r2,r2,#26             ;46
000024  4350              MULS     r0,r2,r0              ;48
000026  1c49              ADDS     r1,r1,#1              ;48
000028  f7fffffe          BL       __aeabi_uidivmod
00002c  bd10              POP      {r4,pc}
;;;52     
                          ENDP

00002e  0000              DCW      0x0000
                  |L2.48|
                          DCD      0x50000200
                  |L2.52|
                          DCD      0x00b71b00
                  |L2.56|
                          DCD      0x00f42400

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;93     
;;;94     void SystemCoreClockUpdate (void)
000000  b510              PUSH     {r4,lr}
;;;95     {
;;;96     
;;;97         SystemCoreClock = SysGet_HCLKFreq();
000002  f7fffffe          BL       SysGet_HCLKFreq
000006  4c04              LDR      r4,|L3.24|
;;;98         CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
000008  4904              LDR      r1,|L3.28|
00000a  6020              STR      r0,[r4,#0]  ; SystemCoreClock
00000c  104a              ASRS     r2,r1,#1
00000e  1880              ADDS     r0,r0,r2
000010  f7fffffe          BL       __aeabi_uidivmod
000014  6060              STR      r0,[r4,#4]  ; CyclesPerUs
;;;99     }
000016  bd10              POP      {r4,pc}
;;;100    
                          ENDP

                  |L3.24|
                          DCD      ||.data||
                  |L3.28|
                          DCD      0x000f4240

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x00b71b00
                  CyclesPerUs
                          DCD      0x0000000c

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\Device\\Nuvoton\\Nano1X2Series\\Source\\system_Nano1X2Series.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___22_system_Nano1X2Series_c_5d646a67____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___22_system_Nano1X2Series_c_5d646a67____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___22_system_Nano1X2Series_c_5d646a67____REVSH|
#line 132
|__asm___22_system_Nano1X2Series_c_5d646a67____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
