; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\timer.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\timer.d --cpu=Cortex-M0 --apcs=interwork -I..\..\..\..\Library\Device\Nuvoton\Nano1X2Series\Include -I..\..\..\..\Library\StdDriver\inc -I..\..\..\..\Library\CMSIS\Include -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\timer.crf ..\..\..\..\Library\StdDriver\src\timer.c]
                          THUMB

                          AREA ||i.TIMER_Close||, CODE, READONLY, ALIGN=1

                  TIMER_Close PROC
;;;68       */
;;;69     void TIMER_Close(TIMER_T *timer)
000000  2100              MOVS     r1,#0
;;;70     {
;;;71         timer->CTL = 0;
000002  6001              STR      r1,[r0,#0]
;;;72         timer->IER = 0;
000004  60c1              STR      r1,[r0,#0xc]
;;;73     }
000006  4770              BX       lr
;;;74     
                          ENDP


                          AREA ||i.TIMER_Delay||, CODE, READONLY, ALIGN=2

                  TIMER_Delay PROC
;;;82       */
;;;83     void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
000000  b5f8              PUSH     {r3-r7,lr}
;;;84     {
000002  460f              MOV      r7,r1
000004  4605              MOV      r5,r0
;;;85         uint32_t u32Clk = TIMER_GetModuleClock(timer);
000006  f7fffffe          BL       TIMER_GetModuleClock
00000a  4606              MOV      r6,r0
;;;86         uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
00000c  2000              MOVS     r0,#0
00000e  9000              STR      r0,[sp,#0]
000010  481e              LDR      r0,|L2.140|
000012  4631              MOV      r1,r6
000014  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
000016  f7fffffe          BL       __aeabi_uidivmod
00001a  4604              MOV      r4,r0
;;;87         float fCmpr;
;;;88     
;;;89         // Clear current timer configuration
;;;90         timer->CTL = 0;
00001c  2000              MOVS     r0,#0
00001e  6028              STR      r0,[r5,#0]
;;;91     
;;;92         if(u32Clk == 10000) {         // min delay is 100us if timer clock source is LIRC 10k
000020  481b              LDR      r0,|L2.144|
000022  4286              CMP      r6,r0
000024  d106              BNE      |L2.52|
;;;93             u32Usec = ((u32Usec + 99) / 100) * 100;
000026  4638              MOV      r0,r7
000028  2164              MOVS     r1,#0x64
00002a  3063              ADDS     r0,r0,#0x63
00002c  f7fffffe          BL       __aeabi_uidivmod
000030  2164              MOVS     r1,#0x64
000032  e005              B        |L2.64|
                  |L2.52|
;;;94         } else {    // 10 usec every step
;;;95             u32Usec = ((u32Usec + 9) / 10) * 10;
000034  4638              MOV      r0,r7
000036  210a              MOVS     r1,#0xa
000038  3009              ADDS     r0,r0,#9
00003a  f7fffffe          BL       __aeabi_uidivmod
00003e  210a              MOVS     r1,#0xa
                  |L2.64|
000040  4348              MULS     r0,r1,r0
000042  4607              MOV      r7,r0
;;;96         }
;;;97     
;;;98         if(u32Clk > 0xFFFFFF) { // For Mini, only needs to consider 24MHz at most
000044  4813              LDR      r0,|L2.148|
000046  4286              CMP      r6,r0
000048  d902              BLS      |L2.80|
;;;99             u32Prescale = 1;
00004a  2001              MOVS     r0,#1
;;;100            u32Clk >>= 1;
00004c  0876              LSRS     r6,r6,#1
00004e  9000              STR      r0,[sp,#0]
                  |L2.80|
;;;101        }
;;;102    
;;;103        // u32Usec * u32Clk might overflow if using uint32_t
;;;104        fCmpr = ((float)u32Usec * (float)u32Clk) / 1000000.0;
000050  4630              MOV      r0,r6
000052  f7fffffe          BL       __aeabi_ui2f
000056  4606              MOV      r6,r0
000058  4638              MOV      r0,r7
00005a  f7fffffe          BL       __aeabi_ui2f
00005e  4631              MOV      r1,r6
000060  f7fffffe          BL       __aeabi_fmul
000064  490c              LDR      r1,|L2.152|
000066  f7fffffe          BL       __aeabi_fdiv
;;;105    
;;;106        timer->CMPR = (uint32_t)fCmpr;
00006a  f7fffffe          BL       __aeabi_f2uiz
00006e  60a8              STR      r0,[r5,#8]
;;;107        timer->CTL = TIMER_CTL_TMR_EN_Msk | u32Prescale; // one shot mode
000070  9800              LDR      r0,[sp,#0]
000072  2101              MOVS     r1,#1
000074  4308              ORRS     r0,r0,r1
000076  6028              STR      r0,[r5,#0]
;;;108    
;;;109        // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
;;;110        // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
;;;111        for(; delay > 0; delay--) {
000078  2c00              CMP      r4,#0
00007a  d002              BEQ      |L2.130|
                  |L2.124|
;;;112            __NOP();
00007c  bf00              NOP      
00007e  1e64              SUBS     r4,r4,#1              ;111
000080  d1fc              BNE      |L2.124|
                  |L2.130|
;;;113        }
;;;114    
;;;115        while(timer->CTL & TIMER_CTL_TMR_ACT_Msk);
000082  6828              LDR      r0,[r5,#0]
000084  0600              LSLS     r0,r0,#24
000086  d4fc              BMI      |L2.130|
;;;116    
;;;117    }
000088  bdf8              POP      {r3-r7,pc}
;;;118    
                          ENDP

00008a  0000              DCW      0x0000
                  |L2.140|
                          DCD      SystemCoreClock
                  |L2.144|
                          DCD      0x00002710
                  |L2.148|
                          DCD      0x00ffffff
                  |L2.152|
                          DCD      0x49742400

                          AREA ||i.TIMER_DisableCapture||, CODE, READONLY, ALIGN=1

                  TIMER_DisableCapture PROC
;;;147      */
;;;148    void TIMER_DisableCapture(TIMER_T *timer)
000000  6801              LDR      r1,[r0,#0]
;;;149    {
;;;150        timer->CTL &= ~TIMER_CTL_TCAP_EN_Msk;
000002  2201              MOVS     r2,#1
000004  0412              LSLS     r2,r2,#16
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;151    
;;;152    }
00000a  4770              BX       lr
;;;153    
                          ENDP


                          AREA ||i.TIMER_DisableEventCounter||, CODE, READONLY, ALIGN=1

                  TIMER_DisableEventCounter PROC
;;;173      */
;;;174    void TIMER_DisableEventCounter(TIMER_T *timer)
000000  6801              LDR      r1,[r0,#0]
;;;175    {
;;;176        timer->CTL &= ~TIMER_CTL_EVENT_EN_Msk;
000002  2201              MOVS     r2,#1
000004  0312              LSLS     r2,r2,#12
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;177    }
00000a  4770              BX       lr
;;;178    
                          ENDP


                          AREA ||i.TIMER_DisableFreqCounter||, CODE, READONLY, ALIGN=1

                  TIMER_DisableFreqCounter PROC
;;;264      */
;;;265    void TIMER_DisableFreqCounter(TIMER_T *timer)
000000  6801              LDR      r1,[r0,#0]
;;;266    {
;;;267        timer->CTL &= ~(TIMER_CTL_INTR_TRG_EN_Msk | TIMER_CTL_INTR_TRG_MODE_Msk);
000002  2203              MOVS     r2,#3
000004  0612              LSLS     r2,r2,#24
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;268    }
00000a  4770              BX       lr
;;;269    
                          ENDP


                          AREA ||i.TIMER_EnableCapture||, CODE, READONLY, ALIGN=1

                  TIMER_EnableCapture PROC
;;;133      */
;;;134    void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
000000  b510              PUSH     {r4,lr}
;;;135    {
;;;136    
;;;137        timer->CTL = (timer->CTL & ~(TIMER_CTL_TCAP_MODE_Msk |
000002  6803              LDR      r3,[r0,#0]
000004  240f              MOVS     r4,#0xf
000006  0464              LSLS     r4,r4,#17
000008  43a3              BICS     r3,r3,r4
00000a  430b              ORRS     r3,r3,r1
00000c  2101              MOVS     r1,#1
00000e  4313              ORRS     r3,r3,r2
000010  0409              LSLS     r1,r1,#16
000012  430b              ORRS     r3,r3,r1
000014  6003              STR      r3,[r0,#0]
;;;138                                     TIMER_CTL_TCAP_CNT_MODE_Msk |
;;;139                                     TIMER_CTL_TCAP_EDGE_Msk)) |
;;;140                     u32CapMode | u32Edge | TIMER_CTL_TCAP_EN_Msk;
;;;141    }
000016  bd10              POP      {r4,pc}
;;;142    
                          ENDP


                          AREA ||i.TIMER_EnableEventCounter||, CODE, READONLY, ALIGN=1

                  TIMER_EnableEventCounter PROC
;;;162      */
;;;163    void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
000000  6802              LDR      r2,[r0,#0]
;;;164    {
;;;165        timer->CTL = (timer->CTL & ~TIMER_CTL_EVENT_EDGE_Msk) | u32Edge;
000002  2301              MOVS     r3,#1
000004  035b              LSLS     r3,r3,#13
000006  439a              BICS     r2,r2,r3
000008  430a              ORRS     r2,r2,r1
00000a  6002              STR      r2,[r0,#0]
;;;166        timer->CTL |= TIMER_CTL_EVENT_EN_Msk;
00000c  6801              LDR      r1,[r0,#0]
00000e  105a              ASRS     r2,r3,#1
000010  4311              ORRS     r1,r1,r2
000012  6001              STR      r1,[r0,#0]
;;;167    }
000014  4770              BX       lr
;;;168    
                          ENDP


                          AREA ||i.TIMER_EnableFreqCounter||, CODE, READONLY, ALIGN=2

                  TIMER_EnableFreqCounter PROC
;;;237      */
;;;238    void TIMER_EnableFreqCounter(TIMER_T *timer,
000000  b510              PUSH     {r4,lr}
;;;239                                 uint32_t u32DropCount,
;;;240                                 uint32_t u32Timeout,
;;;241                                 uint32_t u32EnableInt)
;;;242    {
;;;243        uint32_t mode = TIMER_CTL_INTR_TRG_EN_Msk;
000002  2401              MOVS     r4,#1
000004  0624              LSLS     r4,r4,#24
;;;244        TIMER_T *t;    // store the timer base to configure compare value
;;;245    
;;;246        if(u32DropCount != 0 || u32Timeout >= 2)
000006  2900              CMP      r1,#0
000008  d101              BNE      |L8.14|
00000a  2a02              CMP      r2,#2
00000c  d303              BCC      |L8.22|
                  |L8.14|
;;;247            mode |= TIMER_CTL_INTR_TRG_MODE_Msk;
00000e  2403              MOVS     r4,#3
000010  0624              LSLS     r4,r4,#24
;;;248        if(u32Timeout < 2)
000012  2a02              CMP      r2,#2
000014  d200              BCS      |L8.24|
                  |L8.22|
;;;249            u32Timeout = 0xFFFFFF;
000016  4a0a              LDR      r2,|L8.64|
                  |L8.24|
;;;250    
;;;251        timer->ECTL = u32DropCount << TIMER_ECTL_EVNT_DROP_CNT_Pos;
000018  0609              LSLS     r1,r1,#24
00001a  6201              STR      r1,[r0,#0x20]
;;;252        t = (timer == TIMER0) ? TIMER1 : TIMER3;
00001c  4909              LDR      r1,|L8.68|
00001e  4288              CMP      r0,r1
000020  d101              BNE      |L8.38|
000022  4909              LDR      r1,|L8.72|
000024  e000              B        |L8.40|
                  |L8.38|
000026  4909              LDR      r1,|L8.76|
                  |L8.40|
;;;253    
;;;254        t->CMPR = u32Timeout;
000028  608a              STR      r2,[r1,#8]
;;;255        t->IER = u32EnableInt ? TIMER_IER_TCAP_IE_Msk : 0;
00002a  2b00              CMP      r3,#0
00002c  d001              BEQ      |L8.50|
00002e  2202              MOVS     r2,#2
000030  e000              B        |L8.52|
                  |L8.50|
000032  2200              MOVS     r2,#0
                  |L8.52|
000034  60ca              STR      r2,[r1,#0xc]
;;;256        timer->CTL = mode | TIMER_CTL_TMR_EN_Msk;
000036  2101              MOVS     r1,#1
000038  430c              ORRS     r4,r4,r1
00003a  6004              STR      r4,[r0,#0]
;;;257    
;;;258        return;
;;;259    }
00003c  bd10              POP      {r4,pc}
;;;260    /**
                          ENDP

00003e  0000              DCW      0x0000
                  |L8.64|
                          DCD      0x00ffffff
                  |L8.68|
                          DCD      0x40010000
                  |L8.72|
                          DCD      0x40010100
                  |L8.76|
                          DCD      0x40110100

                          AREA ||i.TIMER_GetModuleClock||, CODE, READONLY, ALIGN=2

                  TIMER_GetModuleClock PROC
;;;184      */
;;;185    uint32_t TIMER_GetModuleClock(TIMER_T *timer)
000000  b51f              PUSH     {r0-r4,lr}
;;;186    {
;;;187        uint32_t u32Src;
;;;188        const uint32_t au32Clk[] = {__HXT, __LXT, __LIRC, 0};   // we don't know actual clock if external pin is clock source, set to 0 here
000002  4c16              LDR      r4,|L9.92|
000004  cc1e              LDM      r4,{r1-r4}
;;;189    
;;;190        if(timer == TIMER0)
000006  9403              STR      r4,[sp,#0xc]
000008  466c              MOV      r4,sp
00000a  c40e              STM      r4!,{r1-r3}
00000c  4a14              LDR      r2,|L9.96|
;;;191            u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0_S_Msk) >> CLK_CLKSEL1_TMR0_S_Pos;
00000e  4915              LDR      r1,|L9.100|
000010  4290              CMP      r0,r2                 ;190
000012  d101              BNE      |L9.24|
000014  6948              LDR      r0,[r1,#0x14]
000016  e008              B        |L9.42|
                  |L9.24|
;;;192        else if(timer == TIMER1)
000018  4a13              LDR      r2,|L9.104|
00001a  4290              CMP      r0,r2
00001c  d101              BNE      |L9.34|
;;;193            u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1_S_Msk) >> CLK_CLKSEL1_TMR1_S_Pos;
00001e  6948              LDR      r0,[r1,#0x14]
000020  e006              B        |L9.48|
                  |L9.34|
;;;194        else if(timer == TIMER2)
000022  4a12              LDR      r2,|L9.108|
000024  4290              CMP      r0,r2
;;;195            u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR2_S_Msk) >> CLK_CLKSEL2_TMR2_S_Pos;
;;;196        else // Timer 3
;;;197            u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR3_S_Msk) >> CLK_CLKSEL2_TMR3_S_Pos;
000026  6988              LDR      r0,[r1,#0x18]
000028  d102              BNE      |L9.48|
                  |L9.42|
00002a  0540              LSLS     r0,r0,#21             ;195
00002c  0f40              LSRS     r0,r0,#29             ;195
00002e  e001              B        |L9.52|
                  |L9.48|
000030  0440              LSLS     r0,r0,#17
000032  0f40              LSRS     r0,r0,#29
                  |L9.52|
;;;198    
;;;199        if(u32Src < 4)
000034  2804              CMP      r0,#4
000036  d204              BCS      |L9.66|
;;;200            return au32Clk[u32Src];
000038  0080              LSLS     r0,r0,#2
00003a  4669              MOV      r1,sp
00003c  5808              LDR      r0,[r1,r0]
                  |L9.62|
;;;201        else if(u32Src == 4) {
;;;202            if((CLK->PWRCTL & CLK_PWRCTL_HIRC_FSEL_Msk) == CLK_PWRCTL_HIRC_FSEL_Msk)
;;;203                return __HIRC16M;
;;;204            else
;;;205                return __HIRC12M;
;;;206        } else
;;;207            return CLK_GetHCLKFreq();
;;;208    }
00003e  b004              ADD      sp,sp,#0x10
000040  bd10              POP      {r4,pc}
                  |L9.66|
000042  2804              CMP      r0,#4                 ;201
000044  d002              BEQ      |L9.76|
000046  f7fffffe          BL       CLK_GetHCLKFreq
00004a  e7f8              B        |L9.62|
                  |L9.76|
00004c  6808              LDR      r0,[r1,#0]            ;202
00004e  04c0              LSLS     r0,r0,#19             ;202
000050  d501              BPL      |L9.86|
000052  4807              LDR      r0,|L9.112|
000054  e7f3              B        |L9.62|
                  |L9.86|
000056  4807              LDR      r0,|L9.116|
000058  e7f1              B        |L9.62|
;;;209    
                          ENDP

00005a  0000              DCW      0x0000
                  |L9.92|
                          DCD      ||.constdata||
                  |L9.96|
                          DCD      0x40010000
                  |L9.100|
                          DCD      0x50000200
                  |L9.104|
                          DCD      0x40010100
                  |L9.108|
                          DCD      0x40110000
                  |L9.112|
                          DCD      0x00f42400
                  |L9.116|
                          DCD      0x00b71b00

                          AREA ||i.TIMER_Open||, CODE, READONLY, ALIGN=2

                  TIMER_Open PROC
;;;40       */
;;;41     uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
000000  b5f7              PUSH     {r0-r2,r4-r7,lr}
;;;42     {
000002  4606              MOV      r6,r0
000004  4617              MOV      r7,r2
;;;43         uint32_t u32Clk = TIMER_GetModuleClock(timer);
000006  f7fffffe          BL       TIMER_GetModuleClock
00000a  4604              MOV      r4,r0
;;;44         uint32_t u32Cmpr = 0, u32Prescale = 0;
00000c  2500              MOVS     r5,#0
;;;45     
;;;46         // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
;;;47         if(u32Freq > (u32Clk / 2)) {
00000e  0840              LSRS     r0,r0,#1
000010  42b8              CMP      r0,r7
000012  d201              BCS      |L10.24|
;;;48             u32Cmpr = 2;
000014  2002              MOVS     r0,#2
000016  e008              B        |L10.42|
                  |L10.24|
;;;49         } else {
;;;50             if(u32Clk > 0xFFFFFF) { // For Nano1x2, only needs to consider 32MHz at most
000018  490a              LDR      r1,|L10.68|
00001a  428c              CMP      r4,r1
00001c  d901              BLS      |L10.34|
;;;51                 u32Prescale = 1;
00001e  2501              MOVS     r5,#1
;;;52                 u32Clk >>= 1;
000020  4604              MOV      r4,r0
                  |L10.34|
;;;53             }
;;;54             u32Cmpr = u32Clk / u32Freq;
000022  4639              MOV      r1,r7
000024  4620              MOV      r0,r4
000026  f7fffffe          BL       __aeabi_uidivmod
                  |L10.42|
;;;55         }
;;;56         timer->CMPR = u32Cmpr;
00002a  60b0              STR      r0,[r6,#8]
;;;57         timer->PRECNT = u32Prescale;
00002c  6075              STR      r5,[r6,#4]
;;;58         timer->CTL = TIMER_CTL_TMR_EN_Msk | u32Mode;
00002e  9901              LDR      r1,[sp,#4]
000030  2201              MOVS     r2,#1
000032  4311              ORRS     r1,r1,r2
000034  6031              STR      r1,[r6,#0]
;;;59     
;;;60     
;;;61         return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
000036  1c6d              ADDS     r5,r5,#1
000038  4368              MULS     r0,r5,r0
00003a  4601              MOV      r1,r0
00003c  4620              MOV      r0,r4
00003e  f7fffffe          BL       __aeabi_uidivmod
;;;62     }
000042  bdfe              POP      {r1-r7,pc}
;;;63     
                          ENDP

                  |L10.68|
                          DCD      0x00ffffff

                          AREA ||i.TIMER_ResetCounter||, CODE, READONLY, ALIGN=1

                  TIMER_ResetCounter PROC
;;;214      */
;;;215    void TIMER_ResetCounter(TIMER_T *timer)
000000  2100              MOVS     r1,#0
;;;216    {
;;;217        // A write with any value to TIMER DR register will trigger timer counter reset
;;;218        timer->DR = 0;
000002  6141              STR      r1,[r0,#0x14]
;;;219    }
000004  4770              BX       lr
;;;220    
                          ENDP


                          AREA ||i.TIMER_SetTriggerSource||, CODE, READONLY, ALIGN=1

                  TIMER_SetTriggerSource PROC
;;;277      */
;;;278    void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
000000  6802              LDR      r2,[r0,#0]
;;;279    {
;;;280        timer->CTL = (timer->CTL & ~TIMER_CTL_CAP_TRG_EN_Msk) | u32Src;
000002  2301              MOVS     r3,#1
000004  02db              LSLS     r3,r3,#11
000006  439a              BICS     r2,r2,r3
000008  430a              ORRS     r2,r2,r1
00000a  6002              STR      r2,[r0,#0]
;;;281    }
00000c  4770              BX       lr
;;;282    
                          ENDP


                          AREA ||i.TIMER_SetTriggerTarget||, CODE, READONLY, ALIGN=1

                  TIMER_SetTriggerTarget PROC
;;;290      */
;;;291    void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
000000  6802              LDR      r2,[r0,#0]
;;;292    {
;;;293        timer->CTL = (timer->CTL & ~(TIMER_CTL_PDMA_TEEN_Msk | TIMER_CTL_ADC_TEEN_Msk)) | u32Mask;
000002  2305              MOVS     r3,#5
000004  021b              LSLS     r3,r3,#8
000006  439a              BICS     r2,r2,r3
000008  430a              ORRS     r2,r2,r1
00000a  6002              STR      r2,[r0,#0]
;;;294    }
00000c  4770              BX       lr
;;;295    
                          ENDP


                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00b71b00
                          DCD      0x00008000
                          DCD      0x00002710
                          DCD      0x00000000

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\timer.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___7_timer_c_5bec749a____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___7_timer_c_5bec749a____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___7_timer_c_5bec749a____REVSH|
#line 132
|__asm___7_timer_c_5bec749a____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
