1. Write ROMStub\ROMStub.bin to Cortex-M0.
   
   You can use "NuMicro ICP Programming Tool" to write the ROMStub.bin.
   If the Cortex-M0 is configured to boot from APROM, write it to the
   beginning of APROM. Otherwise, write it to LDROM.

2. Create your RAM debug project to debug.

   Keil_Smpl_RAMDebug is a sample project for RAM debugging, which is
   modified from an project in ROM. The modifications are:

   a. Change the linker base address on "Options -> Link",
      R/O Base: 0x20000000, which is essentially the start address of RAM.
      R/W Base: 0x20003000

      Please check the real RAM size of your Cortex-M0 on hand, and 
      make sure that there's sufficient RAM size of both R/O and R/W data.
      (Keil_Smpl_RAMDebug is workable on NUC100 chips with 16K RAM size.)

   b. Uncheck "Update Target before Debugging" on "Options->Utility",
      so that Keil will not writing flash ROM before debugging.

   To run Keil_Smpl_RAMDebug, get a copy of NUC100SeriesBSP, and put it at
       NuvotonPlatform_Keil\Sample\Driver\Keil_Smpl_RAMDebug
   then open Smpl_RAMDebug.uv2 to debug.

3. Please be noted ROMStub.bin need only to be written once since it need
   not be modified for next debugging.

