; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\system_m031series.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_m031series.d --cpu=Cortex-M0 --apcs=interwork --diag_suppress=9931 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\M031\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=526 -DxxDEBUG_ENABLE_SEMIHOST --omf_browse=.\obj\system_m031series.crf ..\..\..\..\Library\Device\Nuvoton\M031\Source\system_M031Series.c]
                          THUMB

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;36      */
;;;37     void SystemCoreClockUpdate(void)
000000  b5f8              PUSH     {r3-r7,lr}
;;;38     {
;;;39         uint32_t u32Freq, u32ClkSrc;
;;;40         uint32_t u32HclkDiv;
;;;41     
;;;42         u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
000002  4d1d              LDR      r5,|L1.120|
000004  6928              LDR      r0,[r5,#0x10]
000006  491c              LDR      r1,|L1.120|
000008  0744              LSLS     r4,r0,#29
00000a  a01c              ADR      r0,|L1.124|
00000c  6800              LDR      r0,[r0,#0]
00000e  9000              STR      r0,[sp,#0]
000010  0f64              LSRS     r4,r4,#29
000012  2000              MOVS     r0,#0
000014  3140              ADDS     r1,r1,#0x40
000016  6809              LDR      r1,[r1,#0]
000018  2205              MOVS     r2,#5
00001a  0412              LSLS     r2,r2,#16
00001c  4211              TST      r1,r2
00001e  d116              BNE      |L1.78|
000020  0308              LSLS     r0,r1,#12             ;38
000022  d501              BPL      |L1.40|
000024  4816              LDR      r0,|L1.128|
000026  e000              B        |L1.42|
                  |L1.40|
000028  4816              LDR      r0,|L1.132|
                  |L1.42|
00002a  038a              LSLS     r2,r1,#14             ;38
00002c  d40f              BMI      |L1.78|
00002e  040a              LSLS     r2,r1,#16             ;38
000030  0f92              LSRS     r2,r2,#30             ;38
000032  466b              MOV      r3,sp                 ;38
000034  5c9b              LDRB     r3,[r3,r2]            ;38
000036  05ca              LSLS     r2,r1,#23             ;38
000038  0489              LSLS     r1,r1,#18             ;38
00003a  0dd2              LSRS     r2,r2,#23             ;38
00003c  0ec9              LSRS     r1,r1,#27             ;38
00003e  1c89              ADDS     r1,r1,#2              ;38
000040  0880              LSRS     r0,r0,#2              ;38
000042  1c92              ADDS     r2,r2,#2              ;38
000044  4359              MULS     r1,r3,r1              ;38
000046  4350              MULS     r0,r2,r0              ;38
000048  f7fffffe          BL       __aeabi_uidivmod
00004c  0080              LSLS     r0,r0,#2              ;38
                  |L1.78|
;;;43     
;;;44         /* Update PLL Clock */
;;;45         PllClock = CLK_GetPLLClockFreq();
00004e  4e0e              LDR      r6,|L1.136|
;;;46     
;;;47         if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL)
000050  2c02              CMP      r4,#2
000052  60b0              STR      r0,[r6,#8]  ; PllClock
000054  d002              BEQ      |L1.92|
;;;48         {
;;;49             /* Use the clock sources directly */
;;;50             u32Freq = gau32ClkSrcTbl[u32ClkSrc];
000056  490d              LDR      r1,|L1.140|
000058  00a0              LSLS     r0,r4,#2
00005a  5808              LDR      r0,[r1,r0]
                  |L1.92|
;;;51         }
;;;52         else
;;;53         {
;;;54             /* Use PLL clock */
;;;55             u32Freq = PllClock;
;;;56         }
;;;57     
;;;58         u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
00005c  6a29              LDR      r1,[r5,#0x20]
00005e  0709              LSLS     r1,r1,#28
000060  0f09              LSRS     r1,r1,#28
000062  1c49              ADDS     r1,r1,#1
;;;59     
;;;60         /* Update System Core Clock */
;;;61         SystemCoreClock = u32Freq / u32HclkDiv;
000064  f7fffffe          BL       __aeabi_uidivmod
;;;62     
;;;63         CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
000068  4909              LDR      r1,|L1.144|
00006a  6030              STR      r0,[r6,#0]  ; SystemCoreClock
00006c  104a              ASRS     r2,r1,#1
00006e  1880              ADDS     r0,r0,r2
000070  f7fffffe          BL       __aeabi_uidivmod
000074  6070              STR      r0,[r6,#4]  ; CyclesPerUs
;;;64     }
000076  bdf8              POP      {r3-r7,pc}
;;;65     
                          ENDP

                  |L1.120|
                          DCD      0x40000200
                  |L1.124|
00007c  01020204          DCB      1,2,2,4
                  |L1.128|
                          DCD      0x00b71b00
                  |L1.132|
                          DCD      0x01e84800
                  |L1.136|
                          DCD      ||.data||
                  |L1.140|
                          DCD      ||.constdata||
                  |L1.144|
                          DCD      0x000f4240

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2

                  SystemInit PROC
;;;75      */
;;;76     void SystemInit(void)
000000  b510              PUSH     {r4,lr}
000002  2159              MOVS     r1,#0x59
000004  480a              LDR      r0,|L2.48|
000006  2316              MOVS     r3,#0x16
000008  2288              MOVS     r2,#0x88
                  |L2.10|
00000a  6001              STR      r1,[r0,#0]
00000c  6003              STR      r3,[r0,#0]
00000e  6002              STR      r2,[r0,#0]
000010  6804              LDR      r4,[r0,#0]
000012  2c00              CMP      r4,#0
000014  d0f9              BEQ      |L2.10|
;;;77     {
;;;78         /* Unlock protected registers */
;;;79         SYS_UnlockReg();
;;;80     
;;;81         /* Set HXTGain Level dependend on HXT Frequency */
;;;82         CLK->PWRCTL = CLK->PWRCTL & ~CLK_PWRCTL_HXTGAIN_Msk;
000016  4907              LDR      r1,|L2.52|
000018  680b              LDR      r3,[r1,#0]
00001a  2207              MOVS     r2,#7
00001c  0512              LSLS     r2,r2,#20
00001e  4393              BICS     r3,r3,r2
000020  600b              STR      r3,[r1,#0]
;;;83         if ((__HXT >= FREQ_4MHZ) && (__HXT < FREQ_8MHZ))
;;;84         {
;;;85             CLK->PWRCTL |= (1 << CLK_PWRCTL_HXTGAIN_Pos);
;;;86         }
;;;87         else if ((__HXT >= FREQ_8MHZ) && (__HXT < FREQ_12MHZ))
;;;88         {
;;;89             CLK->PWRCTL |= (2 << CLK_PWRCTL_HXTGAIN_Pos);
;;;90         }
;;;91         else if ((__HXT >= FREQ_12MHZ) && (__HXT < FREQ_16MHZ))
;;;92         {
;;;93             CLK->PWRCTL |= (3 << CLK_PWRCTL_HXTGAIN_Pos);
;;;94         }
;;;95         else if ((__HXT >= FREQ_16MHZ) && (__HXT < FREQ_24MHZ))
;;;96         {
;;;97             CLK->PWRCTL |= (4 << CLK_PWRCTL_HXTGAIN_Pos);
;;;98         }
;;;99         else
;;;100        {
;;;101            CLK->PWRCTL |= (7 << CLK_PWRCTL_HXTGAIN_Pos);
000022  680b              LDR      r3,[r1,#0]
000024  4313              ORRS     r3,r3,r2
000026  600b              STR      r3,[r1,#0]
000028  2100              MOVS     r1,#0
00002a  6001              STR      r1,[r0,#0]
;;;102        }
;;;103    
;;;104        /* Lock protected registers */
;;;105        SYS_LockReg();
;;;106    }
00002c  bd10              POP      {r4,pc}
;;;107    
                          ENDP

00002e  0000              DCW      0x0000
                  |L2.48|
                          DCD      0x40000100
                  |L2.52|
                          DCD      0x40000200

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                  gau32ClkSrcTbl
                          DCD      0x01e84800
                          DCD      0x00008000
                          DCD      0x05b8d800
                          DCD      0x00009600
                          DCD      0x02dc6c00
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x02dc6c00

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x05b8d800
                  CyclesPerUs
                          DCD      0x00000060
                  PllClock
                          DCD      0x05b8d800

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\Device\\Nuvoton\\M031\\Source\\system_M031Series.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___19_system_M031Series_c_5d646a67____REV16|
#line 388 "..\\..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___19_system_M031Series_c_5d646a67____REV16| PROC
#line 389

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___19_system_M031Series_c_5d646a67____REVSH|
#line 402
|__asm___19_system_M031Series_c_5d646a67____REVSH| PROC
#line 403

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
