; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\system_m480.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_m480.d --cpu=Cortex-M4.fp.sp --apcs=interwork --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\M480\Include -I..\..\..\Library\StdDriver\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=538 --omf_browse=.\obj\system_m480.crf ..\..\..\Library\Device\Nuvoton\M480\Source\system_M480.c]
                          THUMB

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;27      *----------------------------------------------------------------------------*/
;;;28     void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
000000  b510              PUSH     {r4,lr}
;;;29     {
;;;30         uint32_t u32Freq, u32ClkSrc;
;;;31         uint32_t u32HclkDiv;
;;;32     
;;;33         /* Update PLL Clock */
;;;34         PllClock = CLK_GetPLLClockFreq();
000002  f7fffffe          BL       CLK_GetPLLClockFreq
000006  4a0e              LDR      r2,|L1.64|
;;;35     
;;;36         u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
000008  f04f4380          MOV      r3,#0x40000000
00000c  6090              STR      r0,[r2,#8]  ; PllClock
00000e  f8d31210          LDR      r1,[r3,#0x210]
000012  f0010107          AND      r1,r1,#7
;;;37     
;;;38         if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
000016  2902              CMP      r1,#2
000018  d003              BEQ      |L1.34|
;;;39         {
;;;40             /* Use PLL clock */
;;;41             u32Freq = PllClock;
;;;42         }
;;;43         else
;;;44         {
;;;45             /* Use the clock sources directly */
;;;46             u32Freq = gau32ClkSrcTbl[u32ClkSrc];
00001a  f102000c          ADD      r0,r2,#0xc
00001e  f8500021          LDR      r0,[r0,r1,LSL #2]
                  |L1.34|
;;;47         }
;;;48     
;;;49         u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
000022  f8d31220          LDR      r1,[r3,#0x220]
000026  f001010f          AND      r1,r1,#0xf
00002a  1c49              ADDS     r1,r1,#1
;;;50     
;;;51         /* Update System Core Clock */
;;;52         SystemCoreClock = u32Freq / u32HclkDiv;
00002c  fbb0f0f1          UDIV     r0,r0,r1
;;;53     
;;;54     
;;;55         //if(SystemCoreClock == 0)
;;;56         //    __BKPT(0);
;;;57     
;;;58         CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
000030  4904              LDR      r1,|L1.68|
000032  6010              STR      r0,[r2,#0]  ; SystemCoreClock
000034  4408              ADD      r0,r0,r1
000036  0049              LSLS     r1,r1,#1
000038  fbb0f0f1          UDIV     r0,r0,r1
00003c  6050              STR      r0,[r2,#4]  ; CyclesPerUs
;;;59     }
00003e  bd10              POP      {r4,pc}
;;;60     
                          ENDP

                  |L1.64|
                          DCD      ||.data||
                  |L1.68|
                          DCD      0x0007a120

                          AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2

                  SystemInit PROC
;;;80      */
;;;81     void SystemInit (void)
000000  481a              LDR      r0,|L2.108|
;;;82     {
;;;83         /* Add your system initialize code here.
;;;84            Do not use global variables because this function is called before
;;;85            reaching pre-main. RW section maybe overwritten afterwards.          */
;;;86     
;;;87     
;;;88         /* FPU settings ------------------------------------------------------------*/
;;;89     #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
;;;90         SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
000002  6801              LDR      r1,[r0,#0]
000004  f4410170          ORR      r1,r1,#0xf00000
000008  6001              STR      r1,[r0,#0]
;;;91                        (3UL << 11*2)  );               /* set CP11 Full Access */
;;;92     #endif
;;;93     
;;;94         /* Set access cycle for CPU @ 192MHz */
;;;95         FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
00000a  4819              LDR      r0,|L2.112|
00000c  6cc1              LDR      r1,[r0,#0x4c]
00000e  f021010f          BIC      r1,r1,#0xf
000012  f0410108          ORR      r1,r1,#8
000016  64c1              STR      r1,[r0,#0x4c]
;;;96         /* Configure power down bias, must set 1 before entering power down mode.
;;;97            So set it at the very beginning */
;;;98         CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
000018  f04f4080          MOV      r0,#0x40000000
00001c  f8d01298          LDR      r1,[r0,#0x298]
000020  f4412180          ORR      r1,r1,#0x40000
000024  f8c01298          STR      r1,[r0,#0x298]
;;;99         /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
;;;100        CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
000028  f8d01208          LDR      r1,[r0,#0x208]
00002c  f0410102          ORR      r1,r1,#2
000030  f8c01208          STR      r1,[r0,#0x208]
;;;101        RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
000034  490f              LDR      r1,|L2.116|
000036  f8d12104          LDR      r2,[r1,#0x104]
00003a  f00232f7          AND      r2,r2,#0xf7f7f7f7
00003e  f8c12104          STR      r2,[r1,#0x104]
;;;102                           RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
;;;103        RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
000042  f8d12108          LDR      r2,[r1,#0x108]
000046  f00232f7          AND      r2,r2,#0xf7f7f7f7
00004a  f8c12108          STR      r2,[r1,#0x108]
;;;104                           RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
;;;105        CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
00004e  f8d01208          LDR      r1,[r0,#0x208]
000052  f0210102          BIC      r1,r1,#2
000056  f8c01208          STR      r1,[r0,#0x208]
00005a  f04f2040          MOV      r0,#0x40004000
00005e  f8d01140          LDR      r1,[r0,#0x140]
000062  f02101f0          BIC      r1,r1,#0xf0
000066  f8c01140          STR      r1,[r0,#0x140]
;;;106        HXTInit();
;;;107    
;;;108    }
00006a  4770              BX       lr
;;;109    /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
                          ENDP

                  |L2.108|
                          DCD      0xe000ed88
                  |L2.112|
                          DCD      0x4000c000
                  |L2.116|
                          DCD      0x40041000

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x00b71b00
                  CyclesPerUs
                          DCD      0x0000000c
                  PllClock
                          DCD      0x00b71b00
                  gau32ClkSrcTbl
                          DCD      0x00b71b00
                          DCD      0x00008000
                          DCD      0x00000000
                          DCD      0x00002710
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00b71b00

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\Library\\Device\\Nuvoton\\M480\\Source\\system_M480.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___13_system_M480_c_5d646a67____REV16|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___13_system_M480_c_5d646a67____REV16| PROC
#line 389

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___13_system_M480_c_5d646a67____REVSH|
#line 402
|__asm___13_system_M480_c_5d646a67____REVSH| PROC
#line 403

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___13_system_M480_c_5d646a67____RRX|
#line 587
|__asm___13_system_M480_c_5d646a67____RRX| PROC
#line 588

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
