; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\main.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\main.d --cpu=Cortex-M4.fp.sp --apcs=interwork --diag_suppress=9931 -I..\..\..\Library\CMSIS\Include -I..\..\..\Library\Device\Nuvoton\M480\Include -I..\..\..\Library\StdDriver\inc -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=538 --omf_browse=.\obj\main.crf ..\main.c]
                          THUMB

                          AREA ||i.ADC_Convert_Ext_Channel||, CODE, READONLY, ALIGN=2

                  ADC_Convert_Ext_Channel PROC
;;;153    
;;;154    void ADC_Convert_Ext_Channel(void)
000000  b570              PUSH     {r4-r6,lr}
;;;155    {
;;;156    
;;;157        /* Set input mode as single-end, and Single mode*/
;;;158        EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END);
000002  4c1d              LDR      r4,|L1.120|
000004  2100              MOVS     r1,#0
000006  4620              MOV      r0,r4
000008  f7fffffe          BL       EADC_Open
;;;159    
;;;160        EADC_SetExtendSampleTime(EADC, 0x0f, 0x3F);
00000c  223f              MOVS     r2,#0x3f
00000e  210f              MOVS     r1,#0xf
000010  4620              MOV      r0,r4
000012  f7fffffe          BL       EADC_SetExtendSampleTime
;;;161    
;;;162        EADC_ConfigSampleModule(EADC, 0, EADC_ADINT0_TRIGGER, 0);
000016  2300              MOVS     r3,#0
000018  f44f3500          MOV      r5,#0x20000
00001c  462a              MOV      r2,r5
00001e  4619              MOV      r1,r3
000020  4620              MOV      r0,r4
000022  f7fffffe          BL       EADC_ConfigSampleModule
;;;163        EADC_ConfigSampleModule(EADC, 1, EADC_ADINT0_TRIGGER, 1);
000026  2301              MOVS     r3,#1
000028  462a              MOV      r2,r5
00002a  4619              MOV      r1,r3
00002c  4620              MOV      r0,r4
00002e  f7fffffe          BL       EADC_ConfigSampleModule
;;;164        EADC_ConfigSampleModule(EADC, 2, EADC_ADINT0_TRIGGER, 2);
000032  2302              MOVS     r3,#2
000034  462a              MOV      r2,r5
000036  4619              MOV      r1,r3
000038  4620              MOV      r0,r4
00003a  f7fffffe          BL       EADC_ConfigSampleModule
;;;165        EADC_ConfigSampleModule(EADC, 3, EADC_ADINT0_TRIGGER, 3);
00003e  2303              MOVS     r3,#3
000040  462a              MOV      r2,r5
000042  4619              MOV      r1,r3
000044  4620              MOV      r0,r4
000046  f7fffffe          BL       EADC_ConfigSampleModule
;;;166    
;;;167    
;;;168        EADC_CLR_INT_FLAG(EADC, EADC_STATUS2_ADIF0_Msk);
00004a  2001              MOVS     r0,#1
00004c  f8c400f8          STR      r0,[r4,#0xf8]
;;;169        EADC_ENABLE_INT(EADC, (BIT0 << 0));
000050  6d20              LDR      r0,[r4,#0x50]
000052  f0400004          ORR      r0,r0,#4
000056  6520              STR      r0,[r4,#0x50]
;;;170    
;;;171        EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 0, 0x7FF);
000058  f8d400d0          LDR      r0,[r4,#0xd0]
00005c  f24071ff          MOV      r1,#0x7ff
000060  4308              ORRS     r0,r0,r1
000062  f8c400d0          STR      r0,[r4,#0xd0]
;;;172    
;;;173        NVIC_EnableIRQ(EADC00_IRQn);
000066  202a              MOVS     r0,#0x2a
000068  f7fffffe          BL       NVIC_EnableIRQ
;;;174    
;;;175        PDMA_Init();
00006c  f7fffffe          BL       PDMA_Init
;;;176    
;;;177        EADC_START_CONV(EADC, 0x0F);
000070  200f              MOVS     r0,#0xf
000072  6560              STR      r0,[r4,#0x54]
;;;178    
;;;179    }
000074  bd70              POP      {r4-r6,pc}
;;;180    
                          ENDP

000076  0000              DCW      0x0000
                  |L1.120|
                          DCD      0x40043000

                          AREA ||i.EADC00_IRQHandler||, CODE, READONLY, ALIGN=2

                  EADC00_IRQHandler PROC
;;;146    
;;;147    void EADC00_IRQHandler(void)
000000  4902              LDR      r1,|L2.12|
;;;148    {
;;;149    //    printf(" EADC00_IRQHandler\r\n");
;;;150        EADC_CLR_INT_FLAG(EADC, EADC_STATUS2_ADIF0_Msk);      /* Clear the A/D ADINT0 interrupt flag */
000002  2001              MOVS     r0,#1
000004  f8c100f8          STR      r0,[r1,#0xf8]
;;;151    }
000008  4770              BX       lr
;;;152    
                          ENDP

00000a  0000              DCW      0x0000
                  |L2.12|
                          DCD      0x40043000

                          AREA ||i.NVIC_EnableIRQ||, CODE, READONLY, ALIGN=1

                  NVIC_EnableIRQ PROC
;;;1625    */
;;;1626   __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
000000  f000021f          AND      r2,r0,#0x1f
;;;1627   {
;;;1628     NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
000004  2101              MOVS     r1,#1
000006  4091              LSLS     r1,r1,r2
000008  0940              LSRS     r0,r0,#5
00000a  0080              LSLS     r0,r0,#2
00000c  f10020e0          ADD      r0,r0,#0xe000e000
000010  f8c01100          STR      r1,[r0,#0x100]
;;;1629   }
000014  4770              BX       lr
;;;1630   
                          ENDP


                          AREA ||i.PDMA_IRQHandler||, CODE, READONLY, ALIGN=2

                  PDMA_IRQHandler PROC
;;;73     
;;;74     void PDMA_IRQHandler(void)
000000  b570              PUSH     {r4-r6,lr}
;;;75     {
;;;76         uint32_t status = PDMA_GET_INT_STATUS(PDMA);
000002  4914              LDR      r1,|L4.84|
000004  6808              LDR      r0,[r1,#0]
;;;77     
;;;78         if (status & PDMA_INTSTS_ABTIF_Msk)   /* abort */
;;;79         {
;;;80     #if 0
;;;81             PDMA_CLR_ABORT_FLAG(PDMA, PDMA_GET_ABORT_STS(PDMA));
;;;82     #else
;;;83             if (PDMA_GET_ABORT_STS(PDMA) & ADC_PDMA_OPENED_CH)
;;;84             {
;;;85                 printf("ABTSTS\r\n");
;;;86             }
;;;87             PDMA_CLR_ABORT_FLAG(PDMA, ADC_PDMA_OPENED_CH);
000006  f04f0510          MOV      r5,#0x10
00000a  07c2              LSLS     r2,r0,#31             ;78
00000c  d007              BEQ      |L4.30|
00000e  1d0c              ADDS     r4,r1,#4              ;83
000010  6820              LDR      r0,[r4,#0]            ;83
000012  06c0              LSLS     r0,r0,#27             ;83
000014  d501              BPL      |L4.26|
000016  a010              ADR      r0,|L4.88|
000018  e00e              B        |L4.56|
                  |L4.26|
00001a  6025              STR      r5,[r4,#0]
                  |L4.28|
;;;88     
;;;89     #endif
;;;90         }
;;;91         else if (status & PDMA_INTSTS_TDIF_Msk)     /* done */
;;;92         {
;;;93             if(PDMA_GET_TD_STS(PDMA) & ADC_PDMA_OPENED_CH)
;;;94             {
;;;95                 //insert process
;;;96                 set_flag(flag_PDMA_Trans_Data_Ready, ENABLE);
;;;97                 printf("TDIF\r\n");
;;;98             }
;;;99     
;;;100            /* Clear PDMA transfer done interrupt flag */
;;;101            PDMA_CLR_TD_FLAG(PDMA, ADC_PDMA_OPENED_CH);
;;;102        }
;;;103        else if (status & (PDMA_INTSTS_REQTOF1_Msk))     /* Check the DMA time-out interrupt flag */
;;;104        {
;;;105            PDMA_CLR_TMOUT_FLAG(PDMA, ADC_PDMA_CH);
;;;106            printf("REQTOF\r\n");
;;;107    
;;;108        }
;;;109        else
;;;110        {
;;;111    
;;;112        }
;;;113    
;;;114    }
00001c  bd70              POP      {r4-r6,pc}
                  |L4.30|
00001e  0782              LSLS     r2,r0,#30             ;91
000020  d50d              BPL      |L4.62|
000022  4c0c              LDR      r4,|L4.84|
000024  3408              ADDS     r4,r4,#8              ;93
000026  6820              LDR      r0,[r4,#0]            ;93
000028  06c0              LSLS     r0,r0,#27             ;93
00002a  d5f6              BPL      |L4.26|
00002c  480d              LDR      r0,|L4.100|
00002e  6801              LDR      r1,[r0,#0]            ;96  ; BitFlag
000030  f0410108          ORR      r1,r1,#8              ;96
000034  6001              STR      r1,[r0,#0]            ;97  ; BitFlag
000036  a00c              ADR      r0,|L4.104|
                  |L4.56|
000038  f7fffffe          BL       __2printf
00003c  e7ed              B        |L4.26|
                  |L4.62|
00003e  0580              LSLS     r0,r0,#22             ;103
000040  d5ec              BPL      |L4.28|
000042  f44f5080          MOV      r0,#0x1000            ;105
000046  6008              STR      r0,[r1,#0]            ;105
000048  e8bd4070          POP      {r4-r6,lr}            ;106
00004c  a008              ADR      r0,|L4.112|
00004e  f7ffbffe          B.W      __2printf
;;;115    
                          ENDP

000052  0000              DCW      0x0000
                  |L4.84|
                          DCD      0x4000841c
                  |L4.88|
000058  41425453          DCB      "ABTSTS\r\n",0
00005c  54530d0a
000060  00      
000061  00                DCB      0
000062  00                DCB      0
000063  00                DCB      0
                  |L4.100|
                          DCD      ||.data||
                  |L4.104|
000068  54444946          DCB      "TDIF\r\n",0
00006c  0d0a00  
00006f  00                DCB      0
                  |L4.112|
000070  52455154          DCB      "REQTOF\r\n",0
000074  4f460d0a
000078  00      
000079  00                DCB      0
00007a  00                DCB      0
00007b  00                DCB      0

                          AREA ||i.PDMA_Init||, CODE, READONLY, ALIGN=2

                  PDMA_Init PROC
;;;116    
;;;117    void PDMA_Init(void)
000000  b57c              PUSH     {r2-r6,lr}
;;;118    {
;;;119        SYS_ResetModule(PDMA_RST);
000002  2002              MOVS     r0,#2
000004  f7fffffe          BL       SYS_ResetModule
;;;120    
;;;121        /* Configure PDMA peripheral mode form ADC to memory */
;;;122        /* Open PDMA Channel 1 based on ADC_PDMA_CH setting*/
;;;123    //    PDMA_Open(PDMA, BIT0 << ADC_PDMA_CH);
;;;124        PDMA_Open(PDMA, 0);
000008  4d1a              LDR      r5,|L5.116|
00000a  2100              MOVS     r1,#0
00000c  4628              MOV      r0,r5
00000e  f7fffffe          BL       PDMA_Open
;;;125    
;;;126        /* transfer width is half word(16 bit) and transfer count is ADCDatalenght+1 */
;;;127        PDMA_SetTransferCnt(PDMA, ADC_PDMA_CH, PDMA_WIDTH_16, ADC_DMA_SAMPLE_COUNT);
000012  2304              MOVS     r3,#4
000014  029a              LSLS     r2,r3,#10
000016  4619              MOV      r1,r3
000018  4628              MOV      r0,r5
00001a  f7fffffe          BL       PDMA_SetTransferCnt
;;;128    
;;;129        /* Set source address as ADC data register (no increment) and destination address as g_i32ConversionData array (increment) */
;;;130        PDMA_SetTransferAddr(PDMA, ADC_PDMA_CH, (uint32_t) & (EADC->CURDAT), PDMA_SAR_FIX, (uint32_t)pdmaConvertedData, PDMA_DAR_INC);
00001e  2400              MOVS     r4,#0
000020  4915              LDR      r1,|L5.120|
000022  e9cd1400          STRD     r1,r4,[sp,#0]
000026  f44f7340          MOV      r3,#0x300
00002a  4a14              LDR      r2,|L5.124|
00002c  2104              MOVS     r1,#4
00002e  4628              MOV      r0,r5
000030  f7fffffe          BL       PDMA_SetTransferAddr
;;;131    
;;;132        /* Select PDMA request source as ADC RX */
;;;133        PDMA_SetTransferMode(PDMA, ADC_PDMA_CH, PDMA_EADC0_RX, FALSE, 0);
000034  2300              MOVS     r3,#0
000036  2232              MOVS     r2,#0x32
000038  2104              MOVS     r1,#4
00003a  4628              MOV      r0,r5
00003c  9400              STR      r4,[sp,#0]
00003e  f7fffffe          BL       PDMA_SetTransferMode
;;;134    
;;;135        /* Set PDMA as single request type for ADC */
;;;136        PDMA_SetBurstType(PDMA, ADC_PDMA_CH, PDMA_REQ_SINGLE, PDMA_BURST_128);
000042  2204              MOVS     r2,#4
000044  2300              MOVS     r3,#0
000046  4611              MOV      r1,r2
000048  4628              MOV      r0,r5
00004a  f7fffffe          BL       PDMA_SetBurstType
;;;137    
;;;138        PDMA_EnableInt(PDMA, ADC_PDMA_CH, PDMA_INT_TRANS_DONE);
00004e  2200              MOVS     r2,#0
000050  2104              MOVS     r1,#4
000052  4628              MOV      r0,r5
000054  f7fffffe          BL       PDMA_EnableInt
;;;139        NVIC_EnableIRQ(PDMA_IRQn);
000058  2028              MOVS     r0,#0x28
00005a  f7fffffe          BL       NVIC_EnableIRQ
;;;140    
;;;141        PDMA_Trigger(PDMA, ADC_PDMA_CH);
00005e  2104              MOVS     r1,#4
000060  4628              MOV      r0,r5
000062  f7fffffe          BL       PDMA_Trigger
;;;142    
;;;143        /* ADC enable PDMA transfer */
;;;144        EADC_ENABLE_PDMA(EADC);
000066  4805              LDR      r0,|L5.124|
000068  384c              SUBS     r0,r0,#0x4c
00006a  6d01              LDR      r1,[r0,#0x50]
00006c  f4416100          ORR      r1,r1,#0x800
000070  6501              STR      r1,[r0,#0x50]
;;;145    }
000072  bd7c              POP      {r2-r6,pc}
;;;146    
                          ENDP

                  |L5.116|
                          DCD      0x40008000
                  |L5.120|
                          DCD      ||.data||+0x4
                  |L5.124|
                          DCD      0x4004304c

                          AREA ||i.ReloadPDMA||, CODE, READONLY, ALIGN=2

                  ReloadPDMA PROC
;;;64     
;;;65     void ReloadPDMA(void)
000000  b538              PUSH     {r3-r5,lr}
;;;66     {
;;;67         /* transfer width is half word(16 bit) and transfer count is ADCDatalenght+1 */
;;;68         PDMA_SetTransferCnt(PDMA, ADC_PDMA_CH, PDMA_WIDTH_16, ADC_DMA_SAMPLE_COUNT);
000002  2304              MOVS     r3,#4
000004  4c07              LDR      r4,|L6.36|
000006  029a              LSLS     r2,r3,#10
000008  4619              MOV      r1,r3
00000a  4620              MOV      r0,r4
00000c  f7fffffe          BL       PDMA_SetTransferCnt
;;;69     
;;;70         /* Select PDMA request source as ADC RX */
;;;71         PDMA_SetTransferMode(PDMA, ADC_PDMA_CH, PDMA_EADC0_RX, FALSE, (uint32_t) 0);
000010  2100              MOVS     r1,#0
000012  460b              MOV      r3,r1
000014  9100              STR      r1,[sp,#0]
000016  2232              MOVS     r2,#0x32
000018  2104              MOVS     r1,#4
00001a  4620              MOV      r0,r4
00001c  f7fffffe          BL       PDMA_SetTransferMode
;;;72     }
000020  bd38              POP      {r3-r5,pc}
;;;73     
                          ENDP

000022  0000              DCW      0x0000
                  |L6.36|
                          DCD      0x40008000

                          AREA ||i.SYS_Init||, CODE, READONLY, ALIGN=2

                  SYS_Init PROC
;;;181    
;;;182    void SYS_Init(void)
000000  b570              PUSH     {r4-r6,lr}
000002  2059              MOVS     r0,#0x59
000004  0784              LSLS     r4,r0,#30
000006  2116              MOVS     r1,#0x16
000008  2288              MOVS     r2,#0x88
                  |L7.10|
00000a  f8c40100          STR      r0,[r4,#0x100]
00000e  f8c41100          STR      r1,[r4,#0x100]
000012  f8c42100          STR      r2,[r4,#0x100]
000016  f8d43100          LDR      r3,[r4,#0x100]
00001a  2b00              CMP      r3,#0
00001c  d0f5              BEQ      |L7.10|
;;;183    {
;;;184        /*---------------------------------------------------------------------------------------------------------*/
;;;185        /* Init System Clock                                                                                       */
;;;186        /*---------------------------------------------------------------------------------------------------------*/
;;;187        /* Unlock protected registers */
;;;188        SYS_UnlockReg();
;;;189    
;;;190        /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
;;;191        PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
00001e  f04f2540          MOV      r5,#0x40004000
000022  f8d50140          LDR      r0,[r5,#0x140]
000026  f02000f0          BIC      r0,r0,#0xf0
00002a  f8c50140          STR      r0,[r5,#0x140]
;;;192    
;;;193        /* Enable External XTAL (4~24 MHz) */
;;;194        CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
00002e  2001              MOVS     r0,#1
000030  f7fffffe          BL       CLK_EnableXtalRC
;;;195    
;;;196        /* Waiting for 12MHz clock ready */
;;;197        CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
000034  2001              MOVS     r0,#1
000036  f7fffffe          BL       CLK_WaitClockReady
;;;198    
;;;199        /* Set core clock as PLL_CLOCK from PLL */
;;;200        CLK_SetCoreClock(FREQ_192MHZ);
00003a  481f              LDR      r0,|L7.184|
00003c  f7fffffe          BL       CLK_SetCoreClock
;;;201        /* Set PCLK0/PCLK1 to HCLK/2 */
;;;202        CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2);
000040  2011              MOVS     r0,#0x11
000042  f8c40234          STR      r0,[r4,#0x234]
;;;203    
;;;204        /* Enable UART clock */
;;;205        CLK_EnableModuleClock(UART0_MODULE);
000046  4e1d              LDR      r6,|L7.188|
000048  4630              MOV      r0,r6
00004a  f7fffffe          BL       CLK_EnableModuleClock
;;;206    
;;;207        /* Select UART clock source from HXT */
;;;208        CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
00004e  2200              MOVS     r2,#0
000050  4611              MOV      r1,r2
000052  4630              MOV      r0,r6
000054  f7fffffe          BL       CLK_SetModuleClock
;;;209    
;;;210        /* Enable EADC module clock */
;;;211        CLK_EnableModuleClock(EADC_MODULE);
000058  4e19              LDR      r6,|L7.192|
00005a  4630              MOV      r0,r6
00005c  f7fffffe          BL       CLK_EnableModuleClock
;;;212    
;;;213        /* EADC clock source is 96MHz, set divider to 8, EADC clock is 96/8 MHz */
;;;214        CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
000060  f44f22e0          MOV      r2,#0x70000
000064  2100              MOVS     r1,#0
000066  4630              MOV      r0,r6
000068  f7fffffe          BL       CLK_SetModuleClock
;;;215    
;;;216        CLK_EnableModuleClock(PDMA_MODULE);
00006c  2001              MOVS     r0,#1
00006e  f7fffffe          BL       CLK_EnableModuleClock
;;;217    
;;;218        /* Update System Core Clock */
;;;219        /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
;;;220        SystemCoreClockUpdate();
000072  f7fffffe          BL       SystemCoreClockUpdate
;;;221    
;;;222        /* Set GPB multi-function pins for UART0 RXD and TXD */
;;;223        SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk | SYS_GPB_MFPH_PB13MFP_Msk);
000076  6be0              LDR      r0,[r4,#0x3c]
000078  f420007f          BIC      r0,r0,#0xff0000
00007c  63e0              STR      r0,[r4,#0x3c]
;;;224        SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB12MFP_UART0_RXD | SYS_GPB_MFPH_PB13MFP_UART0_TXD);
00007e  6be0              LDR      r0,[r4,#0x3c]
000080  f44000cc          ORR      r0,r0,#0x660000
000084  63e0              STR      r0,[r4,#0x3c]
;;;225    
;;;226        PB->MODE &= ~(GPIO_MODE_MODE0_Msk | GPIO_MODE_MODE1_Msk | GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
000086  6c28              LDR      r0,[r5,#0x40]
000088  f02000ff          BIC      r0,r0,#0xff
00008c  6428              STR      r0,[r5,#0x40]
;;;227        SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk);
00008e  6ba0              LDR      r0,[r4,#0x38]
000090  f36f000f          BFC      r0,#0,#16
000094  63a0              STR      r0,[r4,#0x38]
;;;228        SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC0_CH0 | SYS_GPB_MFPL_PB1MFP_EADC0_CH1 | SYS_GPB_MFPL_PB2MFP_EADC0_CH2 | SYS_GPB_MFPL_PB3MFP_EADC0_CH3);
000096  6ba0              LDR      r0,[r4,#0x38]
000098  f2411111          MOV      r1,#0x1111
00009c  4308              ORRS     r0,r0,r1
00009e  63a0              STR      r0,[r4,#0x38]
;;;229        GPIO_DISABLE_DIGITAL_PATH(PB, BIT0 | BIT1 | BIT2 | BIT3);
0000a0  6c68              LDR      r0,[r5,#0x44]
0000a2  f4402070          ORR      r0,r0,#0xf0000
0000a6  6468              STR      r0,[r5,#0x44]
;;;230    
;;;231    
;;;232    
;;;233        /* Set reference voltage to external pin (3.3V) */
;;;234        SYS_SetVRef(SYS_VREFCTL_VREF_PIN);
0000a8  2000              MOVS     r0,#0
0000aa  f7fffffe          BL       SYS_SetVRef
0000ae  2000              MOVS     r0,#0
0000b0  f8c40100          STR      r0,[r4,#0x100]
;;;235    
;;;236        /* Lock protected registers */
;;;237        SYS_LockReg();
;;;238    }
0000b4  bd70              POP      {r4-r6,pc}
;;;239    
                          ENDP

0000b6  0000              DCW      0x0000
                  |L7.184|
                          DCD      0x0b71b000
                  |L7.188|
                          DCD      0x57803d10
                  |L7.192|
                          DCD      0x4003fe1c

                          AREA ||i.main||, CODE, READONLY, ALIGN=2

                          REQUIRE _printf_pre_padding
                          REQUIRE _printf_percent
                          REQUIRE _printf_widthprec
                          REQUIRE _printf_d
                          REQUIRE _printf_int_dec
                          REQUIRE _printf_flags
                  main PROC
;;;247    
;;;248    int main()
000000  b508              PUSH     {r3,lr}
;;;249    {
;;;250    
;;;251        SYS_Init();
000002  f7fffffe          BL       SYS_Init
;;;252        /* Init UART to 115200-8n1 for print message */
;;;253        UART_Open(UART0, 115200);
000006  f44f31e1          MOV      r1,#0x1c200
00000a  481b              LDR      r0,|L8.120|
00000c  f7fffffe          BL       UART_Open
;;;254    
;;;255        printf("\r\nCLK_GetCPUFreq : %8d\r\n", CLK_GetCPUFreq());
000010  f7fffffe          BL       CLK_GetCPUFreq
000014  4601              MOV      r1,r0
000016  a019              ADR      r0,|L8.124|
000018  f7fffffe          BL       __2printf
;;;256        printf("CLK_GetHXTFreq : %8d\r\n", CLK_GetHXTFreq());
00001c  f7fffffe          BL       CLK_GetHXTFreq
000020  4601              MOV      r1,r0
000022  a01d              ADR      r0,|L8.152|
000024  f7fffffe          BL       __2printf
;;;257        printf("CLK_GetLXTFreq : %8d\r\n", CLK_GetLXTFreq());
000028  f7fffffe          BL       CLK_GetLXTFreq
00002c  4601              MOV      r1,r0
00002e  a020              ADR      r0,|L8.176|
000030  f7fffffe          BL       __2printf
;;;258        printf("CLK_GetPCLK0Freq : %8d\r\n", CLK_GetPCLK0Freq());
000034  f7fffffe          BL       CLK_GetPCLK0Freq
000038  4601              MOV      r1,r0
00003a  a023              ADR      r0,|L8.200|
00003c  f7fffffe          BL       __2printf
;;;259        printf("CLK_GetPCLK1Freq : %8d\r\n", CLK_GetPCLK1Freq());
000040  f7fffffe          BL       CLK_GetPCLK1Freq
000044  4601              MOV      r1,r0
000046  a027              ADR      r0,|L8.228|
000048  f7fffffe          BL       __2printf
;;;260    
;;;261        ADC_Convert_Ext_Channel();
00004c  f7fffffe          BL       ADC_Convert_Ext_Channel
;;;262    
;;;263        /* Got no where to go, just loop forever */
;;;264        while(1)
;;;265        {
;;;266    
;;;267    
;;;268            pdmaConvertedData[0] = EADC_GET_CONV_DATA(EADC, 0);
000050  4c2b              LDR      r4,|L8.256|
000052  4d2c              LDR      r5,|L8.260|
                  |L8.84|
000054  6820              LDR      r0,[r4,#0]
000056  b281              UXTH     r1,r0
000058  8029              STRH     r1,[r5,#0]
;;;269            pdmaConvertedData[1] = EADC_GET_CONV_DATA(EADC, 1);
00005a  6860              LDR      r0,[r4,#4]
00005c  b282              UXTH     r2,r0
00005e  806a              STRH     r2,[r5,#2]
;;;270            pdmaConvertedData[2] = EADC_GET_CONV_DATA(EADC, 2);
000060  68a0              LDR      r0,[r4,#8]
000062  b283              UXTH     r3,r0
000064  80ab              STRH     r3,[r5,#4]
;;;271            pdmaConvertedData[3] = EADC_GET_CONV_DATA(EADC, 3);
000066  68e0              LDR      r0,[r4,#0xc]
000068  b280              UXTH     r0,r0
00006a  80e8              STRH     r0,[r5,#6]
;;;272    
;;;273            printf("%04d,%04d,%04d,%04d \r\n", pdmaConvertedData[0], pdmaConvertedData[1], pdmaConvertedData[2], pdmaConvertedData[3] );
00006c  9000              STR      r0,[sp,#0]
00006e  a026              ADR      r0,|L8.264|
000070  f7fffffe          BL       __2printf
000074  e7ee              B        |L8.84|
;;;274    
;;;275        }
;;;276    }
;;;277    
                          ENDP

000076  0000              DCW      0x0000
                  |L8.120|
                          DCD      0x40070000
                  |L8.124|
00007c  0d0a434c          DCB      "\r\nCLK_GetCPUFreq : %8d\r\n",0
000080  4b5f4765
000084  74435055
000088  46726571
00008c  203a2025
000090  38640d0a
000094  00      
000095  00                DCB      0
000096  00                DCB      0
000097  00                DCB      0
                  |L8.152|
000098  434c4b5f          DCB      "CLK_GetHXTFreq : %8d\r\n",0
00009c  47657448
0000a0  58544672
0000a4  6571203a
0000a8  20253864
0000ac  0d0a00  
0000af  00                DCB      0
                  |L8.176|
0000b0  434c4b5f          DCB      "CLK_GetLXTFreq : %8d\r\n",0
0000b4  4765744c
0000b8  58544672
0000bc  6571203a
0000c0  20253864
0000c4  0d0a00  
0000c7  00                DCB      0
                  |L8.200|
0000c8  434c4b5f          DCB      "CLK_GetPCLK0Freq : %8d\r\n",0
0000cc  47657450
0000d0  434c4b30
0000d4  46726571
0000d8  203a2025
0000dc  38640d0a
0000e0  00      
0000e1  00                DCB      0
0000e2  00                DCB      0
0000e3  00                DCB      0
                  |L8.228|
0000e4  434c4b5f          DCB      "CLK_GetPCLK1Freq : %8d\r\n",0
0000e8  47657450
0000ec  434c4b31
0000f0  46726571
0000f4  203a2025
0000f8  38640d0a
0000fc  00      
0000fd  00                DCB      0
0000fe  00                DCB      0
0000ff  00                DCB      0
                  |L8.256|
                          DCD      0x40043000
                  |L8.260|
                          DCD      ||.data||+0x4
                  |L8.264|
000108  25303464          DCB      "%04d,%04d,%04d,%04d \r\n",0
00010c  2c253034
000110  642c2530
000114  34642c25
000118  30346420
00011c  0d0a00  
00011f  00                DCB      0

                          AREA ||.data||, DATA, ALIGN=2

                  BitFlag
                          DCD      0x00000000
                  pdmaConvertedData
000004  0000              DCW      0x0000
000006  0000              DCB      0x00,0x00
                          DCD      0x00000000

                          AREA ||area_number.12||, DATA, ALIGN=0

                          EXPORTAS ||area_number.12||, ||.data||
                  ADC_CH_TypeDef
000000  00                DCB      0x00

;*** Start embedded assembler ***

#line 1 "..\\main.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_b4158b98____REV16|
#line 388 "..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___6_main_c_b4158b98____REV16| PROC
#line 389

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_b4158b98____REVSH|
#line 402
|__asm___6_main_c_b4158b98____REVSH| PROC
#line 403

 revsh r0, r0
 bx lr
	ENDP
	AREA ||.rrx_text||, CODE
	THUMB
	EXPORT |__asm___6_main_c_b4158b98____RRX|
#line 587
|__asm___6_main_c_b4158b98____RRX| PROC
#line 588

 rrx r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***

                  __ARM_use_no_argv EQU 0
