; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\clk.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\clk.d --feedback=.\obj\PWM_Capture.fed --cpu=Cortex-M0 --apcs=interwork -O0 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\Nano100Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\clk.crf ..\..\..\..\Library\StdDriver\src\clk.c]
                          THUMB

                          AREA ||i.CLK_DisableCKO||, CODE, READONLY, ALIGN=2

                  CLK_DisableCKO PROC
;;;30       */
;;;31     void CLK_DisableCKO(void)
000000  4803              LDR      r0,|L1.16|
;;;32     {
;;;33         /* Disable CKO0 clock source */
;;;34         CLK->APBCLK &= (~CLK_APBCLK_FDIV_EN_Msk);
000002  6880              LDR      r0,[r0,#8]
000004  2140              MOVS     r1,#0x40
000006  4388              BICS     r0,r0,r1
000008  4901              LDR      r1,|L1.16|
00000a  6088              STR      r0,[r1,#8]
;;;35     }
00000c  4770              BX       lr
;;;36     
                          ENDP

00000e  0000              DCW      0x0000
                  |L1.16|
                          DCD      0x50000200

                          AREA ||i.CLK_DisableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_DisableModuleClock PROC
;;;437      */
;;;438    void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
000000  4906              LDR      r1,|L2.28|
;;;439    {
;;;440        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4))  &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
000002  0fc2              LSRS     r2,r0,#31
000004  0092              LSLS     r2,r2,#2
000006  5889              LDR      r1,[r1,r2]
000008  06c3              LSLS     r3,r0,#27
00000a  0edb              LSRS     r3,r3,#27
00000c  2201              MOVS     r2,#1
00000e  409a              LSLS     r2,r2,r3
000010  4391              BICS     r1,r1,r2
000012  4a02              LDR      r2,|L2.28|
000014  0fc3              LSRS     r3,r0,#31
000016  009b              LSLS     r3,r3,#2
000018  50d1              STR      r1,[r2,r3]
;;;441    }
00001a  4770              BX       lr
;;;442    
                          ENDP

                  |L2.28|
                          DCD      0x50000204

                          AREA ||i.CLK_DisablePLL||, CODE, READONLY, ALIGN=2

                  CLK_DisablePLL PROC
;;;500      */
;;;501    void CLK_DisablePLL(void)
000000  4803              LDR      r0,|L3.16|
;;;502    {
;;;503        CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
000002  6a40              LDR      r0,[r0,#0x24]
000004  2101              MOVS     r1,#1
000006  0409              LSLS     r1,r1,#16
000008  4388              BICS     r0,r0,r1
00000a  4901              LDR      r1,|L3.16|
00000c  6248              STR      r0,[r1,#0x24]
;;;504    }
00000e  4770              BX       lr
;;;505    
                          ENDP

                  |L3.16|
                          DCD      0x50000200

                          AREA ||i.CLK_DisableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_DisableXtalRC PROC
;;;357      */
;;;358    void CLK_DisableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L4.12|
;;;359    {
;;;360        CLK->PWRCTL &= ~u32ClkMask;
000002  6809              LDR      r1,[r1,#0]
000004  4381              BICS     r1,r1,r0
000006  4a01              LDR      r2,|L4.12|
000008  6011              STR      r1,[r2,#0]
;;;361    }
00000a  4770              BX       lr
;;;362    
                          ENDP

                  |L4.12|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableCKO||, CODE, READONLY, ALIGN=2

                  CLK_EnableCKO PROC
;;;53       */
;;;54     void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  2210              MOVS     r2,#0x10
;;;55     {
;;;56         /* CKO = clock source / 2^(u32ClkDiv + 1) */
;;;57         CLK->FRQDIV = CLK_FRQDIV_FDIV_EN_Msk | u32ClkDiv ;
000002  430a              ORRS     r2,r2,r1
000004  4b07              LDR      r3,|L5.36|
000006  629a              STR      r2,[r3,#0x28]
;;;58     
;;;59         /* Enable CKO clock source */
;;;60         CLK->APBCLK |= CLK_APBCLK_FDIV_EN_Msk;
000008  461a              MOV      r2,r3
00000a  6892              LDR      r2,[r2,#8]
00000c  2340              MOVS     r3,#0x40
00000e  431a              ORRS     r2,r2,r3
000010  4b04              LDR      r3,|L5.36|
000012  609a              STR      r2,[r3,#8]
;;;61     
;;;62         /* Select CKO clock source */
;;;63         CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV_S_Msk)) | u32ClkSrc;
000014  461a              MOV      r2,r3
000016  6992              LDR      r2,[r2,#0x18]
000018  230c              MOVS     r3,#0xc
00001a  439a              BICS     r2,r2,r3
00001c  4302              ORRS     r2,r2,r0
00001e  4b01              LDR      r3,|L5.36|
000020  619a              STR      r2,[r3,#0x18]
;;;64     }
000022  4770              BX       lr
;;;65     
                          ENDP

                  |L5.36|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_EnableModuleClock PROC
;;;397      */
;;;398    void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
000000  4906              LDR      r1,|L6.28|
;;;399    {
;;;400        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4))  |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
000002  0fc2              LSRS     r2,r0,#31
000004  0092              LSLS     r2,r2,#2
000006  5889              LDR      r1,[r1,r2]
000008  06c3              LSLS     r3,r0,#27
00000a  0edb              LSRS     r3,r3,#27
00000c  2201              MOVS     r2,#1
00000e  409a              LSLS     r2,r2,r3
000010  4311              ORRS     r1,r1,r2
000012  4a02              LDR      r2,|L6.28|
000014  0fc3              LSRS     r3,r0,#31
000016  009b              LSLS     r3,r3,#2
000018  50d1              STR      r1,[r2,r3]
;;;401    }
00001a  4770              BX       lr
;;;402    
                          ENDP

                  |L6.28|
                          DCD      0x50000204

                          AREA ||i.CLK_EnablePLL||, CODE, READONLY, ALIGN=2

                  CLK_EnablePLL PROC
;;;450      */
;;;451    uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
000000  b5f3              PUSH     {r0,r1,r4-r7,lr}
;;;452    {
000002  b087              SUB      sp,sp,#0x1c
000004  460f              MOV      r7,r1
;;;453        uint32_t u32ClkSrc,u32NR, u32NF,u32Register;
;;;454        uint32_t u32NRTable[4]= {2,4,8,16};
000006  4830              LDR      r0,|L7.200|
000008  4601              MOV      r1,r0
00000a  c90e              LDM      r1,{r1-r3}
00000c  68c0              LDR      r0,[r0,#0xc]  ; <Data1>
00000e  ac01              ADD      r4,sp,#4
000010  c40e              STM      r4!,{r1-r3}
000012  9004              STR      r0,[sp,#0x10]
;;;455        int32_t i32NRVal;
;;;456        if ( u32PllFreq < FREQ_24MHZ)
000014  482d              LDR      r0,|L7.204|
000016  4287              CMP      r7,r0
000018  d201              BCS      |L7.30|
;;;457            u32PllFreq=FREQ_24MHZ;
00001a  4607              MOV      r7,r0
00001c  e003              B        |L7.38|
                  |L7.30|
;;;458        else if(u32PllFreq > FREQ_128MHZ)
00001e  482c              LDR      r0,|L7.208|
000020  4287              CMP      r7,r0
000022  d900              BLS      |L7.38|
;;;459            u32PllFreq=FREQ_128MHZ;
000024  4607              MOV      r7,r0
                  |L7.38|
;;;460    
;;;461        if(u32PllClkSrc!=CLK_PLLCTL_PLL_SRC_HIRC) {
000026  2101              MOVS     r1,#1
000028  0449              LSLS     r1,r1,#17
00002a  9807              LDR      r0,[sp,#0x1c]
00002c  4288              CMP      r0,r1
00002e  d004              BEQ      |L7.58|
;;;462            /* PLL source clock from HXT */
;;;463            u32Register = (0x0UL<<CLK_PLLCTL_PLL_SRC_Pos);
000030  2000              MOVS     r0,#0
000032  9005              STR      r0,[sp,#0x14]
;;;464            u32ClkSrc = __HXT;
000034  4827              LDR      r0,|L7.212|
000036  9006              STR      r0,[sp,#0x18]
000038  e004              B        |L7.68|
                  |L7.58|
;;;465        } else {
;;;466            /* PLL source clock from HIRC */
;;;467            u32Register = (0x1UL<<CLK_PLLCTL_PLL_SRC_Pos);
00003a  2001              MOVS     r0,#1
00003c  0440              LSLS     r0,r0,#17
00003e  9005              STR      r0,[sp,#0x14]
;;;468            u32ClkSrc =__HIRC12M;
000040  4824              LDR      r0,|L7.212|
000042  9006              STR      r0,[sp,#0x18]
                  |L7.68|
;;;469        }
;;;470    
;;;471        u32NF = u32PllFreq / 1000000;
000044  4924              LDR      r1,|L7.216|
000046  4638              MOV      r0,r7
000048  f7fffffe          BL       __aeabi_uidivmod
00004c  4605              MOV      r5,r0
;;;472        u32NR = u32ClkSrc / 1000000;
00004e  4922              LDR      r1,|L7.216|
000050  9806              LDR      r0,[sp,#0x18]
000052  f7fffffe          BL       __aeabi_uidivmod
000056  4604              MOV      r4,r0
;;;473        if(u32ClkSrc%12==0) {
000058  210c              MOVS     r1,#0xc
00005a  9806              LDR      r0,[sp,#0x18]
00005c  f7fffffe          BL       __aeabi_uidivmod
000060  2900              CMP      r1,#0
000062  d109              BNE      |L7.120|
;;;474            u32NF=(u32NF/3)*4;
000064  2103              MOVS     r1,#3
000066  4628              MOV      r0,r5
000068  f7fffffe          BL       __aeabi_uidivmod
00006c  0085              LSLS     r5,r0,#2
;;;475            u32NR=(u32NR/3)*4;
00006e  2103              MOVS     r1,#3
000070  4620              MOV      r0,r4
000072  f7fffffe          BL       __aeabi_uidivmod
000076  0084              LSLS     r4,r0,#2
                  |L7.120|
;;;476        }
;;;477    
;;;478        while( u32NR>16 || u32NF>(0x3F+32) ) {
000078  e001              B        |L7.126|
                  |L7.122|
;;;479            u32NR = u32NR>>1;
00007a  0864              LSRS     r4,r4,#1
;;;480            u32NF = u32NF>>1;
00007c  086d              LSRS     r5,r5,#1
                  |L7.126|
00007e  2c10              CMP      r4,#0x10              ;478
000080  d8fb              BHI      |L7.122|
000082  2d5f              CMP      r5,#0x5f              ;478
000084  d8f9              BHI      |L7.122|
;;;481        }
;;;482    
;;;483        for(i32NRVal=3; i32NRVal>=0; i32NRVal--)
000086  2603              MOVS     r6,#3
000088  e006              B        |L7.152|
                  |L7.138|
;;;484            if(u32NR==u32NRTable[i32NRVal]) break;
00008a  00b0              LSLS     r0,r6,#2
00008c  a901              ADD      r1,sp,#4
00008e  5808              LDR      r0,[r1,r0]
000090  42a0              CMP      r0,r4
000092  d100              BNE      |L7.150|
000094  e002              B        |L7.156|
                  |L7.150|
000096  1e76              SUBS     r6,r6,#1              ;483
                  |L7.152|
000098  2e00              CMP      r6,#0                 ;483
00009a  daf6              BGE      |L7.138|
                  |L7.156|
00009c  bf00              NOP      
;;;485    
;;;486        CLK->PLLCTL = u32Register | (i32NRVal<<8) | (u32NF - 32) ;
00009e  0230              LSLS     r0,r6,#8
0000a0  9905              LDR      r1,[sp,#0x14]
0000a2  4308              ORRS     r0,r0,r1
0000a4  4629              MOV      r1,r5
0000a6  3920              SUBS     r1,r1,#0x20
0000a8  4308              ORRS     r0,r0,r1
0000aa  490c              LDR      r1,|L7.220|
0000ac  6248              STR      r0,[r1,#0x24]
;;;487    
;;;488        CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
0000ae  4608              MOV      r0,r1
0000b0  6a40              LDR      r0,[r0,#0x24]
0000b2  01c9              LSLS     r1,r1,#7
0000b4  4388              BICS     r0,r0,r1
0000b6  4909              LDR      r1,|L7.220|
0000b8  6248              STR      r0,[r1,#0x24]
;;;489    
;;;490        CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
0000ba  2004              MOVS     r0,#4
0000bc  f7fffffe          BL       CLK_WaitClockReady
;;;491    
;;;492        return CLK_GetPLLClockFreq();
0000c0  f7fffffe          BL       CLK_GetPLLClockFreq
;;;493    
;;;494    }
0000c4  b009              ADD      sp,sp,#0x24
0000c6  bdf0              POP      {r4-r7,pc}
;;;495    
                          ENDP

                  |L7.200|
                          DCD      ||.constdata||
                  |L7.204|
                          DCD      0x016e3600
                  |L7.208|
                          DCD      0x07a12000
                  |L7.212|
                          DCD      0x00b71b00
                  |L7.216|
                          DCD      0x000f4240
                  |L7.220|
                          DCD      0x50000200

                          AREA ||i.CLK_EnableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_EnableXtalRC PROC
;;;332      */
;;;333    void CLK_EnableXtalRC(uint32_t u32ClkMask)
000000  b510              PUSH     {r4,lr}
;;;334    {
000002  4604              MOV      r4,r0
;;;335        CLK->PWRCTL |= u32ClkMask;
000004  480d              LDR      r0,|L8.60|
000006  6800              LDR      r0,[r0,#0]
000008  4320              ORRS     r0,r0,r4
00000a  490c              LDR      r1,|L8.60|
00000c  6008              STR      r0,[r1,#0]
;;;336        if(u32ClkMask & CLK_PWRCTL_HXT_EN_Msk)
00000e  07e0              LSLS     r0,r4,#31
000010  0fc0              LSRS     r0,r0,#31
000012  d002              BEQ      |L8.26|
;;;337            CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk);
000014  2001              MOVS     r0,#1
000016  f7fffffe          BL       CLK_WaitClockReady
                  |L8.26|
;;;338    
;;;339        if(u32ClkMask & CLK_PWRCTL_LXT_EN_Msk)
00001a  2002              MOVS     r0,#2
00001c  4204              TST      r4,r0
00001e  d001              BEQ      |L8.36|
;;;340            CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk);
000020  f7fffffe          BL       CLK_WaitClockReady
                  |L8.36|
;;;341    
;;;342        if(u32ClkMask & CLK_PWRCTL_HIRC_EN_Msk)
000024  2004              MOVS     r0,#4
000026  4204              TST      r4,r0
000028  d002              BEQ      |L8.48|
;;;343            CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk);
00002a  2010              MOVS     r0,#0x10
00002c  f7fffffe          BL       CLK_WaitClockReady
                  |L8.48|
;;;344    
;;;345        if(u32ClkMask & CLK_PWRCTL_LIRC_EN_Msk)
000030  2008              MOVS     r0,#8
000032  4204              TST      r4,r0
000034  d001              BEQ      |L8.58|
;;;346            CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk);
000036  f7fffffe          BL       CLK_WaitClockReady
                  |L8.58|
;;;347    }
00003a  bd10              POP      {r4,pc}
;;;348    
                          ENDP

                  |L8.60|
                          DCD      0x50000200

                          AREA ||i.CLK_GetCPUFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetCPUFreq PROC
;;;129      */
;;;130    uint32_t CLK_GetCPUFreq(void)
000000  b510              PUSH     {r4,lr}
;;;131    {
;;;132        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;133        return SystemCoreClock;
000006  4801              LDR      r0,|L9.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;134    }
00000a  bd10              POP      {r4,pc}
;;;135    
                          ENDP

                  |L9.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHCLKFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHCLKFreq PROC
;;;117      */
;;;118    uint32_t CLK_GetHCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;119    {
;;;120        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;121        return SystemCoreClock;
000006  4801              LDR      r0,|L10.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;122    }
00000a  bd10              POP      {r4,pc}
;;;123    
                          ENDP

                  |L10.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHXTFreq PROC
;;;92       */
;;;93     uint32_t CLK_GetHXTFreq(void)
000000  4804              LDR      r0,|L11.20|
;;;94     {
;;;95         if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN )
000002  6800              LDR      r0,[r0,#0]
000004  07c0              LSLS     r0,r0,#31
000006  0fc0              LSRS     r0,r0,#31
000008  d001              BEQ      |L11.14|
;;;96             return __HXT;
00000a  4803              LDR      r0,|L11.24|
                  |L11.12|
;;;97         else
;;;98             return 0;
;;;99     }
00000c  4770              BX       lr
                  |L11.14|
00000e  2000              MOVS     r0,#0                 ;98
000010  e7fc              B        |L11.12|
;;;100    
                          ENDP

000012  0000              DCW      0x0000
                  |L11.20|
                          DCD      0x50000200
                  |L11.24|
                          DCD      0x00b71b00

                          AREA ||i.CLK_GetLXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetLXTFreq PROC
;;;104      */
;;;105    uint32_t CLK_GetLXTFreq(void)
000000  4804              LDR      r0,|L12.20|
;;;106    {
;;;107        if(CLK->PWRCTL & CLK_PWRCTL_LXT_EN )
000002  6800              LDR      r0,[r0,#0]
000004  2102              MOVS     r1,#2
000006  4208              TST      r0,r1
000008  d001              BEQ      |L12.14|
;;;108            return __LXT;
00000a  0388              LSLS     r0,r1,#14
                  |L12.12|
;;;109        else
;;;110            return 0;
;;;111    }
00000c  4770              BX       lr
                  |L12.14|
00000e  2000              MOVS     r0,#0                 ;110
000010  e7fc              B        |L12.12|
;;;112    
                          ENDP

000012  0000              DCW      0x0000
                  |L12.20|
                          DCD      0x50000200

                          AREA ||i.CLK_GetPLLClockFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetPLLClockFreq PROC
;;;140      */
;;;141    uint32_t CLK_GetPLLClockFreq(void)
000000  b5fe              PUSH     {r1-r7,lr}
;;;142    {
;;;143        uint32_t u32Freq =0, u32PLLSrc;
000002  2000              MOVS     r0,#0
000004  9002              STR      r0,[sp,#8]
;;;144        uint32_t u32NO, u32NR, u32IN_DV, u32PllReg;
;;;145    
;;;146        u32PllReg = CLK->PLLCTL;
000006  481b              LDR      r0,|L13.116|
000008  6a45              LDR      r5,[r0,#0x24]
;;;147    
;;;148        if (u32PllReg & CLK_PLLCTL_PD)
00000a  01c0              LSLS     r0,r0,#7
00000c  4205              TST      r5,r0
00000e  d001              BEQ      |L13.20|
;;;149            return 0;  /* PLL is in power down mode */
000010  2000              MOVS     r0,#0
                  |L13.18|
;;;150    
;;;151        if (u32PllReg & CLK_PLLCTL_PLL_SRC_Msk)
;;;152            u32PLLSrc = __HIRC12M;
;;;153        else
;;;154            u32PLLSrc = __HXT;
;;;155    
;;;156        u32NO = (u32PllReg & CLK_PLLCTL_OUT_DV) ? 2: 1;
;;;157    
;;;158        u32IN_DV = (u32PllReg & CLK_PLLCTL_IN_DV_Msk) >> 8;
;;;159        if (u32IN_DV == 0)
;;;160            u32NR = 2;
;;;161        else if (u32IN_DV == 1)
;;;162            u32NR = 4;
;;;163        else if (u32IN_DV == 2)
;;;164            u32NR = 8;
;;;165        else
;;;166            u32NR = 16;
;;;167    
;;;168        u32Freq = u32PLLSrc * ((u32PllReg & CLK_PLLCTL_FB_DV_Msk) +32) / u32NR / u32NO;
;;;169    
;;;170        return u32Freq;
;;;171    }
000012  bdfe              POP      {r1-r7,pc}
                  |L13.20|
000014  2001              MOVS     r0,#1                 ;151
000016  0440              LSLS     r0,r0,#17             ;151
000018  4205              TST      r5,r0                 ;151
00001a  d001              BEQ      |L13.32|
00001c  4f16              LDR      r7,|L13.120|
00001e  e000              B        |L13.34|
                  |L13.32|
000020  4f15              LDR      r7,|L13.120|
                  |L13.34|
000022  2001              MOVS     r0,#1                 ;156
000024  0300              LSLS     r0,r0,#12             ;156
000026  4205              TST      r5,r0                 ;156
000028  d001              BEQ      |L13.46|
00002a  2002              MOVS     r0,#2                 ;156
00002c  e000              B        |L13.48|
                  |L13.46|
00002e  2001              MOVS     r0,#1                 ;156
                  |L13.48|
000030  9001              STR      r0,[sp,#4]            ;156
000032  2003              MOVS     r0,#3                 ;158
000034  0200              LSLS     r0,r0,#8              ;158
000036  4028              ANDS     r0,r0,r5              ;158
000038  0a06              LSRS     r6,r0,#8              ;158
00003a  2e00              CMP      r6,#0                 ;159
00003c  d101              BNE      |L13.66|
00003e  2402              MOVS     r4,#2                 ;160
000040  e008              B        |L13.84|
                  |L13.66|
000042  2e01              CMP      r6,#1                 ;161
000044  d101              BNE      |L13.74|
000046  2404              MOVS     r4,#4                 ;162
000048  e004              B        |L13.84|
                  |L13.74|
00004a  2e02              CMP      r6,#2                 ;163
00004c  d101              BNE      |L13.82|
00004e  2408              MOVS     r4,#8                 ;164
000050  e000              B        |L13.84|
                  |L13.82|
000052  2410              MOVS     r4,#0x10              ;166
                  |L13.84|
000054  06e9              LSLS     r1,r5,#27             ;168
000056  0ec9              LSRS     r1,r1,#27             ;168
000058  3120              ADDS     r1,r1,#0x20           ;168
00005a  4379              MULS     r1,r7,r1              ;168
00005c  4608              MOV      r0,r1                 ;168
00005e  4621              MOV      r1,r4                 ;168
000060  f7fffffe          BL       __aeabi_uidivmod
000064  9000              STR      r0,[sp,#0]            ;168
000066  9901              LDR      r1,[sp,#4]            ;168
000068  f7fffffe          BL       __aeabi_uidivmod
00006c  9002              STR      r0,[sp,#8]            ;168
00006e  9802              LDR      r0,[sp,#8]            ;170
000070  e7cf              B        |L13.18|
;;;172    
                          ENDP

000072  0000              DCW      0x0000
                  |L13.116|
                          DCD      0x50000200
                  |L13.120|
                          DCD      0x00b71b00

                          AREA ||i.CLK_Idle||, CODE, READONLY, ALIGN=2

                  CLK_Idle PROC
;;;81       */
;;;82     void CLK_Idle(void)
000000  4803              LDR      r0,|L14.16|
;;;83     {
;;;84         CLK->PWRCTL |= (CLK_PWRCTL_PD_EN_Msk );
000002  6800              LDR      r0,[r0,#0]
000004  2140              MOVS     r1,#0x40
000006  4308              ORRS     r0,r0,r1
000008  4901              LDR      r1,|L14.16|
00000a  6008              STR      r0,[r1,#0]
;;;85         __WFI();
00000c  bf30              WFI      
;;;86     }
00000e  4770              BX       lr
;;;87     
                          ENDP

                  |L14.16|
                          DCD      0x50000200

                          AREA ||i.CLK_PowerDown||, CODE, READONLY, ALIGN=2

                  CLK_PowerDown PROC
;;;70       */
;;;71     void CLK_PowerDown(void)
000000  2004              MOVS     r0,#4
;;;72     {
;;;73         SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
000002  4905              LDR      r1,|L15.24|
000004  6108              STR      r0,[r1,#0x10]
;;;74         CLK->PWRCTL |= (CLK_PWRCTL_PD_EN_Msk | CLK_PWRCTL_WK_DLY_Msk );
000006  4805              LDR      r0,|L15.28|
000008  6800              LDR      r0,[r0,#0]
00000a  2150              MOVS     r1,#0x50
00000c  4308              ORRS     r0,r0,r1
00000e  4903              LDR      r1,|L15.28|
000010  6008              STR      r0,[r1,#0]
;;;75         __WFI();
000012  bf30              WFI      
;;;76     }
000014  4770              BX       lr
;;;77     
                          ENDP

000016  0000              DCW      0x0000
                  |L15.24|
                          DCD      0xe000ed00
                  |L15.28|
                          DCD      0x50000200

                          AREA ||i.CLK_SetCoreClock||, CODE, READONLY, ALIGN=2

                  CLK_SetCoreClock PROC
;;;177      */
;;;178    uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
000000  b510              PUSH     {r4,lr}
;;;179    {
000002  4604              MOV      r4,r0
;;;180        if(u32Hclk<FREQ_24MHZ) u32Hclk=FREQ_24MHZ;
000004  480e              LDR      r0,|L16.64|
000006  4284              CMP      r4,r0
000008  d200              BCS      |L16.12|
00000a  4604              MOV      r4,r0
                  |L16.12|
;;;181        if(u32Hclk>FREQ_42MHZ) u32Hclk=FREQ_42MHZ;
00000c  480d              LDR      r0,|L16.68|
00000e  4284              CMP      r4,r0
000010  d900              BLS      |L16.20|
000012  4604              MOV      r4,r0
                  |L16.20|
;;;182    
;;;183        if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN)
000014  480c              LDR      r0,|L16.72|
000016  6800              LDR      r0,[r0,#0]
000018  07c0              LSLS     r0,r0,#31
00001a  0fc0              LSRS     r0,r0,#31
00001c  d004              BEQ      |L16.40|
;;;184            CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT,u32Hclk);
00001e  4621              MOV      r1,r4
000020  2000              MOVS     r0,#0
000022  f7fffffe          BL       CLK_EnablePLL
000026  e004              B        |L16.50|
                  |L16.40|
;;;185        else
;;;186            CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC,u32Hclk);
000028  4621              MOV      r1,r4
00002a  2001              MOVS     r0,#1
00002c  0440              LSLS     r0,r0,#17
00002e  f7fffffe          BL       CLK_EnablePLL
                  |L16.50|
;;;187        CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(1));
000032  2100              MOVS     r1,#0
000034  2002              MOVS     r0,#2
000036  f7fffffe          BL       CLK_SetHCLK
;;;188        return SystemCoreClock;
00003a  4804              LDR      r0,|L16.76|
00003c  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;189    }
00003e  bd10              POP      {r4,pc}
;;;190    
                          ENDP

                  |L16.64|
                          DCD      0x016e3600
                  |L16.68|
                          DCD      0x0280de80
                  |L16.72|
                          DCD      0x50000200
                  |L16.76|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_SetHCLK||, CODE, READONLY, ALIGN=2

                  CLK_SetHCLK PROC
;;;202      */
;;;203    void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b570              PUSH     {r4-r6,lr}
;;;204    {
000002  4604              MOV      r4,r0
000004  460d              MOV      r5,r1
;;;205        CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_N_Msk) | u32ClkDiv;
000006  4808              LDR      r0,|L17.40|
000008  69c0              LDR      r0,[r0,#0x1c]
00000a  0900              LSRS     r0,r0,#4
00000c  0100              LSLS     r0,r0,#4
00000e  4328              ORRS     r0,r0,r5
000010  4905              LDR      r1,|L17.40|
000012  61c8              STR      r0,[r1,#0x1c]
;;;206        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc;
000014  4608              MOV      r0,r1
000016  6900              LDR      r0,[r0,#0x10]
000018  08c0              LSRS     r0,r0,#3
00001a  00c0              LSLS     r0,r0,#3
00001c  4320              ORRS     r0,r0,r4
00001e  6108              STR      r0,[r1,#0x10]
;;;207        SystemCoreClockUpdate();
000020  f7fffffe          BL       SystemCoreClockUpdate
;;;208    }
000024  bd70              POP      {r4-r6,pc}
;;;209    
                          ENDP

000026  0000              DCW      0x0000
                  |L17.40|
                          DCD      0x50000200

                          AREA ||i.CLK_SetModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_SetModuleClock PROC
;;;304    
;;;305    void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b5f0              PUSH     {r4-r7,lr}
;;;306    {
000002  460b              MOV      r3,r1
;;;307        uint32_t u32tmp=0,u32sel=0,u32div=0;
000004  2100              MOVS     r1,#0
000006  2400              MOVS     r4,#0
000008  2500              MOVS     r5,#0
;;;308    
;;;309        if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
00000a  0386              LSLS     r6,r0,#14
00000c  0e36              LSRS     r6,r6,#24
00000e  d00f              BEQ      |L18.48|
;;;310            u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4);
000010  4e12              LDR      r6,|L18.92|
000012  0307              LSLS     r7,r0,#12
000014  0fbf              LSRS     r7,r7,#30
000016  00bf              LSLS     r7,r7,#2
000018  19f5              ADDS     r5,r6,r7
;;;311            u32tmp = *(volatile uint32_t *)(u32div);
00001a  6829              LDR      r1,[r5,#0]
;;;312            u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
00001c  0386              LSLS     r6,r0,#14
00001e  0e37              LSRS     r7,r6,#24
000020  0586              LSLS     r6,r0,#22
000022  0ef6              LSRS     r6,r6,#27
000024  40b7              LSLS     r7,r7,r6
000026  460e              MOV      r6,r1
000028  43be              BICS     r6,r6,r7
00002a  4316              ORRS     r6,r6,r2
00002c  4631              MOV      r1,r6
;;;313            *(volatile uint32_t *)(u32div) = u32tmp;
00002e  6029              STR      r1,[r5,#0]
                  |L18.48|
;;;314        }
;;;315    
;;;316        if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
000030  00c6              LSLS     r6,r0,#3
000032  0f36              LSRS     r6,r6,#28
000034  d010              BEQ      |L18.88|
;;;317            u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
000036  4e09              LDR      r6,|L18.92|
000038  3e0c              SUBS     r6,r6,#0xc
00003a  0047              LSLS     r7,r0,#1
00003c  0fbf              LSRS     r7,r7,#30
00003e  00bf              LSLS     r7,r7,#2
000040  19f4              ADDS     r4,r6,r7
;;;318            u32tmp = *(volatile uint32_t *)(u32sel);
000042  6821              LDR      r1,[r4,#0]
;;;319            u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
000044  00c6              LSLS     r6,r0,#3
000046  0f37              LSRS     r7,r6,#28
000048  01c6              LSLS     r6,r0,#7
00004a  0ef6              LSRS     r6,r6,#27
00004c  40b7              LSLS     r7,r7,r6
00004e  460e              MOV      r6,r1
000050  43be              BICS     r6,r6,r7
000052  431e              ORRS     r6,r6,r3
000054  4631              MOV      r1,r6
;;;320            *(volatile uint32_t *)(u32sel) = u32tmp;
000056  6021              STR      r1,[r4,#0]
                  |L18.88|
;;;321        }
;;;322    }
000058  bdf0              POP      {r4-r7,pc}
;;;323    
                          ENDP

00005a  0000              DCW      0x0000
                  |L18.92|
                          DCD      0x5000021c

                          AREA ||i.CLK_SysTickDelay||, CODE, READONLY, ALIGN=2

                  CLK_SysTickDelay PROC
;;;513      */
;;;514    void CLK_SysTickDelay(uint32_t us)
000000  4908              LDR      r1,|L19.36|
;;;515    {
;;;516        SysTick->LOAD = us * CyclesPerUs;
000002  6809              LDR      r1,[r1,#0]  ; CyclesPerUs
000004  4341              MULS     r1,r0,r1
000006  4a08              LDR      r2,|L19.40|
000008  6151              STR      r1,[r2,#0x14]
;;;517        SysTick->VAL  =  (0x00);
00000a  2100              MOVS     r1,#0
00000c  6191              STR      r1,[r2,#0x18]
;;;518        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
00000e  2105              MOVS     r1,#5
000010  6111              STR      r1,[r2,#0x10]
;;;519    
;;;520        /* Waiting for down-count to zero */
;;;521        while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
000012  bf00              NOP      
                  |L19.20|
000014  4904              LDR      r1,|L19.40|
000016  6909              LDR      r1,[r1,#0x10]
000018  2201              MOVS     r2,#1
00001a  0412              LSLS     r2,r2,#16
00001c  4211              TST      r1,r2
00001e  d0f9              BEQ      |L19.20|
;;;522    }
000020  4770              BX       lr
;;;523    
                          ENDP

000022  0000              DCW      0x0000
                  |L19.36|
                          DCD      CyclesPerUs
                  |L19.40|
                          DCD      0xe000e000

                          AREA ||i.CLK_WaitClockReady||, CODE, READONLY, ALIGN=2

                  CLK_WaitClockReady PROC
;;;537      */
;;;538    uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
000000  4601              MOV      r1,r0
;;;539    {
;;;540        int32_t i32TimeOutCnt;
;;;541    
;;;542        i32TimeOutCnt = __HSI / 200; /* About 5ms */
000002  4a07              LDR      r2,|L20.32|
;;;543    
;;;544        while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask) {
000004  e005              B        |L20.18|
                  |L20.6|
;;;545            if(i32TimeOutCnt-- <= 0)
000006  4610              MOV      r0,r2
000008  1e52              SUBS     r2,r2,#1
00000a  2800              CMP      r0,#0
00000c  dc01              BGT      |L20.18|
;;;546                return 0;
00000e  2000              MOVS     r0,#0
                  |L20.16|
;;;547        }
;;;548        return 1;
;;;549    }
000010  4770              BX       lr
                  |L20.18|
000012  4804              LDR      r0,|L20.36|
000014  68c0              LDR      r0,[r0,#0xc]          ;544
000016  4008              ANDS     r0,r0,r1              ;544
000018  4288              CMP      r0,r1                 ;544
00001a  d1f4              BNE      |L20.6|
00001c  2001              MOVS     r0,#1                 ;548
00001e  e7f7              B        |L20.16|
;;;550    
                          ENDP

                  |L20.32|
                          DCD      0x0000ea60
                  |L20.36|
                          DCD      0x50000200

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00000002
                          DCD      0x00000004
                          DCD      0x00000008
                          DCD      0x00000010

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\clk.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_clk_c_9b5832dc____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_clk_c_9b5832dc____REVSH|
#line 132
|__asm___5_clk_c_9b5832dc____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
