; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\main.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\main.d --feedback=.\obj\PWM_Capture.fed --cpu=Cortex-M0 --apcs=interwork -O0 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\Nano100Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\main.crf ..\main.c]
                          THUMB

                          AREA ||i.PWM0_IRQHandler||, CODE, READONLY, ALIGN=2

                  PWM0_IRQHandler PROC
;;;21     
;;;22     void PWM0_IRQHandler(void)
000000  b570              PUSH     {r4-r6,lr}
;;;23     {
;;;24         static uint8_t token = 0;
;;;25         uint32_t u32CapIntFlag;
;;;26         uint8_t u8Count = cap_index;
000002  481e              LDR      r0,|L1.124|
000004  7805              LDRB     r5,[r0,#0]  ; cap_index
;;;27     
;;;28         if(u8Count >= SAMPLE_CNT)
000006  2d20              CMP      r5,#0x20
000008  db00              BLT      |L1.12|
                  |L1.10|
;;;29             return;
;;;30     
;;;31         // Get channel 2 capture interrupt flag
;;;32         u32CapIntFlag = PWM_GetCaptureIntFlag(PWM0, 2);
;;;33     
;;;34         // Rising latch condition happened
;;;35         if ((u32CapIntFlag & PWM_RISING_LATCH_INT_FLAG) && token == 0) {
;;;36             cap_val[u8Count >> 1][0] = PWM_GET_CAPTURE_RISING_DATA(PWM0, 2);
;;;37             cap_index++;
;;;38             token = 1;
;;;39         }
;;;40         // Falling latch condition happened
;;;41         if ((u32CapIntFlag & PWM_FALLING_LATCH_INT_FLAG) && token == 1) {
;;;42             cap_val[u8Count >> 1][1] = PWM_GET_CAPTURE_FALLING_DATA(PWM0, 2);
;;;43             cap_index++;
;;;44             token = 0;
;;;45         }
;;;46     
;;;47         // Clear channel 2 capture interrupt flag
;;;48         PWM_ClearCaptureIntFlag(PWM0, 2, PWM_RISING_FALLING_LATCH_INT_FLAG);
;;;49     }
00000a  bd70              POP      {r4-r6,pc}
                  |L1.12|
00000c  2102              MOVS     r1,#2                 ;32
00000e  481c              LDR      r0,|L1.128|
000010  f7fffffe          BL       PWM_GetCaptureIntFlag
000014  4604              MOV      r4,r0                 ;32
000016  2002              MOVS     r0,#2                 ;35
000018  4204              TST      r4,r0                 ;35
00001a  d011              BEQ      |L1.64|
00001c  4819              LDR      r0,|L1.132|
00001e  7800              LDRB     r0,[r0,#0]            ;35  ; token
000020  2800              CMP      r0,#0                 ;35
000022  d10d              BNE      |L1.64|
000024  4816              LDR      r0,|L1.128|
000026  6f00              LDR      r0,[r0,#0x70]         ;36
000028  1069              ASRS     r1,r5,#1              ;36
00002a  00c9              LSLS     r1,r1,#3              ;36
00002c  4a16              LDR      r2,|L1.136|
00002e  5050              STR      r0,[r2,r1]            ;36
000030  4812              LDR      r0,|L1.124|
000032  7800              LDRB     r0,[r0,#0]            ;37  ; cap_index
000034  1c40              ADDS     r0,r0,#1              ;37
000036  4911              LDR      r1,|L1.124|
000038  7008              STRB     r0,[r1,#0]            ;37
00003a  2001              MOVS     r0,#1                 ;38
00003c  4911              LDR      r1,|L1.132|
00003e  7008              STRB     r0,[r1,#0]            ;38
                  |L1.64|
000040  2004              MOVS     r0,#4                 ;41
000042  4204              TST      r4,r0                 ;41
000044  d012              BEQ      |L1.108|
000046  480f              LDR      r0,|L1.132|
000048  7800              LDRB     r0,[r0,#0]            ;41  ; token
00004a  2801              CMP      r0,#1                 ;41
00004c  d10e              BNE      |L1.108|
00004e  480c              LDR      r0,|L1.128|
000050  6f40              LDR      r0,[r0,#0x74]         ;42
000052  1069              ASRS     r1,r5,#1              ;42
000054  00c9              LSLS     r1,r1,#3              ;42
000056  4a0c              LDR      r2,|L1.136|
000058  1889              ADDS     r1,r1,r2              ;42
00005a  6048              STR      r0,[r1,#4]            ;42
00005c  4807              LDR      r0,|L1.124|
00005e  7800              LDRB     r0,[r0,#0]            ;43  ; cap_index
000060  1c40              ADDS     r0,r0,#1              ;43
000062  4906              LDR      r1,|L1.124|
000064  7008              STRB     r0,[r1,#0]            ;43
000066  2000              MOVS     r0,#0                 ;44
000068  4906              LDR      r1,|L1.132|
00006a  7008              STRB     r0,[r1,#0]            ;44
                  |L1.108|
00006c  2206              MOVS     r2,#6                 ;48
00006e  2102              MOVS     r1,#2                 ;48
000070  4803              LDR      r0,|L1.128|
000072  f7fffffe          BL       PWM_ClearCaptureIntFlag
000076  bf00              NOP      
000078  e7c7              B        |L1.10|
;;;50     
                          ENDP

00007a  0000              DCW      0x0000
                  |L1.124|
                          DCD      cap_index
                  |L1.128|
                          DCD      0x40040000
                  |L1.132|
                          DCD      token
                  |L1.136|
                          DCD      cap_val

                          AREA ||i.SYS_Init||, CODE, READONLY, ALIGN=2

                  SYS_Init PROC
;;;53     /*---------------------------------------------------------------------------------------------------------*/
;;;54     void SYS_Init(void)
000000  b510              PUSH     {r4,lr}
;;;55     {
;;;56         /* Unlock protected registers */
;;;57         SYS_UnlockReg();
000002  f7fffffe          BL       SYS_UnlockReg
;;;58     
;;;59         /* Set HCLK source form HXT and HCLK source divide 1  */
;;;60         CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
000006  2100              MOVS     r1,#0
000008  4608              MOV      r0,r1
00000a  f7fffffe          BL       CLK_SetHCLK
;;;61     
;;;62         /* Enable external 12MHz HXT, 32KHz LXT and HIRC */
;;;63         CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);
00000e  2007              MOVS     r0,#7
000010  f7fffffe          BL       CLK_EnableXtalRC
;;;64     
;;;65         /* Waiting for clock ready */
;;;66         CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);
000014  2013              MOVS     r0,#0x13
000016  f7fffffe          BL       CLK_WaitClockReady
;;;67     
;;;68         /*  Set HCLK frequency 42MHz */
;;;69         CLK_SetCoreClock(42000000);
00001a  4827              LDR      r0,|L2.184|
00001c  f7fffffe          BL       CLK_SetCoreClock
;;;70     
;;;71         /* Enable IP clock */
;;;72         CLK_EnableModuleClock(UART0_MODULE);
000020  4826              LDR      r0,|L2.188|
000022  f7fffffe          BL       CLK_EnableModuleClock
;;;73     
;;;74         /* Enable PWM clock */
;;;75         CLK_EnableModuleClock(PWM0_CH01_MODULE);
000026  4826              LDR      r0,|L2.192|
000028  f7fffffe          BL       CLK_EnableModuleClock
;;;76         CLK_EnableModuleClock(PWM0_CH23_MODULE);
00002c  4825              LDR      r0,|L2.196|
00002e  f7fffffe          BL       CLK_EnableModuleClock
;;;77     
;;;78         /* Select IP clock source */
;;;79         CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_UART_CLK_DIVIDER(1));
000032  2200              MOVS     r2,#0
000034  4611              MOV      r1,r2
000036  4821              LDR      r0,|L2.188|
000038  f7fffffe          BL       CLK_SetModuleClock
;;;80     
;;;81         /* Set HCLK as PWM clock source */
;;;82         CLK_SetModuleClock(PWM0_CH01_MODULE, CLK_CLKSEL1_PWM0_CH01_S_HCLK, 0);
00003c  2200              MOVS     r2,#0
00003e  2120              MOVS     r1,#0x20
000040  481f              LDR      r0,|L2.192|
000042  f7fffffe          BL       CLK_SetModuleClock
;;;83         CLK_SetModuleClock(PWM0_CH23_MODULE, CLK_CLKSEL1_PWM0_CH23_S_HCLK, 0);
000046  2200              MOVS     r2,#0
000048  2180              MOVS     r1,#0x80
00004a  481e              LDR      r0,|L2.196|
00004c  f7fffffe          BL       CLK_SetModuleClock
;;;84     
;;;85     
;;;86         /*---------------------------------------------------------------------------------------------------------*/
;;;87         /* Init I/O Multi-function                                                                                 */
;;;88         /*---------------------------------------------------------------------------------------------------------*/
;;;89         /* Set PA multi-function pins for UART0 RXD and TXD */
;;;90         SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
000050  2005              MOVS     r0,#5
000052  0700              LSLS     r0,r0,#28
000054  6b80              LDR      r0,[r0,#0x38]
000056  2177              MOVS     r1,#0x77
000058  4388              BICS     r0,r0,r1
00005a  2105              MOVS     r1,#5
00005c  0709              LSLS     r1,r1,#28
00005e  6388              STR      r0,[r1,#0x38]
;;;91         SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_RX | SYS_PB_L_MFP_PB1_MFP_UART0_TX );
000060  4608              MOV      r0,r1
000062  6b80              LDR      r0,[r0,#0x38]
000064  2111              MOVS     r1,#0x11
000066  4308              ORRS     r0,r0,r1
000068  2105              MOVS     r1,#5
00006a  0709              LSLS     r1,r1,#28
00006c  6388              STR      r0,[r1,#0x38]
;;;92     
;;;93         /* Set PB multi-function pins for Clock Output */
;;;94         SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) |  SYS_PB_H_MFP_PB12_MFP_CKO;
00006e  4608              MOV      r0,r1
000070  6bc0              LDR      r0,[r0,#0x3c]
000072  2107              MOVS     r1,#7
000074  0409              LSLS     r1,r1,#16
000076  4388              BICS     r0,r0,r1
000078  2101              MOVS     r1,#1
00007a  0489              LSLS     r1,r1,#18
00007c  1840              ADDS     r0,r0,r1
00007e  2105              MOVS     r1,#5
000080  0709              LSLS     r1,r1,#28
000082  63c8              STR      r0,[r1,#0x3c]
;;;95     
;;;96         /* Set PA.12 and PA.14 multi-function pins for PWM channel 0 and 2 */
;;;97         SYS->PA_H_MFP = (SYS->PA_H_MFP & ~SYS_PA_H_MFP_PA12_MFP_Msk) | SYS_PA_H_MFP_PA12_MFP_PWM0_CH0;
000084  4608              MOV      r0,r1
000086  6b40              LDR      r0,[r0,#0x34]
000088  2107              MOVS     r1,#7
00008a  0409              LSLS     r1,r1,#16
00008c  4388              BICS     r0,r0,r1
00008e  2101              MOVS     r1,#1
000090  0409              LSLS     r1,r1,#16
000092  1840              ADDS     r0,r0,r1
000094  2105              MOVS     r1,#5
000096  0709              LSLS     r1,r1,#28
000098  6348              STR      r0,[r1,#0x34]
;;;98         SYS->PA_H_MFP = (SYS->PA_H_MFP & ~SYS_PA_H_MFP_PA14_MFP_Msk) | SYS_PA_H_MFP_PA14_MFP_PWM0_CH2;
00009a  4608              MOV      r0,r1
00009c  6b40              LDR      r0,[r0,#0x34]
00009e  2107              MOVS     r1,#7
0000a0  0609              LSLS     r1,r1,#24
0000a2  4388              BICS     r0,r0,r1
0000a4  2101              MOVS     r1,#1
0000a6  0609              LSLS     r1,r1,#24
0000a8  1840              ADDS     r0,r0,r1
0000aa  2105              MOVS     r1,#5
0000ac  0709              LSLS     r1,r1,#28
0000ae  6348              STR      r0,[r1,#0x34]
;;;99     
;;;100        /* Lock protected registers */
;;;101        SYS_LockReg();
0000b0  f7fffffe          BL       SYS_LockReg
;;;102    }
0000b4  bd10              POP      {r4,pc}
;;;103    
                          ENDP

0000b6  0000              DCW      0x0000
                  |L2.184|
                          DCD      0x0280de80
                  |L2.188|
                          DCD      0xa6003d10
                  |L2.192|
                          DCD      0xa6400014
                  |L2.196|
                          DCD      0xa6600015

                          AREA ||i.UART0_Init||, CODE, READONLY, ALIGN=2

                  UART0_Init PROC
;;;103    
;;;104    void UART0_Init()
000000  b510              PUSH     {r4,lr}
;;;105    {
;;;106        /*---------------------------------------------------------------------------------------------------------*/
;;;107        /* Init UART                                                                                               */
;;;108        /*---------------------------------------------------------------------------------------------------------*/
;;;109        UART_Open(UART0, 115200);
000002  21e1              MOVS     r1,#0xe1
000004  0249              LSLS     r1,r1,#9
000006  4802              LDR      r0,|L3.16|
000008  f7fffffe          BL       UART_Open
;;;110    }
00000c  bd10              POP      {r4,pc}
;;;111    
                          ENDP

00000e  0000              DCW      0x0000
                  |L3.16|
                          DCD      0x40050000

                          AREA ||i.main||, CODE, READONLY, ALIGN=2

                          REQUIRE _printf_percent
                          REQUIRE _printf_d
                          REQUIRE _printf_int_dec
                  main PROC
;;;111    
;;;112    int32_t main (void)
000000  f7fffffe          BL       SYS_Init
;;;113    {
;;;114        uint8_t i;
;;;115    
;;;116        /* Init System, IP clock and multi-function I/O
;;;117           In the end of SYS_Init() will issue SYS_LockReg()
;;;118           to lock protected register. If user want to write
;;;119           protected register, please issue SYS_UnlockReg()
;;;120           to unlock protected register if necessary */
;;;121        SYS_Init();
;;;122    
;;;123        /* Init UART to 115200-8n1 for print message */
;;;124        UART0_Init();
000004  f7fffffe          BL       UART0_Init
;;;125    
;;;126        printf("\nPWM0 channel 2 will capture the output of PWM0 channel 0\n");
000008  a028              ADR      r0,|L4.172|
00000a  f7fffffe          BL       __2printf
;;;127        printf("So, please connect GPIO port A12 with A14.\n");
00000e  a036              ADR      r0,|L4.232|
000010  f7fffffe          BL       __2printf
;;;128        // PWM0 frequency is 25000Hz, duty 30%,
;;;129        PWM_ConfigOutputChannel(PWM0, 0, 25000, 30);
000014  231e              MOVS     r3,#0x1e
000016  4a3f              LDR      r2,|L4.276|
000018  2100              MOVS     r1,#0
00001a  483f              LDR      r0,|L4.280|
00001c  f7fffffe          BL       PWM_ConfigOutputChannel
;;;130    
;;;131        // PWM2
;;;132        PWM_ConfigCaptureChannel(PWM0,2,50,1);
000020  2301              MOVS     r3,#1
000022  2232              MOVS     r2,#0x32
000024  2102              MOVS     r1,#2
000026  483c              LDR      r0,|L4.280|
000028  f7fffffe          BL       PWM_ConfigCaptureChannel
;;;133    
;;;134        // Enable output of channel 0
;;;135        PWM_EnableOutput(PWM0, PWM_CH_0_MASK);
00002c  2101              MOVS     r1,#1
00002e  483a              LDR      r0,|L4.280|
000030  f7fffffe          BL       PWM_EnableOutput
;;;136    
;;;137        // Enable capture of channel 2
;;;138        PWM_EnableCapture(PWM0, PWM_CH_2_MASK);
000034  2104              MOVS     r1,#4
000036  4838              LDR      r0,|L4.280|
000038  f7fffffe          BL       PWM_EnableCapture
;;;139    
;;;140        // Enable PWM channel 2 rising and falling edge capture interrupt
;;;141        PWM_EnableCaptureInt(PWM0,2,PWM_RISING_FALLING_LATCH_INT_ENABLE);
00003c  2203              MOVS     r2,#3
00003e  2102              MOVS     r1,#2
000040  4835              LDR      r0,|L4.280|
000042  f7fffffe          BL       PWM_EnableCaptureInt
;;;142        NVIC_EnableIRQ(PWM0_IRQn);
000046  2006              MOVS     r0,#6
000048  2101              MOVS     r1,#1
00004a  4081              LSLS     r1,r1,r0
00004c  4a33              LDR      r2,|L4.284|
00004e  6011              STR      r1,[r2,#0]
000050  bf00              NOP      
;;;143    
;;;144        // Start
;;;145        PWM_Start(PWM0, (PWM_CH_0_MASK|PWM_CH_2_MASK));
000052  2105              MOVS     r1,#5
000054  4830              LDR      r0,|L4.280|
000056  f7fffffe          BL       PWM_Start
;;;146    
;;;147        cap_index = 0;
00005a  2000              MOVS     r0,#0
00005c  4930              LDR      r1,|L4.288|
00005e  7008              STRB     r0,[r1,#0]
;;;148    
;;;149        while(cap_index < SAMPLE_CNT);
000060  bf00              NOP      
                  |L4.98|
000062  482f              LDR      r0,|L4.288|
000064  7800              LDRB     r0,[r0,#0]  ; cap_index
000066  2820              CMP      r0,#0x20
000068  dbfb              BLT      |L4.98|
;;;150    
;;;151        // Disable PWM channel 2 rising and falling edge capture interrupt
;;;152        PWM_DisableCaptureInt(PWM0,2,PWM_RISING_FALLING_LATCH_INT_ENABLE);
00006a  2203              MOVS     r2,#3
00006c  2102              MOVS     r1,#2
00006e  482a              LDR      r0,|L4.280|
000070  f7fffffe          BL       PWM_DisableCaptureInt
;;;153    
;;;154        // Stop
;;;155        PWM_Stop (PWM0, (PWM_CH_0_MASK|PWM_CH_2_MASK));
000074  2105              MOVS     r1,#5
000076  4828              LDR      r0,|L4.280|
000078  f7fffffe          BL       PWM_Stop
;;;156    
;;;157        printf("Captured data is as below.\n");
00007c  a029              ADR      r0,|L4.292|
00007e  f7fffffe          BL       __2printf
;;;158        printf("(rising : falling)\n");
000082  a02f              ADR      r0,|L4.320|
000084  f7fffffe          BL       __2printf
;;;159        for(i = 1; i < (SAMPLE_CNT  >> 1); i++) {  // ignore first sampled data. it's wrong
000088  2401              MOVS     r4,#1
00008a  e00b              B        |L4.164|
                  |L4.140|
;;;160            printf("%d, %d : %d\n", i, cap_val[i][0], cap_val[i][1]);
00008c  00e0              LSLS     r0,r4,#3
00008e  4931              LDR      r1,|L4.340|
000090  1840              ADDS     r0,r0,r1
000092  6843              LDR      r3,[r0,#4]
000094  00e0              LSLS     r0,r4,#3
000096  580a              LDR      r2,[r1,r0]
000098  4621              MOV      r1,r4
00009a  a02f              ADR      r0,|L4.344|
00009c  f7fffffe          BL       __2printf
0000a0  1c60              ADDS     r0,r4,#1              ;159
0000a2  b2c4              UXTB     r4,r0                 ;159
                  |L4.164|
0000a4  2c10              CMP      r4,#0x10              ;159
0000a6  dbf1              BLT      |L4.140|
;;;161        }
;;;162    
;;;163        while(1);
0000a8  bf00              NOP      
                  |L4.170|
0000aa  e7fe              B        |L4.170|
;;;164    
;;;165    
;;;166    }
;;;167    
                          ENDP

                  |L4.172|
0000ac  0a50574d          DCB      "\nPWM0 channel 2 will capture the output of PWM0 channe"
0000b0  30206368
0000b4  616e6e65
0000b8  6c203220
0000bc  77696c6c
0000c0  20636170
0000c4  74757265
0000c8  20746865
0000cc  206f7574
0000d0  70757420
0000d4  6f662050
0000d8  574d3020
0000dc  6368616e
0000e0  6e65    
0000e2  6c20300a          DCB      "l 0\n",0
0000e6  00      
0000e7  00                DCB      0
                  |L4.232|
0000e8  536f2c20          DCB      "So, please connect GPIO port A12 with A14.\n",0
0000ec  706c6561
0000f0  73652063
0000f4  6f6e6e65
0000f8  63742047
0000fc  50494f20
000100  706f7274
000104  20413132
000108  20776974
00010c  68204131
000110  342e0a00
                  |L4.276|
                          DCD      0x000061a8
                  |L4.280|
                          DCD      0x40040000
                  |L4.284|
                          DCD      0xe000e100
                  |L4.288|
                          DCD      cap_index
                  |L4.292|
000124  43617074          DCB      "Captured data is as below.\n",0
000128  75726564
00012c  20646174
000130  61206973
000134  20617320
000138  62656c6f
00013c  772e0a00
                  |L4.320|
000140  28726973          DCB      "(rising : falling)\n",0
000144  696e6720
000148  3a206661
00014c  6c6c696e
000150  67290a00
                  |L4.340|
                          DCD      cap_val
                  |L4.344|
000158  25642c20          DCB      "%d, %d : %d\n",0
00015c  2564203a
000160  2025640a
000164  00      
000165  00                DCB      0
000166  00                DCB      0
000167  00                DCB      0

                          AREA ||.bss||, DATA, NOINIT, ALIGN=2

                  cap_val
                          %        128

                          AREA ||.data||, DATA, ALIGN=0

                  token
000000  00                DCB      0x00
                  cap_index
000001  00                DCB      0x00

;*** Start embedded assembler ***

#line 1 "..\\main.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___6_main_c_78832d56____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___6_main_c_78832d56____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___6_main_c_78832d56____REVSH|
#line 132
|__asm___6_main_c_78832d56____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***

                  __ARM_use_no_argv EQU 0
