; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\pwm.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\pwm.d --feedback=.\obj\PWM_Capture.fed --cpu=Cortex-M0 --apcs=interwork -O0 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\Nano100Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\pwm.crf ..\..\..\..\Library\StdDriver\src\pwm.c]
                          THUMB

                          AREA ||i.PWM_ClearCaptureIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_ClearCaptureIntFlag PROC
;;;409     */
;;;410    void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
000000  b510              PUSH     {r4,lr}
;;;411    {
;;;412        // disable capture interrupt flag
;;;413        pwm->CAPINTSTS = (u32Edge + 1)  << (u32ChannelNum * 8);
000002  00cc              LSLS     r4,r1,#3
000004  1c53              ADDS     r3,r2,#1
000006  40a3              LSLS     r3,r3,r4
000008  65c3              STR      r3,[r0,#0x5c]
;;;414    }
00000a  bd10              POP      {r4,pc}
;;;415    
                          ENDP


                          AREA ||i.PWM_ClearPeriodIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_ClearPeriodIntFlag PROC
;;;461     */
;;;462    void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  2201              MOVS     r2,#1
;;;463    {
;;;464        // write 1 clear
;;;465        pwm->INTSTS = (PWM_INTSTS_TMINT0_Msk << u32ChannelNum);
000002  408a              LSLS     r2,r2,r1
000004  6102              STR      r2,[r0,#0x10]
;;;466    }
000006  4770              BX       lr
;;;467    
                          ENDP


                          AREA ||i.PWM_ConfigCaptureChannel||, CODE, READONLY, ALIGN=2

                  PWM_ConfigCaptureChannel PROC
;;;136     */
;;;137    uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
000000  b5ff              PUSH     {r0-r7,lr}
;;;138                                       uint32_t u32ChannelNum,
;;;139                                       uint32_t u32UnitTimeNsec,
;;;140                                       uint32_t u32CaptureEdge)
;;;141    {
000002  b085              SUB      sp,sp,#0x14
000004  4605              MOV      r5,r0
000006  460c              MOV      r4,r1
;;;142        uint32_t i;
;;;143        uint32_t u32ClkSrc;
;;;144        uint32_t u32PWM_Clock = SystemCoreClock;
000008  4863              LDR      r0,|L3.408|
00000a  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00000c  9003              STR      r0,[sp,#0xc]
;;;145        uint8_t  u8Divider = 1, u8Prescale = 0xFF;
00000e  2601              MOVS     r6,#1
000010  20ff              MOVS     r0,#0xff
000012  9002              STR      r0,[sp,#8]
;;;146        uint16_t u16CNR = 0xFFFF;
000014  4861              LDR      r0,|L3.412|
000016  9001              STR      r0,[sp,#4]
;;;147    
;;;148        if(pwm == PWM0)
000018  4861              LDR      r0,|L3.416|
00001a  4285              CMP      r5,r0
00001c  d10d              BNE      |L3.58|
;;;149            u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2));
00001e  4861              LDR      r0,|L3.420|
000020  6940              LDR      r0,[r0,#0x14]
000022  2102              MOVS     r1,#2
000024  4021              ANDS     r1,r1,r4
000026  2230              MOVS     r2,#0x30
000028  408a              LSLS     r2,r2,r1
00002a  4010              ANDS     r0,r0,r2
00002c  4621              MOV      r1,r4
00002e  2202              MOVS     r2,#2
000030  4011              ANDS     r1,r1,r2
000032  1d09              ADDS     r1,r1,#4
000034  40c8              LSRS     r0,r0,r1
000036  9004              STR      r0,[sp,#0x10]
000038  e00c              B        |L3.84|
                  |L3.58|
;;;150        else
;;;151            u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2));
00003a  485a              LDR      r0,|L3.420|
00003c  6980              LDR      r0,[r0,#0x18]
00003e  2102              MOVS     r1,#2
000040  4021              ANDS     r1,r1,r4
000042  2230              MOVS     r2,#0x30
000044  408a              LSLS     r2,r2,r1
000046  4010              ANDS     r0,r0,r2
000048  4621              MOV      r1,r4
00004a  2202              MOVS     r2,#2
00004c  4011              ANDS     r1,r1,r2
00004e  1d09              ADDS     r1,r1,#4
000050  40c8              LSRS     r0,r0,r1
000052  9004              STR      r0,[sp,#0x10]
                  |L3.84|
;;;152    
;;;153        switch (u32ClkSrc) {
000054  9804              LDR      r0,[sp,#0x10]
000056  2800              CMP      r0,#0
000058  d006              BEQ      |L3.104|
00005a  2801              CMP      r0,#1
00005c  d007              BEQ      |L3.110|
00005e  2802              CMP      r0,#2
000060  d009              BEQ      |L3.118|
000062  2803              CMP      r0,#3
000064  d10e              BNE      |L3.132|
000066  e00a              B        |L3.126|
                  |L3.104|
;;;154        case 0:
;;;155            u32PWM_Clock = __HXT;
000068  484f              LDR      r0,|L3.424|
00006a  9003              STR      r0,[sp,#0xc]
;;;156            break;
00006c  e00a              B        |L3.132|
                  |L3.110|
;;;157        case 1:
;;;158            u32PWM_Clock = __LXT;
00006e  2001              MOVS     r0,#1
000070  03c0              LSLS     r0,r0,#15
000072  9003              STR      r0,[sp,#0xc]
;;;159            break;
000074  e006              B        |L3.132|
                  |L3.118|
;;;160        case 2:
;;;161            u32PWM_Clock = SystemCoreClock;
000076  4848              LDR      r0,|L3.408|
000078  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00007a  9003              STR      r0,[sp,#0xc]
;;;162            break;
00007c  e002              B        |L3.132|
                  |L3.126|
;;;163        case 3:
;;;164            u32PWM_Clock = __HIRC12M;
00007e  484a              LDR      r0,|L3.424|
000080  9003              STR      r0,[sp,#0xc]
;;;165            break;
000082  bf00              NOP      
                  |L3.132|
000084  bf00              NOP                            ;156
;;;166        }
;;;167    
;;;168        for(; u8Divider < 17; u8Divider <<= 1) {  // clk divider could only be 1, 2, 4, 8, 16
000086  e017              B        |L3.184|
                  |L3.136|
;;;169            i = ((u32PWM_Clock / u8Divider) * u32UnitTimeNsec) / 1000000000;
000088  4631              MOV      r1,r6
00008a  9803              LDR      r0,[sp,#0xc]
00008c  f7fffffe          BL       __aeabi_uidivmod
000090  9907              LDR      r1,[sp,#0x1c]
000092  4348              MULS     r0,r1,r0
000094  4945              LDR      r1,|L3.428|
000096  9000              STR      r0,[sp,#0]
000098  f7fffffe          BL       __aeabi_uidivmod
00009c  4607              MOV      r7,r0
;;;170    
;;;171            // If target value is larger than 0xFF, need to use a larger divider
;;;172            if(i > (0xFF))
00009e  2fff              CMP      r7,#0xff
0000a0  d900              BLS      |L3.164|
;;;173                continue;
0000a2  e007              B        |L3.180|
                  |L3.164|
;;;174    
;;;175            u8Prescale = i;
0000a4  b2f8              UXTB     r0,r7
0000a6  9002              STR      r0,[sp,#8]
;;;176    
;;;177            // u8Prescale must at least be 2, otherwise the output stop
;;;178            if(u8Prescale < 3)
0000a8  9802              LDR      r0,[sp,#8]
0000aa  2803              CMP      r0,#3
0000ac  da01              BGE      |L3.178|
;;;179                u8Prescale = 2;
0000ae  2002              MOVS     r0,#2
0000b0  9002              STR      r0,[sp,#8]
                  |L3.178|
;;;180    
;;;181            break;
0000b2  e003              B        |L3.188|
                  |L3.180|
0000b4  0670              LSLS     r0,r6,#25             ;168
0000b6  0e06              LSRS     r6,r0,#24             ;168
                  |L3.184|
0000b8  2e11              CMP      r6,#0x11              ;168
0000ba  dbe5              BLT      |L3.136|
                  |L3.188|
0000bc  bf00              NOP      
;;;182        }
;;;183    
;;;184        // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
;;;185        i = (u8Prescale * u8Divider) * 1000000000 / u32PWM_Clock;
0000be  9902              LDR      r1,[sp,#8]
0000c0  4371              MULS     r1,r6,r1
0000c2  4a3a              LDR      r2,|L3.428|
0000c4  4351              MULS     r1,r2,r1
0000c6  4608              MOV      r0,r1
0000c8  9903              LDR      r1,[sp,#0xc]
0000ca  f7fffffe          BL       __aeabi_uidivmod
0000ce  4607              MOV      r7,r0
;;;186    
;;;187        u8Prescale -= 1;
0000d0  9802              LDR      r0,[sp,#8]
0000d2  1e40              SUBS     r0,r0,#1
0000d4  b2c0              UXTB     r0,r0
0000d6  9002              STR      r0,[sp,#8]
;;;188        u16CNR -= 1;
0000d8  9801              LDR      r0,[sp,#4]
0000da  1e40              SUBS     r0,r0,#1
0000dc  b280              UXTH     r0,r0
0000de  9001              STR      r0,[sp,#4]
;;;189        // convert to real register value
;;;190        if(u8Divider == 1)
0000e0  2e01              CMP      r6,#1
0000e2  d101              BNE      |L3.232|
;;;191            u8Divider = 4;
0000e4  2604              MOVS     r6,#4
0000e6  e00c              B        |L3.258|
                  |L3.232|
;;;192        else if (u8Divider == 2)
0000e8  2e02              CMP      r6,#2
0000ea  d101              BNE      |L3.240|
;;;193            u8Divider = 0;
0000ec  2600              MOVS     r6,#0
0000ee  e008              B        |L3.258|
                  |L3.240|
;;;194        else if (u8Divider == 4)
0000f0  2e04              CMP      r6,#4
0000f2  d101              BNE      |L3.248|
;;;195            u8Divider = 1;
0000f4  2601              MOVS     r6,#1
0000f6  e004              B        |L3.258|
                  |L3.248|
;;;196        else if (u8Divider == 8)
0000f8  2e08              CMP      r6,#8
0000fa  d101              BNE      |L3.256|
;;;197            u8Divider = 2;
0000fc  2602              MOVS     r6,#2
0000fe  e000              B        |L3.258|
                  |L3.256|
;;;198        else // 16
;;;199            u8Divider = 3;
000100  2603              MOVS     r6,#3
                  |L3.258|
;;;200    
;;;201        // every two channels share a prescaler
;;;202        while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk);
000102  bf00              NOP      
                  |L3.260|
000104  6928              LDR      r0,[r5,#0x10]
000106  21ff              MOVS     r1,#0xff
000108  3101              ADDS     r1,#1
00010a  4008              ANDS     r0,r0,r1
00010c  4288              CMP      r0,r1
00010e  d0f9              BEQ      |L3.260|
;;;203        pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
000110  6828              LDR      r0,[r5,#0]
000112  0861              LSRS     r1,r4,#1
000114  00ca              LSLS     r2,r1,#3
000116  21ff              MOVS     r1,#0xff
000118  4091              LSLS     r1,r1,r2
00011a  4388              BICS     r0,r0,r1
00011c  0861              LSRS     r1,r4,#1
00011e  00ca              LSLS     r2,r1,#3
000120  9902              LDR      r1,[sp,#8]
000122  4091              LSLS     r1,r1,r2
000124  4308              ORRS     r0,r0,r1
000126  6028              STR      r0,[r5,#0]
;;;204        pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
000128  6868              LDR      r0,[r5,#4]
00012a  00a2              LSLS     r2,r4,#2
00012c  2107              MOVS     r1,#7
00012e  4091              LSLS     r1,r1,r2
000130  4388              BICS     r0,r0,r1
000132  00a2              LSLS     r2,r4,#2
000134  4631              MOV      r1,r6
000136  4091              LSLS     r1,r1,r2
000138  4308              ORRS     r0,r0,r1
00013a  6068              STR      r0,[r5,#4]
;;;205        pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
00013c  68a8              LDR      r0,[r5,#8]
00013e  00e2              LSLS     r2,r4,#3
000140  2108              MOVS     r1,#8
000142  4091              LSLS     r1,r1,r2
000144  4308              ORRS     r0,r0,r1
000146  60a8              STR      r0,[r5,#8]
;;;206        while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum));
000148  bf00              NOP      
                  |L3.330|
00014a  6928              LDR      r0,[r5,#0x10]
00014c  2110              MOVS     r1,#0x10
00014e  40a1              LSLS     r1,r1,r4
000150  4008              ANDS     r0,r0,r1
000152  2110              MOVS     r1,#0x10
000154  40a1              LSLS     r1,r1,r4
000156  4288              CMP      r0,r1
000158  d0f7              BEQ      |L3.330|
;;;207        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
00015a  0060              LSLS     r0,r4,#1
00015c  1820              ADDS     r0,r4,r0
00015e  0081              LSLS     r1,r0,#2
000160  4628              MOV      r0,r5
000162  301c              ADDS     r0,r0,#0x1c
000164  5840              LDR      r0,[r0,r1]
000166  0c01              LSRS     r1,r0,#16
000168  0409              LSLS     r1,r1,#16
00016a  0060              LSLS     r0,r4,#1
00016c  1820              ADDS     r0,r4,r0
00016e  0082              LSLS     r2,r0,#2
000170  4628              MOV      r0,r5
000172  301c              ADDS     r0,r0,#0x1c
000174  5081              STR      r1,[r0,r2]
;;;208        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
000176  0060              LSLS     r0,r4,#1
000178  1820              ADDS     r0,r4,r0
00017a  0081              LSLS     r1,r0,#2
00017c  4628              MOV      r0,r5
00017e  301c              ADDS     r0,r0,#0x1c
000180  5840              LDR      r0,[r0,r1]
000182  9901              LDR      r1,[sp,#4]
000184  4308              ORRS     r0,r0,r1
000186  0061              LSLS     r1,r4,#1
000188  1861              ADDS     r1,r4,r1
00018a  008a              LSLS     r2,r1,#2
00018c  4629              MOV      r1,r5
00018e  311c              ADDS     r1,r1,#0x1c
000190  5088              STR      r0,[r1,r2]
;;;209    
;;;210        return(i);
000192  4638              MOV      r0,r7
;;;211    }
000194  b009              ADD      sp,sp,#0x24
000196  bdf0              POP      {r4-r7,pc}
;;;212    
                          ENDP

                  |L3.408|
                          DCD      SystemCoreClock
                  |L3.412|
                          DCD      0x0000ffff
                  |L3.416|
                          DCD      0x40040000
                  |L3.420|
                          DCD      0x50000200
                  |L3.424|
                          DCD      0x00b71b00
                  |L3.428|
                          DCD      0x3b9aca00

                          AREA ||i.PWM_ConfigOutputChannel||, CODE, READONLY, ALIGN=2

                  PWM_ConfigOutputChannel PROC
;;;35      */
;;;36     uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
000000  b5ff              PUSH     {r0-r7,lr}
;;;37                                       uint32_t u32ChannelNum,
;;;38                                       uint32_t u32Frequency,
;;;39                                       uint32_t u32DutyCycle)
;;;40     {
000002  b085              SUB      sp,sp,#0x14
000004  4605              MOV      r5,r0
000006  460c              MOV      r4,r1
;;;41         uint32_t i;
;;;42         uint32_t u32ClkSrc;
;;;43         uint32_t u32PWM_Clock = SystemCoreClock;
000008  4888              LDR      r0,|L4.556|
00000a  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00000c  9003              STR      r0,[sp,#0xc]
;;;44         uint8_t  u8Divider = 1, u8Prescale = 0xFF;
00000e  2601              MOVS     r6,#1
000010  20ff              MOVS     r0,#0xff
000012  9002              STR      r0,[sp,#8]
;;;45         uint16_t u16CNR = 0xFFFF;
000014  4886              LDR      r0,|L4.560|
000016  9001              STR      r0,[sp,#4]
;;;46     
;;;47         if(pwm == PWM0)
000018  4886              LDR      r0,|L4.564|
00001a  4285              CMP      r5,r0
00001c  d10d              BNE      |L4.58|
;;;48             u32ClkSrc = (CLK->CLKSEL1 & (CLK_CLKSEL1_PWM0_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL1_PWM0_CH01_S_Pos + (u32ChannelNum & 2));
00001e  4886              LDR      r0,|L4.568|
000020  6940              LDR      r0,[r0,#0x14]
000022  2102              MOVS     r1,#2
000024  4021              ANDS     r1,r1,r4
000026  2230              MOVS     r2,#0x30
000028  408a              LSLS     r2,r2,r1
00002a  4010              ANDS     r0,r0,r2
00002c  4621              MOV      r1,r4
00002e  2202              MOVS     r2,#2
000030  4011              ANDS     r1,r1,r2
000032  1d09              ADDS     r1,r1,#4
000034  40c8              LSRS     r0,r0,r1
000036  9004              STR      r0,[sp,#0x10]
000038  e00c              B        |L4.84|
                  |L4.58|
;;;49     
;;;50         else
;;;51             u32ClkSrc = (CLK->CLKSEL2 & (CLK_CLKSEL2_PWM1_CH01_S_Msk << (u32ChannelNum & 2))) >> (CLK_CLKSEL2_PWM1_CH01_S_Pos + (u32ChannelNum & 2));
00003a  487f              LDR      r0,|L4.568|
00003c  6980              LDR      r0,[r0,#0x18]
00003e  2102              MOVS     r1,#2
000040  4021              ANDS     r1,r1,r4
000042  2230              MOVS     r2,#0x30
000044  408a              LSLS     r2,r2,r1
000046  4010              ANDS     r0,r0,r2
000048  4621              MOV      r1,r4
00004a  2202              MOVS     r2,#2
00004c  4011              ANDS     r1,r1,r2
00004e  1d09              ADDS     r1,r1,#4
000050  40c8              LSRS     r0,r0,r1
000052  9004              STR      r0,[sp,#0x10]
                  |L4.84|
;;;52     
;;;53         switch (u32ClkSrc) {
000054  9804              LDR      r0,[sp,#0x10]
000056  2800              CMP      r0,#0
000058  d006              BEQ      |L4.104|
00005a  2801              CMP      r0,#1
00005c  d007              BEQ      |L4.110|
00005e  2802              CMP      r0,#2
000060  d009              BEQ      |L4.118|
000062  2803              CMP      r0,#3
000064  d10e              BNE      |L4.132|
000066  e00a              B        |L4.126|
                  |L4.104|
;;;54         case 0:
;;;55             u32PWM_Clock = __HXT;
000068  4874              LDR      r0,|L4.572|
00006a  9003              STR      r0,[sp,#0xc]
;;;56             break;
00006c  e00a              B        |L4.132|
                  |L4.110|
;;;57         case 1:
;;;58             u32PWM_Clock = __LXT;
00006e  2001              MOVS     r0,#1
000070  03c0              LSLS     r0,r0,#15
000072  9003              STR      r0,[sp,#0xc]
;;;59             break;
000074  e006              B        |L4.132|
                  |L4.118|
;;;60         case 2:
;;;61             u32PWM_Clock = SystemCoreClock;
000076  486d              LDR      r0,|L4.556|
000078  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
00007a  9003              STR      r0,[sp,#0xc]
;;;62             break;
00007c  e002              B        |L4.132|
                  |L4.126|
;;;63         case 3:
;;;64             u32PWM_Clock = __HIRC12M;
00007e  486f              LDR      r0,|L4.572|
000080  9003              STR      r0,[sp,#0xc]
;;;65             break;
000082  bf00              NOP      
                  |L4.132|
000084  bf00              NOP                            ;56
;;;66         }
;;;67     
;;;68         for(; u8Divider < 17; u8Divider <<= 1) {  // clk divider could only be 1, 2, 4, 8, 16
000086  e02b              B        |L4.224|
                  |L4.136|
;;;69             i = (u32PWM_Clock / u32Frequency) / u8Divider;
000088  9907              LDR      r1,[sp,#0x1c]
00008a  9803              LDR      r0,[sp,#0xc]
00008c  f7fffffe          BL       __aeabi_uidivmod
000090  4631              MOV      r1,r6
000092  9000              STR      r0,[sp,#0]
000094  f7fffffe          BL       __aeabi_uidivmod
000098  4607              MOV      r7,r0
;;;70             // If target value is larger than CNR * prescale, need to use a larger divider
;;;71             if(i > (0x10000 * 0x100))
00009a  2001              MOVS     r0,#1
00009c  0600              LSLS     r0,r0,#24
00009e  4287              CMP      r7,r0
0000a0  d900              BLS      |L4.164|
;;;72                 continue;
0000a2  e01b              B        |L4.220|
                  |L4.164|
;;;73     
;;;74             // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
;;;75             u8Prescale = (i + 0xFFFF)/ 0x10000;
0000a4  4862              LDR      r0,|L4.560|
0000a6  1838              ADDS     r0,r7,r0
0000a8  0200              LSLS     r0,r0,#8
0000aa  0e00              LSRS     r0,r0,#24
0000ac  9002              STR      r0,[sp,#8]
;;;76     
;;;77             // u8Prescale must at least be 2, otherwise the output stop
;;;78             if(u8Prescale < 3)
0000ae  9802              LDR      r0,[sp,#8]
0000b0  2803              CMP      r0,#3
0000b2  da01              BGE      |L4.184|
;;;79                 u8Prescale = 2;
0000b4  2002              MOVS     r0,#2
0000b6  9002              STR      r0,[sp,#8]
                  |L4.184|
;;;80     
;;;81             i /= u8Prescale;
0000b8  4638              MOV      r0,r7
0000ba  9902              LDR      r1,[sp,#8]
0000bc  f7fffffe          BL       __aeabi_uidivmod
0000c0  4607              MOV      r7,r0
;;;82     
;;;83             if(i <= 0x10000) {
0000c2  2001              MOVS     r0,#1
0000c4  0400              LSLS     r0,r0,#16
0000c6  4287              CMP      r7,r0
0000c8  d807              BHI      |L4.218|
;;;84                 if(i == 1)
0000ca  2f01              CMP      r7,#1
0000cc  d102              BNE      |L4.212|
;;;85                     u16CNR = 1;     // Too fast, and PWM cannot generate expected frequency...
0000ce  2001              MOVS     r0,#1
0000d0  9001              STR      r0,[sp,#4]
0000d2  e001              B        |L4.216|
                  |L4.212|
;;;86                 else
;;;87                     u16CNR = i;
0000d4  b2b8              UXTH     r0,r7
0000d6  9001              STR      r0,[sp,#4]
                  |L4.216|
;;;88                 break;
0000d8  e004              B        |L4.228|
                  |L4.218|
0000da  bf00              NOP                            ;72
                  |L4.220|
0000dc  0670              LSLS     r0,r6,#25             ;68
0000de  0e06              LSRS     r6,r0,#24             ;68
                  |L4.224|
0000e0  2e11              CMP      r6,#0x11              ;68
0000e2  dbd1              BLT      |L4.136|
                  |L4.228|
0000e4  bf00              NOP      
;;;89             }
;;;90     
;;;91         }
;;;92         // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
;;;93         i = u32PWM_Clock / (u8Prescale * u8Divider * u16CNR);
0000e6  9802              LDR      r0,[sp,#8]
0000e8  4370              MULS     r0,r6,r0
0000ea  9a01              LDR      r2,[sp,#4]
0000ec  4350              MULS     r0,r2,r0
0000ee  4601              MOV      r1,r0
0000f0  9803              LDR      r0,[sp,#0xc]
0000f2  f7fffffe          BL       __aeabi_uidivmod
0000f6  4607              MOV      r7,r0
;;;94     
;;;95         u8Prescale -= 1;
0000f8  9802              LDR      r0,[sp,#8]
0000fa  1e40              SUBS     r0,r0,#1
0000fc  b2c0              UXTB     r0,r0
0000fe  9002              STR      r0,[sp,#8]
;;;96         u16CNR -= 1;
000100  9801              LDR      r0,[sp,#4]
000102  1e40              SUBS     r0,r0,#1
000104  b280              UXTH     r0,r0
000106  9001              STR      r0,[sp,#4]
;;;97         // convert to real register value
;;;98         if(u8Divider == 1)
000108  2e01              CMP      r6,#1
00010a  d101              BNE      |L4.272|
;;;99             u8Divider = 4;
00010c  2604              MOVS     r6,#4
00010e  e00c              B        |L4.298|
                  |L4.272|
;;;100        else if (u8Divider == 2)
000110  2e02              CMP      r6,#2
000112  d101              BNE      |L4.280|
;;;101            u8Divider = 0;
000114  2600              MOVS     r6,#0
000116  e008              B        |L4.298|
                  |L4.280|
;;;102        else if (u8Divider == 4)
000118  2e04              CMP      r6,#4
00011a  d101              BNE      |L4.288|
;;;103            u8Divider = 1;
00011c  2601              MOVS     r6,#1
00011e  e004              B        |L4.298|
                  |L4.288|
;;;104        else if (u8Divider == 8)
000120  2e08              CMP      r6,#8
000122  d101              BNE      |L4.296|
;;;105            u8Divider = 2;
000124  2602              MOVS     r6,#2
000126  e000              B        |L4.298|
                  |L4.296|
;;;106        else // 16
;;;107            u8Divider = 3;
000128  2603              MOVS     r6,#3
                  |L4.298|
;;;108    
;;;109        // every two channels share a prescaler
;;;110        while((pwm->INTSTS & PWM_INTSTS_PRESSYNC_Msk ) == PWM_INTSTS_PRESSYNC_Msk);
00012a  bf00              NOP      
                  |L4.300|
00012c  6928              LDR      r0,[r5,#0x10]
00012e  21ff              MOVS     r1,#0xff
000130  3101              ADDS     r1,#1
000132  4008              ANDS     r0,r0,r1
000134  4288              CMP      r0,r1
000136  d0f9              BEQ      |L4.300|
;;;111        pwm->PRES = (pwm->PRES & ~(PWM_PRES_CP01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
000138  6828              LDR      r0,[r5,#0]
00013a  0861              LSRS     r1,r4,#1
00013c  00ca              LSLS     r2,r1,#3
00013e  21ff              MOVS     r1,#0xff
000140  4091              LSLS     r1,r1,r2
000142  4388              BICS     r0,r0,r1
000144  0861              LSRS     r1,r4,#1
000146  00ca              LSLS     r2,r1,#3
000148  9902              LDR      r1,[sp,#8]
00014a  4091              LSLS     r1,r1,r2
00014c  4308              ORRS     r0,r0,r1
00014e  6028              STR      r0,[r5,#0]
;;;112        pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
000150  6868              LDR      r0,[r5,#4]
000152  00a2              LSLS     r2,r4,#2
000154  2107              MOVS     r1,#7
000156  4091              LSLS     r1,r1,r2
000158  4388              BICS     r0,r0,r1
00015a  00a2              LSLS     r2,r4,#2
00015c  4631              MOV      r1,r6
00015e  4091              LSLS     r1,r1,r2
000160  4308              ORRS     r0,r0,r1
000162  6068              STR      r0,[r5,#4]
;;;113        pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
000164  68a9              LDR      r1,[r5,#8]
000166  00e2              LSLS     r2,r4,#3
000168  2008              MOVS     r0,#8
00016a  4090              LSLS     r0,r0,r2
00016c  4301              ORRS     r1,r1,r0
00016e  60a9              STR      r1,[r5,#8]
;;;114        while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum));
000170  bf00              NOP      
                  |L4.370|
000172  6928              LDR      r0,[r5,#0x10]
000174  2110              MOVS     r1,#0x10
000176  40a1              LSLS     r1,r1,r4
000178  4008              ANDS     r0,r0,r1
00017a  2110              MOVS     r1,#0x10
00017c  40a1              LSLS     r1,r1,r4
00017e  4288              CMP      r0,r1
000180  d0f7              BEQ      |L4.370|
;;;115        if(u32DutyCycle == 0)
000182  9808              LDR      r0,[sp,#0x20]
000184  2800              CMP      r0,#0
000186  d10d              BNE      |L4.420|
;;;116            *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
000188  0060              LSLS     r0,r4,#1
00018a  1820              ADDS     r0,r4,r0
00018c  0081              LSLS     r1,r0,#2
00018e  4628              MOV      r0,r5
000190  301c              ADDS     r0,r0,#0x1c
000192  5840              LDR      r0,[r0,r1]
000194  b281              UXTH     r1,r0
000196  0060              LSLS     r0,r4,#1
000198  1820              ADDS     r0,r4,r0
00019a  0082              LSLS     r2,r0,#2
00019c  4628              MOV      r0,r5
00019e  301c              ADDS     r0,r0,#0x1c
0001a0  5081              STR      r1,[r0,r2]
0001a2  e023              B        |L4.492|
                  |L4.420|
;;;117        else {
;;;118            *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
0001a4  0060              LSLS     r0,r4,#1
0001a6  1820              ADDS     r0,r4,r0
0001a8  0081              LSLS     r1,r0,#2
0001aa  4628              MOV      r0,r5
0001ac  301c              ADDS     r0,r0,#0x1c
0001ae  5840              LDR      r0,[r0,r1]
0001b0  b281              UXTH     r1,r0
0001b2  0060              LSLS     r0,r4,#1
0001b4  1820              ADDS     r0,r4,r0
0001b6  0082              LSLS     r2,r0,#2
0001b8  4628              MOV      r0,r5
0001ba  301c              ADDS     r0,r0,#0x1c
0001bc  5081              STR      r1,[r0,r2]
;;;119            *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 100 - 1) << PWM_DUTY_CM_Pos);
0001be  9a01              LDR      r2,[sp,#4]
0001c0  1c52              ADDS     r2,r2,#1
0001c2  9908              LDR      r1,[sp,#0x20]
0001c4  4351              MULS     r1,r2,r1
0001c6  4608              MOV      r0,r1
0001c8  2164              MOVS     r1,#0x64
0001ca  f7fffffe          BL       __aeabi_uidivmod
0001ce  1e40              SUBS     r0,r0,#1
0001d0  0400              LSLS     r0,r0,#16
0001d2  0061              LSLS     r1,r4,#1
0001d4  1861              ADDS     r1,r4,r1
0001d6  008a              LSLS     r2,r1,#2
0001d8  4629              MOV      r1,r5
0001da  311c              ADDS     r1,r1,#0x1c
0001dc  5889              LDR      r1,[r1,r2]
0001de  4308              ORRS     r0,r0,r1
0001e0  0061              LSLS     r1,r4,#1
0001e2  1861              ADDS     r1,r4,r1
0001e4  008a              LSLS     r2,r1,#2
0001e6  4629              MOV      r1,r5
0001e8  311c              ADDS     r1,r1,#0x1c
0001ea  5088              STR      r0,[r1,r2]
                  |L4.492|
;;;120        }
;;;121        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
0001ec  0060              LSLS     r0,r4,#1
0001ee  1820              ADDS     r0,r4,r0
0001f0  0081              LSLS     r1,r0,#2
0001f2  4628              MOV      r0,r5
0001f4  301c              ADDS     r0,r0,#0x1c
0001f6  5840              LDR      r0,[r0,r1]
0001f8  0c01              LSRS     r1,r0,#16
0001fa  0409              LSLS     r1,r1,#16
0001fc  0060              LSLS     r0,r4,#1
0001fe  1820              ADDS     r0,r4,r0
000200  0082              LSLS     r2,r0,#2
000202  4628              MOV      r0,r5
000204  301c              ADDS     r0,r0,#0x1c
000206  5081              STR      r1,[r0,r2]
;;;122        *(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
000208  0060              LSLS     r0,r4,#1
00020a  1820              ADDS     r0,r4,r0
00020c  0081              LSLS     r1,r0,#2
00020e  4628              MOV      r0,r5
000210  301c              ADDS     r0,r0,#0x1c
000212  5840              LDR      r0,[r0,r1]
000214  9901              LDR      r1,[sp,#4]
000216  4308              ORRS     r0,r0,r1
000218  0061              LSLS     r1,r4,#1
00021a  1861              ADDS     r1,r4,r1
00021c  008a              LSLS     r2,r1,#2
00021e  4629              MOV      r1,r5
000220  311c              ADDS     r1,r1,#0x1c
000222  5088              STR      r0,[r1,r2]
;;;123    
;;;124        return(i);
000224  4638              MOV      r0,r7
;;;125    }
000226  b009              ADD      sp,sp,#0x24
000228  bdf0              POP      {r4-r7,pc}
;;;126    
                          ENDP

00022a  0000              DCW      0x0000
                  |L4.556|
                          DCD      SystemCoreClock
                  |L4.560|
                          DCD      0x0000ffff
                  |L4.564|
                          DCD      0x40040000
                  |L4.568|
                          DCD      0x50000200
                  |L4.572|
                          DCD      0x00b71b00

                          AREA ||i.PWM_DisableCapture||, CODE, READONLY, ALIGN=1

                  PWM_DisableCapture PROC
;;;294     */
;;;295    void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b570              PUSH     {r4-r6,lr}
;;;296    {
000002  460a              MOV      r2,r1
;;;297        uint8_t i;
;;;298        uint32_t u32CTLMask = 0;
000004  2300              MOVS     r3,#0
;;;299        uint32_t u32CAPCTLMask = 0;
000006  2400              MOVS     r4,#0
;;;300    
;;;301        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
000008  2100              MOVS     r1,#0
00000a  e00d              B        |L5.40|
                  |L5.12|
;;;302            if ( u32ChannelMask  & (1 << i)) {
00000c  2501              MOVS     r5,#1
00000e  408d              LSLS     r5,r5,r1
000010  4215              TST      r5,r2
000012  d007              BEQ      |L5.36|
;;;303                u32CTLMask |= (PWM_CTL_CH0EN_Msk << (i * 8));
000014  00ce              LSLS     r6,r1,#3
000016  2501              MOVS     r5,#1
000018  40b5              LSLS     r5,r5,r6
00001a  432b              ORRS     r3,r3,r5
;;;304                u32CAPCTLMask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
00001c  00ce              LSLS     r6,r1,#3
00001e  2506              MOVS     r5,#6
000020  40b5              LSLS     r5,r5,r6
000022  432c              ORRS     r4,r4,r5
                  |L5.36|
000024  1c4d              ADDS     r5,r1,#1              ;301
000026  b2e9              UXTB     r1,r5                 ;301
                  |L5.40|
000028  2904              CMP      r1,#4                 ;301
00002a  dbef              BLT      |L5.12|
;;;305            }
;;;306        }
;;;307    
;;;308        pwm->CTL &= ~u32CTLMask;
00002c  6885              LDR      r5,[r0,#8]
00002e  439d              BICS     r5,r5,r3
000030  6085              STR      r5,[r0,#8]
;;;309        pwm->CAPCTL &= ~u32CAPCTLMask;
000032  6d45              LDR      r5,[r0,#0x54]
000034  43a5              BICS     r5,r5,r4
000036  6545              STR      r5,[r0,#0x54]
;;;310    }
000038  bd70              POP      {r4-r6,pc}
;;;311    
                          ENDP


                          AREA ||i.PWM_DisableCaptureInt||, CODE, READONLY, ALIGN=1

                  PWM_DisableCaptureInt PROC
;;;393     */
;;;394    void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
000000  b530              PUSH     {r4,r5,lr}
;;;395    {
;;;396        // disable capture interrupt
;;;397        pwm->CAPINTEN &= ~(u32Edge << (u32ChannelNum * 8));
000002  6d83              LDR      r3,[r0,#0x58]
000004  00cd              LSLS     r5,r1,#3
000006  4614              MOV      r4,r2
000008  40ac              LSLS     r4,r4,r5
00000a  43a3              BICS     r3,r3,r4
00000c  6583              STR      r3,[r0,#0x58]
;;;398    }
00000e  bd30              POP      {r4,r5,pc}
;;;399    
                          ENDP


                          AREA ||i.PWM_DisableDeadZone||, CODE, READONLY, ALIGN=1

                  PWM_DisableDeadZone PROC
;;;359     */
;;;360    void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
000000  0849              LSRS     r1,r1,#1
;;;361    {
;;;362        // every two channels shares the same setting
;;;363        u32ChannelNum >>= 1;
;;;364        // enable dead zone
;;;365        pwm->CTL &= ~(PWM_CTL_DZEN01_Msk << u32ChannelNum);
000002  6882              LDR      r2,[r0,#8]
000004  2310              MOVS     r3,#0x10
000006  408b              LSLS     r3,r3,r1
000008  439a              BICS     r2,r2,r3
00000a  6082              STR      r2,[r0,#8]
;;;366    }
00000c  4770              BX       lr
;;;367    
                          ENDP


                          AREA ||i.PWM_DisableOutput||, CODE, READONLY, ALIGN=1

                  PWM_DisableOutput PROC
;;;330     */
;;;331    void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
000000  6942              LDR      r2,[r0,#0x14]
;;;332    {
;;;333        pwm->OE &= ~u32ChannelMask;
000002  438a              BICS     r2,r2,r1
000004  6142              STR      r2,[r0,#0x14]
;;;334    }
000006  4770              BX       lr
;;;335    
                          ENDP


                          AREA ||i.PWM_DisablePDMA||, CODE, READONLY, ALIGN=1

                  PWM_DisablePDMA PROC
;;;507     */
;;;508    void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
000000  2900              CMP      r1,#0
;;;509    {
;;;510        if (u32ChannelNum == 0)
000002  d104              BNE      |L9.14|
;;;511            pwm->CAPCTL &= ~PWM_CAPCTL_CH0PDMAEN_Msk;
000004  6d42              LDR      r2,[r0,#0x54]
000006  2308              MOVS     r3,#8
000008  439a              BICS     r2,r2,r3
00000a  6542              STR      r2,[r0,#0x54]
00000c  e004              B        |L9.24|
                  |L9.14|
;;;512        else
;;;513            pwm->CAPCTL &= ~PWM_CAPCTL_CH2PDMAEN_Msk;
00000e  6d42              LDR      r2,[r0,#0x54]
000010  2301              MOVS     r3,#1
000012  04db              LSLS     r3,r3,#19
000014  439a              BICS     r2,r2,r3
000016  6542              STR      r2,[r0,#0x54]
                  |L9.24|
;;;514    }
000018  4770              BX       lr
;;;515    
                          ENDP


                          AREA ||i.PWM_DisablePeriodInt||, CODE, READONLY, ALIGN=1

                  PWM_DisablePeriodInt PROC
;;;450     */
;;;451    void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
000000  68c2              LDR      r2,[r0,#0xc]
;;;452    {
;;;453        pwm->INTEN &= ~(PWM_INTEN_TMIE0_Msk << u32ChannelNum);
000002  2301              MOVS     r3,#1
000004  408b              LSLS     r3,r3,r1
000006  439a              BICS     r2,r2,r3
000008  60c2              STR      r2,[r0,#0xc]
;;;454    }
00000a  4770              BX       lr
;;;455    
                          ENDP


                          AREA ||i.PWM_EnableCapture||, CODE, READONLY, ALIGN=1

                  PWM_EnableCapture PROC
;;;273     */
;;;274    void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;275    {
000002  4602              MOV      r2,r0
;;;276        uint8_t i;
;;;277        uint32_t u32Mask = 0;
000004  2300              MOVS     r3,#0
;;;278    
;;;279        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
000006  2000              MOVS     r0,#0
000008  e009              B        |L11.30|
                  |L11.10|
;;;280            if ( u32ChannelMask  & (1 << i)) {
00000a  2401              MOVS     r4,#1
00000c  4084              LSLS     r4,r4,r0
00000e  420c              TST      r4,r1
000010  d003              BEQ      |L11.26|
;;;281                u32Mask |= ((PWM_CAPCTL_CAPCH0EN_Msk | PWM_CAPCTL_CAPCH0PADEN_Msk) << (i * 8));
000012  00c5              LSLS     r5,r0,#3
000014  2406              MOVS     r4,#6
000016  40ac              LSLS     r4,r4,r5
000018  4323              ORRS     r3,r3,r4
                  |L11.26|
00001a  1c44              ADDS     r4,r0,#1              ;279
00001c  b2e0              UXTB     r0,r4                 ;279
                  |L11.30|
00001e  2804              CMP      r0,#4                 ;279
000020  dbf3              BLT      |L11.10|
;;;282            }
;;;283        }
;;;284    
;;;285        pwm->CAPCTL |= u32Mask;
000022  6d54              LDR      r4,[r2,#0x54]
000024  431c              ORRS     r4,r4,r3
000026  6554              STR      r4,[r2,#0x54]
;;;286    }
000028  bd30              POP      {r4,r5,pc}
;;;287    
                          ENDP


                          AREA ||i.PWM_EnableCaptureInt||, CODE, READONLY, ALIGN=1

                  PWM_EnableCaptureInt PROC
;;;377     */
;;;378    void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
000000  b530              PUSH     {r4,r5,lr}
;;;379    {
;;;380        // enable capture interrupt
;;;381        pwm->CAPINTEN |= (u32Edge << (u32ChannelNum * 8));
000002  6d83              LDR      r3,[r0,#0x58]
000004  00cd              LSLS     r5,r1,#3
000006  4614              MOV      r4,r2
000008  40ac              LSLS     r4,r4,r5
00000a  4323              ORRS     r3,r3,r4
00000c  6583              STR      r3,[r0,#0x58]
;;;382    }
00000e  bd30              POP      {r4,r5,pc}
;;;383    
                          ENDP


                          AREA ||i.PWM_EnableDeadZone||, CODE, READONLY, ALIGN=1

                  PWM_EnableDeadZone PROC
;;;343     */
;;;344    void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
000000  b530              PUSH     {r4,r5,lr}
;;;345    {
;;;346        // every two channels shares the same setting
;;;347        u32ChannelNum >>= 1;
000002  0849              LSRS     r1,r1,#1
;;;348        // set duration
;;;349        pwm->PRES = (pwm->PRES & ~(PWM_PRES_DZ01_Msk << (8 * u32ChannelNum))) | ((u32Duration << PWM_PRES_DZ01_Pos ) << (8 * u32ChannelNum));
000004  6803              LDR      r3,[r0,#0]
000006  00cd              LSLS     r5,r1,#3
000008  24ff              MOVS     r4,#0xff
00000a  0424              LSLS     r4,r4,#16
00000c  40ac              LSLS     r4,r4,r5
00000e  43a3              BICS     r3,r3,r4
000010  0414              LSLS     r4,r2,#16
000012  00cd              LSLS     r5,r1,#3
000014  40ac              LSLS     r4,r4,r5
000016  4323              ORRS     r3,r3,r4
000018  6003              STR      r3,[r0,#0]
;;;350        // enable dead zone
;;;351        pwm->CTL |= (PWM_CTL_DZEN01_Msk << u32ChannelNum);
00001a  6883              LDR      r3,[r0,#8]
00001c  2410              MOVS     r4,#0x10
00001e  408c              LSLS     r4,r4,r1
000020  4323              ORRS     r3,r3,r4
000022  6083              STR      r3,[r0,#8]
;;;352    }
000024  bd30              POP      {r4,r5,pc}
;;;353    
                          ENDP


                          AREA ||i.PWM_EnableOutput||, CODE, READONLY, ALIGN=1

                  PWM_EnableOutput PROC
;;;318     */
;;;319    void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
000000  6942              LDR      r2,[r0,#0x14]
;;;320    {
;;;321        pwm->OE |= u32ChannelMask;
000002  430a              ORRS     r2,r2,r1
000004  6142              STR      r2,[r0,#0x14]
;;;322    }
000006  4770              BX       lr
;;;323    
                          ENDP


                          AREA ||i.PWM_EnablePDMA||, CODE, READONLY, ALIGN=2

                  PWM_EnablePDMA PROC
;;;493     */
;;;494    void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
000000  b530              PUSH     {r4,r5,lr}
;;;495    {
;;;496        if (u32ChannelNum == 0)
000002  2900              CMP      r1,#0
000004  d108              BNE      |L15.24|
;;;497            pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD0_Msk | PWM_CAPCTL_CH0RFORDER_Msk)) | u32Mode | u32RisingFirst | PWM_CAPCTL_CH0PDMAEN_Msk;
000006  6d44              LDR      r4,[r0,#0x54]
000008  4d09              LDR      r5,|L15.48|
00000a  402c              ANDS     r4,r4,r5
00000c  431c              ORRS     r4,r4,r3
00000e  4314              ORRS     r4,r4,r2
000010  2508              MOVS     r5,#8
000012  432c              ORRS     r4,r4,r5
000014  6544              STR      r4,[r0,#0x54]
000016  e00a              B        |L15.46|
                  |L15.24|
;;;498        else
;;;499            pwm->CAPCTL = (pwm->CAPCTL & ~(PWM_CAPCTL_PDMACAPMOD2_Msk | PWM_CAPCTL_CH2RFORDER_Msk)) | (u32Mode << 16)| (u32RisingFirst << 16)| PWM_CAPCTL_CH2PDMAEN_Msk;
000018  6d44              LDR      r4,[r0,#0x54]
00001a  4d06              LDR      r5,|L15.52|
00001c  402c              ANDS     r4,r4,r5
00001e  041d              LSLS     r5,r3,#16
000020  432c              ORRS     r4,r4,r5
000022  0415              LSLS     r5,r2,#16
000024  432c              ORRS     r4,r4,r5
000026  2501              MOVS     r5,#1
000028  04ed              LSLS     r5,r5,#19
00002a  432c              ORRS     r4,r4,r5
00002c  6544              STR      r4,[r0,#0x54]
                  |L15.46|
;;;500    }
00002e  bd30              POP      {r4,r5,pc}
;;;501    
                          ENDP

                  |L15.48|
                          DCD      0xffffefcf
                  |L15.52|
                          DCD      0xefcfffff

                          AREA ||i.PWM_EnablePeriodInt||, CODE, READONLY, ALIGN=1

                  PWM_EnablePeriodInt PROC
;;;438     */
;;;439    void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
000000  b510              PUSH     {r4,lr}
;;;440    {
;;;441        // enable period interrupt
;;;442        pwm->INTEN |= (PWM_INTEN_TMIE0_Msk << u32ChannelNum);
000002  68c3              LDR      r3,[r0,#0xc]
000004  2401              MOVS     r4,#1
000006  408c              LSLS     r4,r4,r1
000008  4323              ORRS     r3,r3,r4
00000a  60c3              STR      r3,[r0,#0xc]
;;;443    }
00000c  bd10              POP      {r4,pc}
;;;444    
                          ENDP


                          AREA ||i.PWM_ForceStop||, CODE, READONLY, ALIGN=1

                  PWM_ForceStop PROC
;;;257     */
;;;258    void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;259    {
000002  4602              MOV      r2,r0
;;;260        uint32_t i;
;;;261        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
000004  2000              MOVS     r0,#0
000006  e00a              B        |L17.30|
                  |L17.8|
;;;262            if ( u32ChannelMask  & (1 << i))
000008  2301              MOVS     r3,#1
00000a  4083              LSLS     r3,r3,r0
00000c  420b              TST      r3,r1
00000e  d005              BEQ      |L17.28|
;;;263                pwm->CTL &= ~(PWM_CTL_CH0EN_Msk << (i * 8));
000010  6894              LDR      r4,[r2,#8]
000012  00c5              LSLS     r5,r0,#3
000014  2301              MOVS     r3,#1
000016  40ab              LSLS     r3,r3,r5
000018  439c              BICS     r4,r4,r3
00001a  6094              STR      r4,[r2,#8]
                  |L17.28|
00001c  1c40              ADDS     r0,r0,#1              ;261
                  |L17.30|
00001e  2804              CMP      r0,#4                 ;261
000020  d3f2              BCC      |L17.8|
;;;264        }
;;;265    }
000022  bd30              POP      {r4,r5,pc}
;;;266    
                          ENDP


                          AREA ||i.PWM_GetCaptureIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_GetCaptureIntFlag PROC
;;;425     */
;;;426    uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4602              MOV      r2,r0
;;;427    {
;;;428        return ((pwm->CAPINTSTS >> (u32ChannelNum * 8)) & (PWM_RISING_FALLING_LATCH_INT_FLAG));
000002  6dd0              LDR      r0,[r2,#0x5c]
000004  00cb              LSLS     r3,r1,#3
000006  40d8              LSRS     r0,r0,r3
000008  2306              MOVS     r3,#6
00000a  4018              ANDS     r0,r0,r3
;;;429    }
00000c  4770              BX       lr
;;;430    
                          ENDP


                          AREA ||i.PWM_GetPeriodIntFlag||, CODE, READONLY, ALIGN=1

                  PWM_GetPeriodIntFlag PROC
;;;475     */
;;;476    uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
000000  4602              MOV      r2,r0
;;;477    {
;;;478        return ((pwm->INTSTS & (PWM_INTSTS_TMINT0_Msk << u32ChannelNum)) ? 1 : 0);
000002  6910              LDR      r0,[r2,#0x10]
000004  2301              MOVS     r3,#1
000006  408b              LSLS     r3,r3,r1
000008  4218              TST      r0,r3
00000a  d001              BEQ      |L19.16|
00000c  2001              MOVS     r0,#1
                  |L19.14|
;;;479    }
00000e  4770              BX       lr
                  |L19.16|
000010  2000              MOVS     r0,#0                 ;478
000012  e7fc              B        |L19.14|
;;;480    
                          ENDP


                          AREA ||i.PWM_Start||, CODE, READONLY, ALIGN=1

                  PWM_Start PROC
;;;219     */
;;;220    void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;221    {
000002  4602              MOV      r2,r0
;;;222        uint8_t i;
;;;223        uint32_t u32Mask = 0;
000004  2300              MOVS     r3,#0
;;;224    
;;;225        for (i = 0; i < PWM_CHANNEL_NUM; i++) {
000006  2000              MOVS     r0,#0
000008  e009              B        |L20.30|
                  |L20.10|
;;;226            if ( u32ChannelMask  & (1 << i))
00000a  2401              MOVS     r4,#1
00000c  4084              LSLS     r4,r4,r0
00000e  420c              TST      r4,r1
000010  d003              BEQ      |L20.26|
;;;227                u32Mask |= (PWM_CTL_CH0EN_Msk << (i * 8));
000012  00c5              LSLS     r5,r0,#3
000014  2401              MOVS     r4,#1
000016  40ac              LSLS     r4,r4,r5
000018  4323              ORRS     r3,r3,r4
                  |L20.26|
00001a  1c44              ADDS     r4,r0,#1              ;225
00001c  b2e0              UXTB     r0,r4                 ;225
                  |L20.30|
00001e  2804              CMP      r0,#4                 ;225
000020  dbf3              BLT      |L20.10|
;;;228        }
;;;229    
;;;230        pwm->CTL |= u32Mask;
000022  6894              LDR      r4,[r2,#8]
000024  431c              ORRS     r4,r4,r3
000026  6094              STR      r4,[r2,#8]
;;;231    }
000028  bd30              POP      {r4,r5,pc}
;;;232    
                          ENDP


                          AREA ||i.PWM_Stop||, CODE, READONLY, ALIGN=1

                  PWM_Stop PROC
;;;239     */
;;;240    void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
000000  b530              PUSH     {r4,r5,lr}
;;;241    {
000002  4602              MOV      r2,r0
;;;242        uint32_t i;
;;;243        for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
000004  2000              MOVS     r0,#0
000006  e012              B        |L21.46|
                  |L21.8|
;;;244            if(u32ChannelMask & (1 << i)) {
000008  2301              MOVS     r3,#1
00000a  4083              LSLS     r3,r3,r0
00000c  420b              TST      r3,r1
00000e  d00d              BEQ      |L21.44|
;;;245                *(__IO uint32_t *) (&pwm->DUTY0 + 3 * i) &= ~PWM_DUTY_CN_Msk;
000010  0043              LSLS     r3,r0,#1
000012  18c3              ADDS     r3,r0,r3
000014  009c              LSLS     r4,r3,#2
000016  4613              MOV      r3,r2
000018  331c              ADDS     r3,r3,#0x1c
00001a  591b              LDR      r3,[r3,r4]
00001c  0c1c              LSRS     r4,r3,#16
00001e  0424              LSLS     r4,r4,#16
000020  0043              LSLS     r3,r0,#1
000022  18c3              ADDS     r3,r0,r3
000024  009d              LSLS     r5,r3,#2
000026  4613              MOV      r3,r2
000028  331c              ADDS     r3,r3,#0x1c
00002a  515c              STR      r4,[r3,r5]
                  |L21.44|
00002c  1c40              ADDS     r0,r0,#1              ;243
                  |L21.46|
00002e  2804              CMP      r0,#4                 ;243
000030  d3ea              BCC      |L21.8|
;;;246            }
;;;247        }
;;;248    
;;;249    }
000032  bd30              POP      {r4,r5,pc}
;;;250    
                          ENDP


;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\pwm.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_pwm_c_03ee09af____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___5_pwm_c_03ee09af____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___5_pwm_c_03ee09af____REVSH|
#line 132
|__asm___5_pwm_c_03ee09af____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
