; generated by ARM C/C++ Compiler, 4.1 [Build 894]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\system_nano100series.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\system_nano100series.d --feedback=.\obj\PWM_Capture.fed --cpu=Cortex-M0 --apcs=interwork -O0 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\Nano100Series\Include -I..\..\..\..\Library\StdDriver\inc -IC:\Keil\ARM\RV31\Inc -IC:\Keil\ARM\CMSIS\Include -D__MICROLIB --omf_browse=.\obj\system_nano100series.crf ..\..\..\..\Library\Device\Nuvoton\Nano100Series\Source\system_Nano100Series.c]
                          THUMB

                          AREA ||i.SysGet_HCLKFreq||, CODE, READONLY, ALIGN=2

                  SysGet_HCLKFreq PROC
;;;64       */
;;;65     uint32_t SysGet_HCLKFreq(void)
000000  b570              PUSH     {r4-r6,lr}
;;;66     {
;;;67     
;;;68         uint32_t u32Freqout, u32AHBDivider, u32ClkSel;
;;;69     
;;;70         u32ClkSel = CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk;
000002  4810              LDR      r0,|L1.68|
000004  6900              LDR      r0,[r0,#0x10]
000006  0745              LSLS     r5,r0,#29
000008  0f6d              LSRS     r5,r5,#29
;;;71     
;;;72         if (u32ClkSel == CLK_CLKSEL0_HCLK_S_HXT) {  /* external HXT crystal clock */
00000a  2d00              CMP      r5,#0
00000c  d101              BNE      |L1.18|
;;;73             u32Freqout = __HXT;
00000e  4c0e              LDR      r4,|L1.72|
000010  e00e              B        |L1.48|
                  |L1.18|
;;;74         } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LXT) {    /* external LXT crystal clock */
000012  2d01              CMP      r5,#1
000014  d101              BNE      |L1.26|
;;;75             u32Freqout = __LXT;
000016  03ec              LSLS     r4,r5,#15
000018  e00a              B        |L1.48|
                  |L1.26|
;;;76         } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_PLL) {    /* PLL clock */
00001a  2d02              CMP      r5,#2
00001c  d103              BNE      |L1.38|
;;;77             u32Freqout = SysGet_PLLClockFreq();
00001e  f7fffffe          BL       SysGet_PLLClockFreq
000022  4604              MOV      r4,r0
000024  e004              B        |L1.48|
                  |L1.38|
;;;78         } else if(u32ClkSel == CLK_CLKSEL0_HCLK_S_LIRC) { /* internal LIRC oscillator clock */
000026  2d03              CMP      r5,#3
000028  d101              BNE      |L1.46|
;;;79             u32Freqout = __LIRC;
00002a  4c08              LDR      r4,|L1.76|
00002c  e000              B        |L1.48|
                  |L1.46|
;;;80         } else {                                /* internal HIRC oscillator clock */
;;;81             u32Freqout = __HIRC12M;
00002e  4c06              LDR      r4,|L1.72|
                  |L1.48|
;;;82         }
;;;83         u32AHBDivider = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLK_N_Msk) + 1 ;
000030  4804              LDR      r0,|L1.68|
000032  69c0              LDR      r0,[r0,#0x1c]
000034  0700              LSLS     r0,r0,#28
000036  0f00              LSRS     r0,r0,#28
000038  1c46              ADDS     r6,r0,#1
;;;84     
;;;85         return (u32Freqout/u32AHBDivider);
00003a  4631              MOV      r1,r6
00003c  4620              MOV      r0,r4
00003e  f7fffffe          BL       __aeabi_uidivmod
;;;86     }
000042  bd70              POP      {r4-r6,pc}
;;;87     
                          ENDP

                  |L1.68|
                          DCD      0x50000200
                  |L1.72|
                          DCD      0x00b71b00
                  |L1.76|
                          DCD      0x00002710

                          AREA ||i.SysGet_PLLClockFreq||, CODE, READONLY, ALIGN=2

                  SysGet_PLLClockFreq PROC
;;;26       */
;;;27     uint32_t SysGet_PLLClockFreq(void)
000000  b5fe              PUSH     {r1-r7,lr}
;;;28     {
;;;29         uint32_t u32Freq =0, u32PLLSrc;
000002  2000              MOVS     r0,#0
000004  9002              STR      r0,[sp,#8]
;;;30         uint32_t u32NO, u32NR, u32IN_DV, u32PllReg;
;;;31     
;;;32         u32PllReg = CLK->PLLCTL;
000006  481b              LDR      r0,|L2.116|
000008  6a45              LDR      r5,[r0,#0x24]
;;;33     
;;;34         if (u32PllReg & CLK_PLLCTL_PD)
00000a  01c0              LSLS     r0,r0,#7
00000c  4205              TST      r5,r0
00000e  d001              BEQ      |L2.20|
;;;35             return 0;    /* PLL is in power down mode */
000010  2000              MOVS     r0,#0
                  |L2.18|
;;;36     
;;;37         if (u32PllReg & CLK_PLLCTL_PLL_SRC_Msk)
;;;38             u32PLLSrc = __HIRC12M;
;;;39         else
;;;40             u32PLLSrc = __HXT;
;;;41     
;;;42         u32NO = (u32PllReg & CLK_PLLCTL_OUT_DV) ? 2: 1;
;;;43     
;;;44         u32IN_DV = (u32PllReg & CLK_PLLCTL_IN_DV_Msk) >> 8;
;;;45         if (u32IN_DV == 0)
;;;46             u32NR = 2;
;;;47         else if (u32IN_DV == 1)
;;;48             u32NR = 4;
;;;49         else if (u32IN_DV == 2)
;;;50             u32NR = 8;
;;;51         else
;;;52             u32NR = 16;
;;;53     
;;;54         u32Freq = u32PLLSrc * ((u32PllReg & CLK_PLLCTL_FB_DV_Msk) +32) / u32NR / u32NO;
;;;55     
;;;56         return u32Freq;
;;;57     }
000012  bdfe              POP      {r1-r7,pc}
                  |L2.20|
000014  2001              MOVS     r0,#1                 ;37
000016  0440              LSLS     r0,r0,#17             ;37
000018  4205              TST      r5,r0                 ;37
00001a  d001              BEQ      |L2.32|
00001c  4f16              LDR      r7,|L2.120|
00001e  e000              B        |L2.34|
                  |L2.32|
000020  4f15              LDR      r7,|L2.120|
                  |L2.34|
000022  2001              MOVS     r0,#1                 ;42
000024  0300              LSLS     r0,r0,#12             ;42
000026  4205              TST      r5,r0                 ;42
000028  d001              BEQ      |L2.46|
00002a  2002              MOVS     r0,#2                 ;42
00002c  e000              B        |L2.48|
                  |L2.46|
00002e  2001              MOVS     r0,#1                 ;42
                  |L2.48|
000030  9001              STR      r0,[sp,#4]            ;42
000032  2003              MOVS     r0,#3                 ;44
000034  0200              LSLS     r0,r0,#8              ;44
000036  4028              ANDS     r0,r0,r5              ;44
000038  0a06              LSRS     r6,r0,#8              ;44
00003a  2e00              CMP      r6,#0                 ;45
00003c  d101              BNE      |L2.66|
00003e  2402              MOVS     r4,#2                 ;46
000040  e008              B        |L2.84|
                  |L2.66|
000042  2e01              CMP      r6,#1                 ;47
000044  d101              BNE      |L2.74|
000046  2404              MOVS     r4,#4                 ;48
000048  e004              B        |L2.84|
                  |L2.74|
00004a  2e02              CMP      r6,#2                 ;49
00004c  d101              BNE      |L2.82|
00004e  2408              MOVS     r4,#8                 ;50
000050  e000              B        |L2.84|
                  |L2.82|
000052  2410              MOVS     r4,#0x10              ;52
                  |L2.84|
000054  06e9              LSLS     r1,r5,#27             ;54
000056  0ec9              LSRS     r1,r1,#27             ;54
000058  3120              ADDS     r1,r1,#0x20           ;54
00005a  4379              MULS     r1,r7,r1              ;54
00005c  4608              MOV      r0,r1                 ;54
00005e  4621              MOV      r1,r4                 ;54
000060  f7fffffe          BL       __aeabi_uidivmod
000064  9000              STR      r0,[sp,#0]            ;54
000066  9901              LDR      r1,[sp,#4]            ;54
000068  f7fffffe          BL       __aeabi_uidivmod
00006c  9002              STR      r0,[sp,#8]            ;54
00006e  9802              LDR      r0,[sp,#8]            ;56
000070  e7cf              B        |L2.18|
;;;58     
                          ENDP

000072  0000              DCW      0x0000
                  |L2.116|
                          DCD      0x50000200
                  |L2.120|
                          DCD      0x00b71b00

                          AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2

                  SystemCoreClockUpdate PROC
;;;95     
;;;96     void SystemCoreClockUpdate (void)
000000  b510              PUSH     {r4,lr}
;;;97     {
;;;98     
;;;99         SystemCoreClock = SysGet_HCLKFreq();
000002  f7fffffe          BL       SysGet_HCLKFreq
000006  4906              LDR      r1,|L3.32|
000008  6008              STR      r0,[r1,#0]  ; SystemCoreClock
;;;100        CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
00000a  4906              LDR      r1,|L3.36|
00000c  4804              LDR      r0,|L3.32|
00000e  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
000010  104a              ASRS     r2,r1,#1
000012  1880              ADDS     r0,r0,r2
000014  f7fffffe          BL       __aeabi_uidivmod
000018  4903              LDR      r1,|L3.40|
00001a  6008              STR      r0,[r1,#0]  ; CyclesPerUs
;;;101    }
00001c  bd10              POP      {r4,pc}
;;;102    
                          ENDP

00001e  0000              DCW      0x0000
                  |L3.32|
                          DCD      SystemCoreClock
                  |L3.36|
                          DCD      0x000f4240
                  |L3.40|
                          DCD      CyclesPerUs

                          AREA ||.data||, DATA, ALIGN=2

                  SystemCoreClock
                          DCD      0x00b71b00
                  CyclesPerUs
                          DCD      0x0000000c

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\Device\\Nuvoton\\Nano100Series\\Source\\system_Nano100Series.c"
	AREA ||.rev16_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___22_system_Nano100Series_c_5d646a67____REV16|
#line 118 "..\\..\\..\\..\\Library\\CMSIS\\Include\\core_cmInstr.h"
|__asm___22_system_Nano100Series_c_5d646a67____REV16| PROC
#line 119

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE, READONLY
	THUMB
	EXPORT |__asm___22_system_Nano100Series_c_5d646a67____REVSH|
#line 132
|__asm___22_system_Nano100Series_c_5d646a67____REVSH| PROC
#line 133

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
