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发表于 2022-11-7 08:50:54
SYS_UnlockReg();
/* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
/* Enable External XTAL (4~24 MHz) */
CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; //
/* Waiting for 4MHz clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Switch HCLK clock source to XTAL */
CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLKSEL_Msk;
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_HXT;
/* Set PCLK0/PCLK1 to HCLK/2 */
//CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2);
CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV1 | CLK_PCLKDIV_APB1DIV_DIV1);
我是这么写的,但仿真中看到的是12M系统时钟,是哪里写错了还是芯片不支持4M系统时钟?
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