| 我的以下CLK为啥不行?: /* Unlock protected registers */
 //SYS_UnlockReg();
 
 /* Enable clock source */
 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
 
 /* Waiting for clock source ready */
 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
 
 /* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */
 /* Set HCLK clock */
 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));
 
 /* Set PCLK-related clock */
 CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV1 | CLK_PCLKDIV_APB1DIV_DIV1);
 
 /* Enable IP clock */
 
 /* Update System Core Clock */
 /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
 //SystemCoreClockUpdate();
 /* Enable RTC module clock */
 CLK_EnableModuleClock(RTC_MODULE);
 
 CLK_EnableModuleClock(EADC_MODULE);
 CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(0));
 /* Enable PDMA clock source */
 CLK_EnableModuleClock(PDMA0_MODULE);
 /* Enable TIMER module clock */
 CLK_EnableModuleClock(TMR0_MODULE);
 CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);
 /* Enable TIMER module clock */
 CLK_EnableModuleClock(TMR1_MODULE);
 CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_HXT, 0);//ssp
 /* Enable TIMER module clock */
 CLK_EnableModuleClock(TMR2_MODULE);
 CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HXT, 0);
 /* Enable UART module clock */
 CLK_EnableModuleClock(UART0_MODULE);
 /* Select UART module clock source as HXT and UART module clock divider as 1 */
 CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
 /* Enable WDT module clock */
 CLK_EnableModuleClock(WDT_MODULE);
 CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0);
 /* Lock protected registers */
 //SYS_LockReg();
 
 debug后出现CLK寄存器错误:
 AGDI-WARNING:failed to read memory at 0x40000230一直到0x400002B4
 |